diff options
| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2014-06-22 14:33:09 -0700 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2014-06-22 14:33:09 -0700 |
| commit | 5b08e211ab35fd6d936dafda45014c78b5e68300 (patch) | |
| tree | 771950b6f1e0c775d83a5f03f2387f2e3850cc58 /tests/long/fs | |
| parent | b085db84afcbb4824d34b8755f4c09c1fcfefcee (diff) | |
| download | gem5-5b08e211ab35fd6d936dafda45014c78b5e68300.tar.xz | |
stats: update for O3 changes
Mostly small differences in total ticks, but O3 stall causes
shifted significantly.
30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex
by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8%
slower.
Diffstat (limited to 'tests/long/fs')
41 files changed, 14309 insertions, 14147 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini index 01fef3e75..69d3e7023 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini @@ -15,17 +15,18 @@ boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 cache_line_size=64 clk_domain=system.clk_domain -console=/dist/binaries/console +console=/home/stever/m5/m5_system_2.0b3/binaries/console eventq_index=0 init_param=0 -kernel=/dist/binaries/vmlinux +kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -pal=/dist/binaries/ts_osfpal -readfile=tests/halt.sh +pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal +readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh symbolfile= system_rev=1024 system_type=34 @@ -131,6 +132,7 @@ smtLSQThreshold=100 smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 +socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false @@ -636,6 +638,7 @@ smtLSQThreshold=100 smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 +socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false @@ -1091,7 +1094,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/disks/linux-latest.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img read_only=true [system.disk2] @@ -1114,7 +1117,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/disks/linux-bigswap2.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -1235,9 +1238,9 @@ warn_access= pio=system.membus.default [system.physmem] -type=SimpleDRAM +type=DRAMCtrl activation_limit=4 -addr_mapping=RaBaChCo +addr_mapping=RoRaBaChCo banks_per_rank=8 burst_length=8 channels=1 @@ -1248,27 +1251,33 @@ device_rowbuffer_size=1024 devices_per_rank=8 eventq_index=0 in_addr_map=true +max_accesses_per_row=16 mem_sched_policy=frfcfs +min_writes_per_switch=16 null=false -page_policy=open +page_policy=open_adaptive range=0:134217727 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 +tCK=1250 tCL=13750 tRAS=35000 tRCD=13750 tREFI=7800000 -tRFC=300000 +tRFC=260000 tRP=13750 -tRRD=6250 +tRRD=6000 +tRTP=7500 +tRTW=2500 +tWR=15000 tWTR=7500 -tXAW=40000 -write_buffer_size=32 -write_high_thresh_perc=70 -write_low_thresh_perc=0 +tXAW=30000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 port=system.membus.master[1] [system.simple_disk] @@ -1281,7 +1290,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage eventq_index=0 -image_file=/dist/disks/linux-latest.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr index 20fe2d682..c0d08bdf9 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr @@ -2,3 +2,4 @@ warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything +warn: Obsolete M5 ivlb instruction encountered. diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout index d125f29b8..d865b26f6 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout @@ -1,13 +1,15 @@ +Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual/simout +Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 16:27:55 -gem5 started Jan 22 2014 19:30:57 -gem5 executing on u200540-lin -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual +gem5 compiled Jun 21 2014 10:36:29 +gem5 started Jun 21 2014 13:05:58 +gem5 executing on phenom +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/binaries/vmlinux +info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -info: Launching CPU 1 @ 126320000 -Exiting @ tick 1903338216000 because m5_exit instruction encountered +info: Launching CPU 1 @ 121062000 +Exiting @ tick 1906207240000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 5cabf17a2..2b53a578a 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,139 +1,139 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.905651 # Number of seconds simulated -sim_ticks 1905651402000 # Number of ticks simulated -final_tick 1905651402000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.906207 # Number of seconds simulated +sim_ticks 1906207240000 # Number of ticks simulated +final_tick 1906207240000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 124387 # Simulator instruction rate (inst/s) -host_op_rate 124387 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4179760275 # Simulator tick rate (ticks/s) -host_mem_usage 352908 # Number of bytes of host memory used -host_seconds 455.92 # Real time elapsed on the host -sim_insts 56710998 # Number of instructions simulated -sim_ops 56710998 # Number of ops (including micro ops) simulated +host_inst_rate 147655 # Simulator instruction rate (inst/s) +host_op_rate 147655 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5021061637 # Simulator tick rate (ticks/s) +host_mem_usage 308576 # Number of bytes of host memory used +host_seconds 379.64 # Real time elapsed on the host +sim_insts 56056069 # Number of instructions simulated +sim_ops 56056069 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 897600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24800576 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2649600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 78720 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 431296 # Number of bytes read from this memory -system.physmem.bytes_read::total 28857792 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 897600 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 78720 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 976320 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7816896 # Number of bytes written to this memory -system.physmem.bytes_written::total 7816896 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 14025 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 387509 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41400 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1230 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 6739 # Number of read requests responded to by this memory -system.physmem.num_reads::total 450903 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 122139 # Number of write requests responded to by this memory -system.physmem.num_writes::total 122139 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 471020 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 13014225 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1390391 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 41309 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 226325 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15143269 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 471020 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 41309 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 512329 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4101955 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4101955 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4101955 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 471020 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 13014225 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1390391 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 41309 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 226325 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19245224 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 450903 # Number of read requests accepted -system.physmem.writeReqs 122139 # Number of write requests accepted -system.physmem.readBursts 450903 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 122139 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 28848704 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9088 # Total number of bytes read from write queue -system.physmem.bytesWritten 7815360 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 28857792 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7816896 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 142 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu0.inst 903488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24906304 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2649664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 74560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 378304 # Number of bytes read from this memory +system.physmem.bytes_read::total 28912320 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 903488 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 74560 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 978048 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7848000 # Number of bytes written to this memory +system.physmem.bytes_written::total 7848000 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 14117 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 389161 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41401 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1165 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 5911 # Number of read requests responded to by this memory +system.physmem.num_reads::total 451755 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 122625 # Number of write requests responded to by this memory +system.physmem.num_writes::total 122625 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 473972 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 13065895 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1390019 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 39114 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 198459 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15167459 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 473972 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 39114 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 513086 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4117076 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4117076 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4117076 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 473972 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 13065895 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1390019 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 39114 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 198459 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19284535 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 451755 # Number of read requests accepted +system.physmem.writeReqs 122625 # Number of write requests accepted +system.physmem.readBursts 451755 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 122625 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 28904128 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8192 # Total number of bytes read from write queue +system.physmem.bytesWritten 7846080 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 28912320 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7848000 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 128 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4858 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 28020 # Per bank write bursts -system.physmem.perBankRdBursts::1 28240 # Per bank write bursts -system.physmem.perBankRdBursts::2 28746 # Per bank write bursts -system.physmem.perBankRdBursts::3 28309 # Per bank write bursts -system.physmem.perBankRdBursts::4 27973 # Per bank write bursts -system.physmem.perBankRdBursts::5 28180 # Per bank write bursts -system.physmem.perBankRdBursts::6 28116 # Per bank write bursts -system.physmem.perBankRdBursts::7 27456 # Per bank write bursts -system.physmem.perBankRdBursts::8 27700 # Per bank write bursts -system.physmem.perBankRdBursts::9 28070 # Per bank write bursts -system.physmem.perBankRdBursts::10 27744 # Per bank write bursts -system.physmem.perBankRdBursts::11 28151 # Per bank write bursts -system.physmem.perBankRdBursts::12 28476 # Per bank write bursts -system.physmem.perBankRdBursts::13 28764 # Per bank write bursts -system.physmem.perBankRdBursts::14 28477 # Per bank write bursts -system.physmem.perBankRdBursts::15 28339 # Per bank write bursts -system.physmem.perBankWrBursts::0 7807 # Per bank write bursts -system.physmem.perBankWrBursts::1 7750 # Per bank write bursts -system.physmem.perBankWrBursts::2 8222 # Per bank write bursts -system.physmem.perBankWrBursts::3 7743 # Per bank write bursts -system.physmem.perBankWrBursts::4 7390 # Per bank write bursts -system.physmem.perBankWrBursts::5 7636 # Per bank write bursts -system.physmem.perBankWrBursts::6 7609 # Per bank write bursts -system.physmem.perBankWrBursts::7 6913 # Per bank write bursts -system.physmem.perBankWrBursts::8 6944 # Per bank write bursts -system.physmem.perBankWrBursts::9 7275 # Per bank write bursts -system.physmem.perBankWrBursts::10 7157 # Per bank write bursts -system.physmem.perBankWrBursts::11 7547 # Per bank write bursts -system.physmem.perBankWrBursts::12 7916 # Per bank write bursts -system.physmem.perBankWrBursts::13 8234 # Per bank write bursts -system.physmem.perBankWrBursts::14 8082 # Per bank write bursts -system.physmem.perBankWrBursts::15 7890 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 3217 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 28097 # Per bank write bursts +system.physmem.perBankRdBursts::1 28602 # Per bank write bursts +system.physmem.perBankRdBursts::2 29043 # Per bank write bursts +system.physmem.perBankRdBursts::3 27571 # Per bank write bursts +system.physmem.perBankRdBursts::4 27384 # Per bank write bursts +system.physmem.perBankRdBursts::5 27564 # Per bank write bursts +system.physmem.perBankRdBursts::6 27744 # Per bank write bursts +system.physmem.perBankRdBursts::7 27694 # Per bank write bursts +system.physmem.perBankRdBursts::8 27865 # Per bank write bursts +system.physmem.perBankRdBursts::9 28720 # Per bank write bursts +system.physmem.perBankRdBursts::10 28531 # Per bank write bursts +system.physmem.perBankRdBursts::11 28618 # Per bank write bursts +system.physmem.perBankRdBursts::12 28938 # Per bank write bursts +system.physmem.perBankRdBursts::13 28977 # Per bank write bursts +system.physmem.perBankRdBursts::14 28277 # Per bank write bursts +system.physmem.perBankRdBursts::15 28002 # Per bank write bursts +system.physmem.perBankWrBursts::0 7839 # Per bank write bursts +system.physmem.perBankWrBursts::1 8045 # Per bank write bursts +system.physmem.perBankWrBursts::2 8418 # Per bank write bursts +system.physmem.perBankWrBursts::3 7040 # Per bank write bursts +system.physmem.perBankWrBursts::4 6886 # Per bank write bursts +system.physmem.perBankWrBursts::5 7040 # Per bank write bursts +system.physmem.perBankWrBursts::6 7326 # Per bank write bursts +system.physmem.perBankWrBursts::7 7097 # Per bank write bursts +system.physmem.perBankWrBursts::8 7158 # Per bank write bursts +system.physmem.perBankWrBursts::9 7908 # Per bank write bursts +system.physmem.perBankWrBursts::10 7739 # Per bank write bursts +system.physmem.perBankWrBursts::11 7821 # Per bank write bursts +system.physmem.perBankWrBursts::12 8331 # Per bank write bursts +system.physmem.perBankWrBursts::13 8401 # Per bank write bursts +system.physmem.perBankWrBursts::14 7959 # Per bank write bursts +system.physmem.perBankWrBursts::15 7587 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 8 # Number of times write queue was full causing retry -system.physmem.totGap 1905651381000 # Total gap between requests +system.physmem.totGap 1906202745000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 450903 # Read request sizes (log2) +system.physmem.readPktSize::6 451755 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 122139 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 319686 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 41704 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 44614 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 8998 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2006 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 4380 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 3959 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 3971 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2562 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2247 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 2201 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2095 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1646 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1635 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1944 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1926 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 2121 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1207 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 949 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 885 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 11 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 122625 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 319401 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 41325 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 46009 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9272 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2017 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 4338 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 3935 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 3967 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2525 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2198 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 2156 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 2109 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1642 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1631 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1933 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1904 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 2142 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1252 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 959 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 893 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see @@ -158,358 +158,359 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2413 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3733 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4487 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5021 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5063 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5369 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5553 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5837 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6527 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7038 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6311 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6522 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6544 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 950 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 934 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 961 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 906 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1002 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 986 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1094 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1000 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1407 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1623 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1831 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 2000 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1809 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 1691 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 1834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 1598 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 810 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 331 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3479 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4546 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5068 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5411 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5622 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5871 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6561 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6383 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6572 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6556 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6376 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 959 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 905 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 926 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 871 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 926 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 950 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 955 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1449 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1666 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1863 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 2097 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1921 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1890 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 1710 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 1833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 1636 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 350 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 22 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 11 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 66611 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 550.416718 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 337.147598 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 420.487836 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14710 22.08% 22.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11156 16.75% 38.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5022 7.54% 46.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2851 4.28% 50.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2435 3.66% 54.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1624 2.44% 56.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1521 2.28% 59.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1728 2.59% 61.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 25564 38.38% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 66611 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7169 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 62.875994 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2479.971838 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 7166 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::63 16 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 66892 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 549.396161 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 336.305192 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 420.466175 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14808 22.14% 22.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11177 16.71% 38.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5157 7.71% 46.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2881 4.31% 50.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2294 3.43% 54.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1713 2.56% 56.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1492 2.23% 59.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1822 2.72% 61.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 25548 38.19% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 66892 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7192 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 62.794355 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2475.959084 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 7189 99.96% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.01% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7169 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7169 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.033756 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.809188 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 3.694603 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 5699 79.50% 79.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 43 0.60% 80.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 713 9.95% 90.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 256 3.57% 93.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 102 1.42% 95.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 22 0.31% 95.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 28 0.39% 95.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 86 1.20% 96.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 18 0.25% 97.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 42 0.59% 97.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 15 0.21% 97.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 21 0.29% 98.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 11 0.15% 98.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 10 0.14% 98.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 3 0.04% 98.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 26 0.36% 98.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 2 0.03% 99.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::35 2 0.03% 99.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36 2 0.03% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::37 1 0.01% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38 1 0.01% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::39 4 0.06% 99.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40 3 0.04% 99.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::41 6 0.08% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42 2 0.03% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::43 1 0.01% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44 3 0.04% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::45 5 0.07% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::47 11 0.15% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48 5 0.07% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::49 4 0.06% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50 1 0.01% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::51 1 0.01% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::55 1 0.01% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56 7 0.10% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::57 11 0.15% 99.99% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 7192 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7192 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.046023 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.810949 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 3.823344 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 5742 79.84% 79.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 42 0.58% 80.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 691 9.61% 90.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 254 3.53% 93.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 102 1.42% 94.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 28 0.39% 95.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 28 0.39% 95.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 90 1.25% 97.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 10 0.14% 97.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 32 0.44% 97.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 22 0.31% 97.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 14 0.19% 98.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 15 0.21% 98.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 7 0.10% 98.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 9 0.13% 98.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 23 0.32% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 11 0.15% 99.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34 2 0.03% 99.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::35 2 0.03% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36 1 0.01% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::37 3 0.04% 99.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38 2 0.03% 99.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::39 4 0.06% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40 3 0.04% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::41 4 0.06% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42 2 0.03% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::43 1 0.01% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44 2 0.03% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::45 1 0.01% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::47 8 0.11% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::49 1 0.01% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50 1 0.01% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::51 2 0.03% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52 4 0.06% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::55 2 0.03% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56 13 0.18% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::57 13 0.18% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::58 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7169 # Writes before turning the bus around for reads -system.physmem.totQLat 8930594750 # Total ticks spent queuing -system.physmem.totMemAccLat 17382363500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2253805000 # Total ticks spent in databus transfers -system.physmem.avgQLat 19812.26 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 7192 # Writes before turning the bus around for reads +system.physmem.totQLat 9007685000 # Total ticks spent queuing +system.physmem.totMemAccLat 17475691250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2258135000 # Total ticks spent in databus transfers +system.physmem.avgQLat 19944.97 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 38562.26 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 15.14 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 4.10 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 15.14 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 4.10 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 38694.97 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 15.16 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 4.12 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 15.17 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 4.12 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.86 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.90 # Average write queue length when enqueuing -system.physmem.readRowHits 407659 # Number of row buffer hits during reads -system.physmem.writeRowHits 98604 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.44 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.73 # Row buffer hit rate for writes -system.physmem.avgGap 3325500.37 # Average gap between requests -system.physmem.pageHitRate 88.37 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 1804524317000 # Time in different power states -system.physmem.memoryStateTime::REF 63633700000 # Time in different power states +system.physmem.avgRdQLen 1.64 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.04 # Average write queue length when enqueuing +system.physmem.readRowHits 408104 # Number of row buffer hits during reads +system.physmem.writeRowHits 99226 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.36 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.92 # Row buffer hit rate for writes +system.physmem.avgGap 3318713.65 # Average gap between requests +system.physmem.pageHitRate 88.35 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 1805036475500 # Time in different power states +system.physmem.memoryStateTime::REF 63652420000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 37488657000 # Time in different power states +system.physmem.memoryStateTime::ACT 37517744500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 19303809 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 296468 # Transaction distribution -system.membus.trans_dist::ReadResp 296393 # Transaction distribution -system.membus.trans_dist::WriteReq 13039 # Transaction distribution -system.membus.trans_dist::WriteResp 13039 # Transaction distribution -system.membus.trans_dist::Writeback 122139 # Transaction distribution -system.membus.trans_dist::UpgradeReq 9699 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 5540 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4861 # Transaction distribution -system.membus.trans_dist::ReadExReq 162690 # Transaction distribution -system.membus.trans_dist::ReadExResp 162297 # Transaction distribution -system.membus.trans_dist::BadAddressError 75 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40466 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 920381 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 150 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 960997 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124647 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124647 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1085644 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 73690 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31367808 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 31441498 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5306880 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 5306880 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 36748378 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 36748378 # Total data (bytes) -system.membus.snoop_data_through_bus 37952 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 37884500 # Layer occupancy (ticks) +system.membus.throughput 19340215 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 296416 # Transaction distribution +system.membus.trans_dist::ReadResp 296338 # Transaction distribution +system.membus.trans_dist::WriteReq 12317 # Transaction distribution +system.membus.trans_dist::WriteResp 12317 # Transaction distribution +system.membus.trans_dist::Writeback 122625 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 1033 # Transaction distribution +system.membus.trans_dist::UpgradeResp 3220 # Transaction distribution +system.membus.trans_dist::ReadExReq 163308 # Transaction distribution +system.membus.trans_dist::ReadExResp 163210 # Transaction distribution +system.membus.trans_dist::BadAddressError 78 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39026 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 910934 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 156 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 950116 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124653 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124653 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1074769 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 67930 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31453376 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 31521306 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5306944 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 5306944 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 36828250 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 36828250 # Total data (bytes) +system.membus.snoop_data_through_bus 38208 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 36079499 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1609423248 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1585687750 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 94500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 97000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3824980631 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3823460772 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 376652994 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 376710991 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 343977 # number of replacements -system.l2c.tags.tagsinuse 65252.773158 # Cycle average of tags in use -system.l2c.tags.total_refs 2582565 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 408968 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.314834 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 7103141750 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 53523.190376 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5304.878115 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 6147.677864 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 207.477812 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 69.548991 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.816699 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.080946 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.093806 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.003166 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.001061 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.995678 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 64991 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 227 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 3387 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 4556 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4338 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 52483 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.991684 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 27108862 # Number of tag accesses -system.l2c.tags.data_accesses 27108862 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 867616 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 736617 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 210128 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 67910 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1882271 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 822208 # number of Writeback hits -system.l2c.Writeback_hits::total 822208 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 169 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 261 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 430 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 49 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 24 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 73 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 154436 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 25581 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 180017 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 867616 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 891053 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 210128 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 93491 # number of demand (read+write) hits -system.l2c.demand_hits::total 2062288 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 867616 # number of overall hits -system.l2c.overall_hits::cpu0.data 891053 # number of overall hits -system.l2c.overall_hits::cpu1.inst 210128 # number of overall hits -system.l2c.overall_hits::cpu1.data 93491 # number of overall hits -system.l2c.overall_hits::total 2062288 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 14035 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 273392 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 1238 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 452 # number of ReadReq misses -system.l2c.ReadReq_misses::total 289117 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2673 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1056 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3729 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 406 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 434 # 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number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 1067454245 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 17881620237 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 96862500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 35356999 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 19081293981 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 964468 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 4567794 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 5532262 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 972461 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 114995 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 1087456 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 9393947733 # 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number of overall miss cycles -system.l2c.overall_miss_latency::total 29114738928 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 881651 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 1010009 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 211366 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 68362 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2171388 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 822208 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 822208 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 2842 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1317 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 4159 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 455 # 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Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375543 # Number of tag accesses -system.iocache.tags.data_accesses 375543 # Number of data accesses -system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses -system.iocache.ReadReq_misses::total 175 # number of ReadReq misses +system.iocache.tags.tag_accesses 375588 # Number of tag accesses +system.iocache.tags.data_accesses 375588 # Number of data accesses +system.iocache.ReadReq_misses::tsunami.ide 180 # number of ReadReq misses +system.iocache.ReadReq_misses::total 180 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.demand_misses::tsunami.ide 41727 # number of demand (read+write) misses -system.iocache.demand_misses::total 41727 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41727 # number of overall misses -system.iocache.overall_misses::total 41727 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21492883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21492883 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 12499299192 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 12499299192 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 12520792075 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 12520792075 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 12520792075 # number of overall miss cycles -system.iocache.overall_miss_latency::total 12520792075 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 41732 # number of demand (read+write) misses +system.iocache.demand_misses::total 41732 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 41732 # number of overall misses +system.iocache.overall_misses::total 41732 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 22063883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 22063883 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 12446165943 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 12446165943 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 12468229826 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 12468229826 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 12468229826 # number of overall miss cycles +system.iocache.overall_miss_latency::total 12468229826 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 180 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 180 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41727 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41727 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41727 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41732 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41732 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41732 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41732 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses @@ -693,40 +694,40 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122816.474286 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 122816.474286 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 300811.012514 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 300811.012514 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 300064.516380 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 300064.516380 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 300064.516380 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 300064.516380 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 367481 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122577.127778 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 122577.127778 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 299532.295509 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 299532.295509 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 298769.045960 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 298769.045960 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 298769.045960 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 298769.045960 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 366756 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 28552 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 28394 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 12.870587 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 12.916673 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 175 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 175 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 180 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 180 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41727 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41727 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41727 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41727 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12390883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12390883 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10336377204 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 10336377204 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 10348768087 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 10348768087 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 10348768087 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 10348768087 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 41732 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41732 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41732 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41732 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12701883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12701883 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10283217961 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 10283217961 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 10295919844 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 10295919844 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 10295919844 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 10295919844 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -735,14 +736,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70805.045714 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 70805.045714 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 248757.633905 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 248757.633905 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 248011.313706 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 248011.313706 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 248011.313706 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 248011.313706 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70566.016667 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 70566.016667 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 247478.291322 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 247478.291322 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 246715.226780 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 246715.226780 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 246715.226780 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 246715.226780 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -756,35 +757,35 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 12477942 # Number of BP lookups -system.cpu0.branchPred.condPredicted 10513633 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 331474 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 8127728 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 5283638 # Number of BTB hits +system.cpu0.branchPred.lookups 13535285 # Number of BP lookups +system.cpu0.branchPred.condPredicted 11399113 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 368683 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 9302001 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 5741441 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 65.007564 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 797741 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 28790 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 61.722644 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 871515 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 32576 # Number of incorrect RAS predictions. system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 8879185 # DTB read hits -system.cpu0.dtb.read_misses 30734 # DTB read misses -system.cpu0.dtb.read_acv 556 # DTB read access violations -system.cpu0.dtb.read_accesses 627584 # DTB read accesses -system.cpu0.dtb.write_hits 5815647 # DTB write hits -system.cpu0.dtb.write_misses 8173 # DTB write misses -system.cpu0.dtb.write_acv 357 # DTB write access violations -system.cpu0.dtb.write_accesses 210225 # DTB write accesses -system.cpu0.dtb.data_hits 14694832 # DTB hits -system.cpu0.dtb.data_misses 38907 # DTB misses -system.cpu0.dtb.data_acv 913 # DTB access violations -system.cpu0.dtb.data_accesses 837809 # DTB accesses -system.cpu0.itb.fetch_hits 998260 # ITB hits -system.cpu0.itb.fetch_misses 27519 # ITB misses -system.cpu0.itb.fetch_acv 894 # ITB acv -system.cpu0.itb.fetch_accesses 1025779 # ITB accesses +system.cpu0.dtb.read_hits 9655924 # DTB read hits +system.cpu0.dtb.read_misses 34371 # DTB read misses +system.cpu0.dtb.read_acv 569 # DTB read access violations +system.cpu0.dtb.read_accesses 673777 # DTB read accesses +system.cpu0.dtb.write_hits 6329246 # DTB write hits +system.cpu0.dtb.write_misses 8477 # DTB write misses +system.cpu0.dtb.write_acv 351 # DTB write access violations +system.cpu0.dtb.write_accesses 236111 # DTB write accesses +system.cpu0.dtb.data_hits 15985170 # DTB hits +system.cpu0.dtb.data_misses 42848 # DTB misses +system.cpu0.dtb.data_acv 920 # DTB access violations +system.cpu0.dtb.data_accesses 909888 # DTB accesses +system.cpu0.itb.fetch_hits 1092484 # ITB hits +system.cpu0.itb.fetch_misses 31809 # ITB misses +system.cpu0.itb.fetch_acv 996 # ITB acv +system.cpu0.itb.fetch_accesses 1124293 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -797,303 +798,304 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 116074371 # number of cpu cycles simulated +system.cpu0.numCycles 120980731 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 25123779 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 63882467 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 12477942 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 6081379 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 12010156 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1699076 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 37307525 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 31946 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 195411 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 352959 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 191 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 7722540 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 223615 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 76113904 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.839301 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.177052 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 27854466 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 69491073 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 13535285 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 6612956 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 12980522 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1985487 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 37586938 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 31052 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 209286 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 361146 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 209 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 8301805 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 269407 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 80329317 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.865077 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.209142 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 64103748 84.22% 84.22% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 767865 1.01% 85.23% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1567652 2.06% 87.29% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 704812 0.93% 88.22% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2586726 3.40% 91.61% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 521075 0.68% 92.30% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 575522 0.76% 93.05% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 832581 1.09% 94.15% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4453923 5.85% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 67348795 83.84% 83.84% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 826622 1.03% 84.87% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1640547 2.04% 86.91% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 764329 0.95% 87.86% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2736993 3.41% 91.27% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 565546 0.70% 91.97% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 615994 0.77% 92.74% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 1025224 1.28% 94.02% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4805267 5.98% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 76113904 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.107500 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.550358 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 26378411 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 36826325 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 10921760 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 930988 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1056419 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 512680 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 35852 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 62713959 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 107463 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1056419 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 27400432 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 14971568 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 18343259 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 10229394 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 4112830 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 59339079 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 7155 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 639099 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1437135 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 39727133 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 72236857 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 72098194 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 129082 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 34929896 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 4797229 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1458801 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 212309 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 11241570 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9288070 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6084553 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1139915 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 737819 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 52640864 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1816659 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 51478960 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 92665 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 5869250 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 3045578 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1230018 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 76113904 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.676341 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.327493 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 80329317 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.111880 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.574398 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 28693302 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 37589637 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 12241193 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 539176 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1266008 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 554913 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 40031 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 68046301 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 123637 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1266008 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 29596220 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 13874520 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 19704370 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 11366279 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 4521918 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 64294985 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 8881 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 963704 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 49626 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 1581472 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 42969329 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 77993479 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 77835647 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 147432 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 36982529 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 5986792 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1597094 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 233553 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 9775023 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 10212119 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6719453 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1264075 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 886942 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 56810323 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 2002217 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 55156303 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 107150 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 7195907 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 4115621 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1359252 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 80329317 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.686627 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.367653 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 53257398 69.97% 69.97% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 10376788 13.63% 83.60% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 4704231 6.18% 89.78% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3091331 4.06% 93.85% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2445214 3.21% 97.06% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1217468 1.60% 98.66% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 651050 0.86% 99.51% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 318171 0.42% 99.93% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 52253 0.07% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 56644741 70.52% 70.52% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 10637349 13.24% 83.76% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 4503428 5.61% 89.36% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 3111745 3.87% 93.24% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2708967 3.37% 96.61% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1473067 1.83% 98.44% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 832512 1.04% 99.48% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 359476 0.45% 99.93% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 58032 0.07% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 76113904 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 80329317 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 82049 12.02% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 319124 46.77% 58.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 281213 41.21% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 91428 11.87% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 367704 47.76% 59.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 310812 40.37% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 3785 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 35464091 68.89% 68.90% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 56550 0.11% 69.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.01% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 15746 0.03% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9235082 17.94% 86.98% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5882526 11.43% 98.41% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 819301 1.59% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 3793 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 37662855 68.28% 68.29% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 60369 0.11% 68.40% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.40% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 16864 0.03% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 10116560 18.34% 86.78% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 6398898 11.60% 98.38% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 895081 1.62% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 51478960 # Type of FU issued -system.cpu0.iq.rate 0.443500 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 682386 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.013256 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 179291609 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 60070073 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 50439032 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 555265 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 269219 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 261959 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 51867113 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 290448 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 544569 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 55156303 # Type of FU issued +system.cpu0.iq.rate 0.455910 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 769944 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.013959 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 190884663 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 65713674 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 53746277 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 634353 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 307759 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 299045 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 55590646 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 331808 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 587688 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1116578 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3845 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 12782 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 445374 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1466473 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 4362 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 13302 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 593267 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18457 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 142389 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18777 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 290466 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1056419 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 10732956 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 797506 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 57687159 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 618379 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9288070 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6084553 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1600267 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 582946 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 5458 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 12782 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 164537 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 351989 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 516526 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 51092894 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 8933351 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 386065 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1266008 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 10034082 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 1132931 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 62323042 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 565721 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 10212119 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6719453 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1762676 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 460962 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 503945 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 13302 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 186944 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 388547 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 575491 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 54610252 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9715916 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 546050 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3229636 # number of nop insts executed -system.cpu0.iew.exec_refs 14770817 # number of memory reference insts executed -system.cpu0.iew.exec_branches 8136394 # Number of branches executed -system.cpu0.iew.exec_stores 5837466 # Number of stores executed -system.cpu0.iew.exec_rate 0.440174 # Inst execution rate -system.cpu0.iew.wb_sent 50791046 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 50700991 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 25278333 # num instructions producing a value -system.cpu0.iew.wb_consumers 34060542 # num instructions consuming a value +system.cpu0.iew.exec_nop 3510502 # number of nop insts executed +system.cpu0.iew.exec_refs 16068148 # number of memory reference insts executed +system.cpu0.iew.exec_branches 8653897 # Number of branches executed +system.cpu0.iew.exec_stores 6352232 # Number of stores executed +system.cpu0.iew.exec_rate 0.451396 # Inst execution rate +system.cpu0.iew.wb_sent 54145867 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 54045322 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 27468175 # num instructions producing a value +system.cpu0.iew.wb_consumers 37895992 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.436797 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.742159 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.446727 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.724831 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6334928 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 586641 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 480870 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 75057485 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.682787 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.597640 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 7798809 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 642965 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 531823 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 79063309 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.688507 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.631609 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 55774455 74.31% 74.31% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 8026658 10.69% 85.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 4417430 5.89% 90.89% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2392691 3.19% 94.08% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1323184 1.76% 95.84% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 562724 0.75% 96.59% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 473653 0.63% 97.22% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 433129 0.58% 97.80% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1653561 2.20% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 59272342 74.97% 74.97% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 8075780 10.21% 85.18% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 4311536 5.45% 90.64% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2381088 3.01% 93.65% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1583020 2.00% 95.65% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 598155 0.76% 96.41% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 490827 0.62% 97.03% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 478799 0.61% 97.63% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1871762 2.37% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 75057485 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 51248256 # Number of instructions committed -system.cpu0.commit.committedOps 51248256 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 79063309 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 54435622 # Number of instructions committed +system.cpu0.commit.committedOps 54435622 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13810671 # Number of memory references committed -system.cpu0.commit.loads 8171492 # Number of loads committed -system.cpu0.commit.membars 199624 # Number of memory barriers committed -system.cpu0.commit.branches 7741114 # Number of branches committed -system.cpu0.commit.fp_insts 259898 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 47457125 # Number of committed integer instructions. -system.cpu0.commit.function_calls 657479 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 2951389 5.76% 5.76% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 33388118 65.15% 70.91% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 55525 0.11% 71.02% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 71.02% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 15746 0.03% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 1879 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 8371116 16.33% 87.39% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 5645183 11.02% 98.40% # Class of committed instruction -system.cpu0.commit.op_class_0::IprAccess 819300 1.60% 100.00% # Class of committed instruction +system.cpu0.commit.refs 14871832 # Number of memory references committed +system.cpu0.commit.loads 8745646 # Number of loads committed +system.cpu0.commit.membars 219982 # Number of memory barriers committed +system.cpu0.commit.branches 8204799 # Number of branches committed +system.cpu0.commit.fp_insts 296843 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 50375539 # Number of committed integer instructions. +system.cpu0.commit.function_calls 712916 # Number of function calls committed. +system.cpu0.commit.op_class_0::No_OpClass 3148922 5.78% 5.78% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 35215746 64.69% 70.48% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 59292 0.11% 70.59% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 70.59% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 16864 0.03% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 1883 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 8965628 16.47% 87.09% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 6132206 11.27% 98.36% # Class of committed instruction +system.cpu0.commit.op_class_0::IprAccess 895081 1.64% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 51248256 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1653561 # number cycles where commit BW limit reached +system.cpu0.commit.op_class_0::total 54435622 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1871762 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 130790454 # The number of ROB reads -system.cpu0.rob.rob_writes 116222813 # The number of ROB writes -system.cpu0.timesIdled 1101169 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 39960467 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3695221845 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 48300626 # Number of Instructions Simulated -system.cpu0.committedOps 48300626 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 2.403165 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.403165 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.416118 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.416118 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 67219449 # number of integer regfile reads -system.cpu0.int_regfile_writes 36695614 # number of integer regfile writes -system.cpu0.fp_regfile_reads 128632 # number of floating regfile reads -system.cpu0.fp_regfile_writes 130173 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1801385 # number of misc regfile reads -system.cpu0.misc_regfile_writes 820377 # number of misc regfile writes +system.cpu0.rob.rob_reads 139225703 # The number of ROB reads +system.cpu0.rob.rob_writes 125735253 # The number of ROB writes +system.cpu0.timesIdled 1168278 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 40651414 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3691427340 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 51290467 # Number of Instructions Simulated +system.cpu0.committedOps 51290467 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 2.358737 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.358737 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.423956 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.423956 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 71570668 # number of integer regfile reads +system.cpu0.int_regfile_writes 39014056 # number of integer regfile writes +system.cpu0.fp_regfile_reads 147010 # number of floating regfile reads +system.cpu0.fp_regfile_writes 148900 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1947197 # number of misc regfile reads +system.cpu0.misc_regfile_writes 897129 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1125,49 +1127,49 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.throughput 111416521 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2199115 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2199023 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 13039 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 13039 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 822208 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 9837 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 5613 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 15450 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 343877 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 302328 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 75 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1763397 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3369225 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 422759 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 294489 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5849870 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 56425664 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 130205428 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 13527424 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 10778278 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 210936794 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 210926490 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 1394560 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4971595549 # Layer occupancy (ticks) +system.toL2Bus.throughput 111935595 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2200566 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2200471 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 12317 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 12317 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 833565 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 4571 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 1080 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 5651 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 347592 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 306043 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 78 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1987262 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3563495 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 190571 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 127415 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5868743 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 63588928 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 138451052 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 6097280 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4501998 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 212639258 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 212628634 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 743808 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 5019455896 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 747000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3972568555 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4476579522 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 5889953047 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 6206391842 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 951834487 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 429200431 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 507907991 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 227242208 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 1435370 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 7369 # Transaction distribution -system.iobus.trans_dist::ReadResp 7369 # Transaction distribution -system.iobus.trans_dist::WriteReq 54591 # Transaction distribution -system.iobus.trans_dist::WriteResp 54591 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11870 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) +system.iobus.throughput 1431950 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 7376 # Transaction distribution +system.iobus.trans_dist::ReadResp 7376 # Transaction distribution +system.iobus.trans_dist::WriteReq 53869 # Transaction distribution +system.iobus.trans_dist::WriteResp 53869 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 10422 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) @@ -1178,12 +1180,12 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 40466 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 123920 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 47480 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 39026 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83464 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83464 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 122490 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 41688 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) @@ -1194,14 +1196,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 73690 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 2735314 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 2735314 # Total data (bytes) -system.iobus.reqLayer0.occupancy 11225000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size_system.bridge.master::total 67930 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661664 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661664 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 2729594 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 2729594 # Total data (bytes) +system.iobus.reqLayer0.occupancy 9777000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1221,268 +1223,267 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 380163081 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 380161835 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 27427000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 26709000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 43193006 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 43245009 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.icache.tags.replacements 881127 # number of replacements -system.cpu0.icache.tags.tagsinuse 509.683312 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 6795719 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 881636 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 7.708078 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 26872936250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.683312 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995475 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.995475 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 36 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 417 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 8604286 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 8604286 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 6795719 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 6795719 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 6795719 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 6795719 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 6795719 # number of overall hits -system.cpu0.icache.overall_hits::total 6795719 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 926821 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 926821 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 926821 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 926821 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 926821 # number of overall misses -system.cpu0.icache.overall_misses::total 926821 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13137729759 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 13137729759 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 13137729759 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 13137729759 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 13137729759 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 13137729759 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 7722540 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 7722540 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 7722540 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 7722540 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 7722540 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 7722540 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.120015 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.120015 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.120015 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.120015 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.120015 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.120015 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14175.045407 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14175.045407 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14175.045407 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14175.045407 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14175.045407 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14175.045407 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 3568 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 70 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 151 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 23.629139 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 70 # average number of cycles each access was blocked +system.cpu0.icache.tags.replacements 993039 # number of replacements +system.cpu0.icache.tags.tagsinuse 509.694749 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 7257459 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 993551 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 7.304566 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 26718502250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.694749 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995498 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.995498 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 425 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 9295490 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 9295490 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 7257459 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 7257459 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 7257459 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 7257459 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 7257459 # number of overall hits +system.cpu0.icache.overall_hits::total 7257459 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1044346 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1044346 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1044346 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1044346 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1044346 # number of overall misses +system.cpu0.icache.overall_misses::total 1044346 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14667970749 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 14667970749 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 14667970749 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 14667970749 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 14667970749 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 14667970749 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 8301805 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 8301805 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 8301805 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 8301805 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 8301805 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 8301805 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.125797 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.125797 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.125797 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.125797 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.125797 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.125797 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14045.125609 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14045.125609 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14045.125609 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14045.125609 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14045.125609 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14045.125609 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 4303 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 182 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 23.642857 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 45075 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 45075 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 45075 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 45075 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 45075 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 45075 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 881746 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 881746 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 881746 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 881746 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 881746 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 881746 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10814665187 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 10814665187 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10814665187 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 10814665187 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10814665187 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 10814665187 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.114178 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.114178 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.114178 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.114178 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.114178 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.114178 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12265.057269 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12265.057269 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12265.057269 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12265.057269 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12265.057269 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12265.057269 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 50661 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 50661 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 50661 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 50661 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 50661 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 50661 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 993685 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 993685 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 993685 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 993685 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 993685 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 993685 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12074149969 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 12074149969 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12074149969 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 12074149969 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12074149969 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 12074149969 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.119695 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.119695 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.119695 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.119695 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.119695 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.119695 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12150.882794 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12150.882794 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12150.882794 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12150.882794 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12150.882794 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12150.882794 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 1281204 # number of replacements -system.cpu0.dcache.tags.tagsinuse 505.636705 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 10489009 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1281716 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 8.183567 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 26139000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.636705 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.987572 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.987572 # Average percentage of cache occupancy +system.cpu0.dcache.tags.replacements 1357625 # number of replacements +system.cpu0.dcache.tags.tagsinuse 506.932074 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 11305784 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1358137 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 8.324480 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 25366000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.932074 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.990102 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.990102 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 228 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 45 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 239 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 224 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 49 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 56677841 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 56677841 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6448265 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6448265 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3678309 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3678309 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 163487 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 163487 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 188240 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 188240 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10126574 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10126574 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10126574 # number of overall hits -system.cpu0.dcache.overall_hits::total 10126574 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1590441 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1590441 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1755180 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1755180 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20486 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 20486 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2716 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 2716 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3345621 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3345621 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3345621 # number of overall misses -system.cpu0.dcache.overall_misses::total 3345621 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 40624107085 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 40624107085 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 78713383276 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 78713383276 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 300049994 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 300049994 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 20153405 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 20153405 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 119337490361 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 119337490361 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 119337490361 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 119337490361 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8038706 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8038706 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5433489 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5433489 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 183973 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 183973 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 190956 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 190956 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13472195 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 13472195 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13472195 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 13472195 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.197848 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.197848 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.323030 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.323030 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.111353 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.111353 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.014223 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.014223 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.248335 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.248335 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.248335 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.248335 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25542.668408 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 25542.668408 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44846.331018 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 44846.331018 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14646.587621 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14646.587621 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7420.252209 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7420.252209 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35669.757681 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 35669.757681 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35669.757681 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 35669.757681 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 2966485 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 566 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 48680 # number of cycles access was blocked +system.cpu0.dcache.tags.tag_accesses 61088591 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 61088591 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6897589 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6897589 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4012977 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4012977 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 181053 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 181053 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 208423 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 208423 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10910566 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10910566 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10910566 # number of overall hits +system.cpu0.dcache.overall_hits::total 10910566 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1718976 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1718976 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1889613 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1889613 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 22934 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 22934 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 507 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 507 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3608589 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3608589 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3608589 # number of overall misses +system.cpu0.dcache.overall_misses::total 3608589 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 42674970043 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 42674970043 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 81294445080 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 81294445080 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 374188245 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 374188245 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3007034 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 3007034 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 123969415123 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 123969415123 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 123969415123 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 123969415123 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8616565 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8616565 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5902590 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5902590 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 203987 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 203987 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 208930 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 208930 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 14519155 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 14519155 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 14519155 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 14519155 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.199497 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.199497 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.320133 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.320133 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.112429 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.112429 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.002427 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.002427 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.248540 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.248540 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.248540 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.248540 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 24825.809111 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 24825.809111 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43021.743119 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 43021.743119 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16315.873594 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16315.873594 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5931.033531 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5931.033531 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34353.985761 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 34353.985761 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34353.985761 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 34353.985761 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 3433420 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 538 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 116463 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 60.938476 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 80.857143 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 29.480779 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 76.857143 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 754427 # number of writebacks -system.cpu0.dcache.writebacks::total 754427 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 586151 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 586151 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1480465 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1480465 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4562 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4562 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 2066616 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 2066616 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 2066616 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 2066616 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1004290 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1004290 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 274715 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 274715 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15924 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15924 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2716 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 2716 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1279005 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1279005 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1279005 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1279005 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 27273016452 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 27273016452 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11562486348 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11562486348 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 175781505 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 175781505 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 14720595 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 14720595 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 38835502800 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 38835502800 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 38835502800 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 38835502800 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1459363000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1459363000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2145424499 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2145424499 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3604787499 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3604787499 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.124932 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.124932 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050560 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050560 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086556 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086556 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.014223 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.014223 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.094937 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.094937 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.094937 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.094937 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 27156.515003 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 27156.515003 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42089.024436 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42089.024436 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11038.778259 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11038.778259 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5419.953976 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5419.953976 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30363.839704 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30363.839704 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30363.839704 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30363.839704 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 808609 # number of writebacks +system.cpu0.dcache.writebacks::total 808609 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 667238 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 667238 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1594728 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1594728 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5762 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5762 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 2261966 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 2261966 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 2261966 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 2261966 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1051738 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 1051738 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 294885 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 294885 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 17172 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 17172 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 507 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 507 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1346623 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1346623 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1346623 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1346623 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 27880739944 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 27880739944 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 12002536573 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 12002536573 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 202887753 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 202887753 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 1992966 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 1992966 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 39883276517 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 39883276517 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 39883276517 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 39883276517 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1460997001 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1460997001 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2069284998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2069284998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3530281999 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3530281999 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.122060 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.122060 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049959 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049959 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.084182 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.084182 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.002427 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.002427 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092748 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.092748 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092748 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.092748 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26509.206612 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26509.206612 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40702.431704 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40702.431704 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11815.033368 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11815.033368 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3930.899408 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3930.899408 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29617.254805 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29617.254805 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29617.254805 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29617.254805 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1490,35 +1491,35 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 2485884 # Number of BP lookups -system.cpu1.branchPred.condPredicted 2055798 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 72106 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 1444173 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 831190 # Number of BTB hits +system.cpu1.branchPred.lookups 1483279 # Number of BP lookups +system.cpu1.branchPred.condPredicted 1227619 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 44770 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 650934 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 463612 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 57.554739 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 170291 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 7410 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 71.222582 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 99211 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 4550 # Number of incorrect RAS predictions. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1846757 # DTB read hits -system.cpu1.dtb.read_misses 10485 # DTB read misses -system.cpu1.dtb.read_acv 25 # DTB read access violations -system.cpu1.dtb.read_accesses 320297 # DTB read accesses -system.cpu1.dtb.write_hits 1188866 # DTB write hits -system.cpu1.dtb.write_misses 1998 # DTB write misses -system.cpu1.dtb.write_acv 67 # DTB write access violations -system.cpu1.dtb.write_accesses 130212 # DTB write accesses -system.cpu1.dtb.data_hits 3035623 # DTB hits -system.cpu1.dtb.data_misses 12483 # DTB misses -system.cpu1.dtb.data_acv 92 # DTB access violations -system.cpu1.dtb.data_accesses 450509 # DTB accesses -system.cpu1.itb.fetch_hits 420713 # ITB hits -system.cpu1.itb.fetch_misses 6600 # ITB misses -system.cpu1.itb.fetch_acv 223 # ITB acv -system.cpu1.itb.fetch_accesses 427313 # ITB accesses +system.cpu1.dtb.read_hits 1187167 # DTB read hits +system.cpu1.dtb.read_misses 8989 # DTB read misses +system.cpu1.dtb.read_acv 6 # DTB read access violations +system.cpu1.dtb.read_accesses 276351 # DTB read accesses +system.cpu1.dtb.write_hits 628916 # DTB write hits +system.cpu1.dtb.write_misses 1890 # DTB write misses +system.cpu1.dtb.write_acv 35 # DTB write access violations +system.cpu1.dtb.write_accesses 104365 # DTB write accesses +system.cpu1.dtb.data_hits 1816083 # DTB hits +system.cpu1.dtb.data_misses 10879 # DTB misses +system.cpu1.dtb.data_acv 41 # DTB access violations +system.cpu1.dtb.data_accesses 380716 # DTB accesses +system.cpu1.itb.fetch_hits 316911 # ITB hits +system.cpu1.itb.fetch_misses 5517 # ITB misses +system.cpu1.itb.fetch_acv 125 # ITB acv +system.cpu1.itb.fetch_accesses 322428 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1531,552 +1532,553 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 14964653 # number of cpu cycles simulated +system.cpu1.numCycles 8637240 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 5680448 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 11756636 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 2485884 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 1001481 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 2105616 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 381271 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 5937724 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 25803 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 62153 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 48156 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 23 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1420733 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 48517 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 14103634 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.833589 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.209447 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 2818807 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 7093634 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 1483279 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 562823 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 1271731 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 278690 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 3719491 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 23500 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 54196 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 48363 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 46 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 894062 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 29430 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 8117811 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.873836 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.252237 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 11998018 85.07% 85.07% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 134082 0.95% 86.02% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 225201 1.60% 87.62% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 169062 1.20% 88.82% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 292225 2.07% 90.89% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 115066 0.82% 91.70% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 124219 0.88% 92.59% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 190666 1.35% 93.94% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 855095 6.06% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 6846080 84.33% 84.33% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 64163 0.79% 85.12% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 148479 1.83% 86.95% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 110798 1.36% 88.32% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 183312 2.26% 90.58% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 76211 0.94% 91.52% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 83539 1.03% 92.54% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 57250 0.71% 93.25% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 547979 6.75% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 14103634 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.166117 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.785627 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 5621005 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 6169812 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 1969307 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 106628 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 236881 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 108171 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 6940 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 11535490 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 20476 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 236881 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 5819966 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 414819 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 5141752 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 1873919 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 616295 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 10688130 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 72 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 55241 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 150444 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 7038513 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 12788456 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 12730882 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 51827 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 5999158 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1039355 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 430985 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 39680 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 1897434 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 1953635 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1261748 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 176061 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 98445 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 9382355 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 465021 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 9121330 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 28823 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1378008 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 697882 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 334259 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 14103634 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.646736 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.322598 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 8117811 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.171731 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.821285 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 2872853 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 3821739 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 1206360 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 38891 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 177967 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 63499 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 3800 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 6911640 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 11536 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 177967 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 2981399 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 177384 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 3223332 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 1138018 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 419709 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 6319378 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 203 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 45248 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 5428 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 135690 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 4267087 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 7667393 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 7641550 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 21648 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 3453234 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 813853 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 270338 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 17002 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 1051064 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 1262745 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 687524 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 118324 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 74010 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 5585108 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 271421 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 5341703 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 20645 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1049804 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 612834 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 207573 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 8117811 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.658023 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.347544 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 10102268 71.63% 71.63% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 1834449 13.01% 84.64% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 778460 5.52% 90.16% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 526095 3.73% 93.89% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 451675 3.20% 97.09% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 203961 1.45% 98.53% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 130101 0.92% 99.46% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 68435 0.49% 99.94% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 8190 0.06% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 5813637 71.62% 71.62% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 1034901 12.75% 84.36% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 447279 5.51% 89.87% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 322285 3.97% 93.84% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 244246 3.01% 96.85% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 126246 1.56% 98.41% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 72876 0.90% 99.31% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 50809 0.63% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 5532 0.07% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 14103634 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 8117811 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 3122 1.64% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 102805 54.10% 55.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 84113 44.26% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 4295 3.26% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 76591 58.14% 61.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 50850 38.60% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3526 0.04% 0.04% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 5686452 62.34% 62.38% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 15839 0.17% 62.55% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.55% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 10725 0.12% 62.67% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.67% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.67% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.67% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1763 0.02% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 1931464 21.18% 83.87% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1211908 13.29% 97.15% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 259653 2.85% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3518 0.07% 0.07% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 3268625 61.19% 61.26% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 9680 0.18% 61.44% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 61.44% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 8881 0.17% 61.60% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 61.60% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 61.60% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 61.60% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1759 0.03% 61.64% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 61.64% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 61.64% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 61.64% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 61.64% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 61.64% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 61.64% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 61.64% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 61.64% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 61.64% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 61.64% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.64% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 61.64% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.64% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.64% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.64% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.64% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.64% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.64% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 61.64% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.64% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.64% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 1232456 23.07% 84.71% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 646098 12.10% 96.80% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 170686 3.20% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 9121330 # Type of FU issued -system.cpu1.iq.rate 0.609525 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 190040 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.020835 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 32366807 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 11130082 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 8856102 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 198350 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 96900 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 93876 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 9204439 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 103405 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 88797 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 5341703 # Type of FU issued +system.cpu1.iq.rate 0.618450 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 131736 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.024662 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 18885884 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 6873502 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 5132762 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 67714 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 33978 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 32480 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 5434957 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 34964 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 63957 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 277499 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 1209 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 1676 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 126244 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 266370 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 353 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 1238 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 98626 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 334 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 13648 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 353 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 72939 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 236881 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 252351 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 39276 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 10330457 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 142523 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 1953635 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1261748 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 421576 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 32385 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 1813 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 1676 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 32559 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 96048 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 128607 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 9031900 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 1864128 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 89430 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 177967 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 80772 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 78093 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 6077668 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 83087 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 1262745 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 687524 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 253926 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 4593 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 73335 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 1238 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 19913 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 60148 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 80061 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 5287979 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 1198929 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 53724 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 483081 # number of nop insts executed -system.cpu1.iew.exec_refs 3060773 # number of memory reference insts executed -system.cpu1.iew.exec_branches 1345265 # Number of branches executed -system.cpu1.iew.exec_stores 1196645 # Number of stores executed -system.cpu1.iew.exec_rate 0.603549 # Inst execution rate -system.cpu1.iew.wb_sent 8976284 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 8949978 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 4203498 # num instructions producing a value -system.cpu1.iew.wb_consumers 5915948 # num instructions consuming a value +system.cpu1.iew.exec_nop 221139 # number of nop insts executed +system.cpu1.iew.exec_refs 1832774 # number of memory reference insts executed +system.cpu1.iew.exec_branches 762873 # Number of branches executed +system.cpu1.iew.exec_stores 633845 # Number of stores executed +system.cpu1.iew.exec_rate 0.612230 # Inst execution rate +system.cpu1.iew.wb_sent 5189273 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 5165242 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 2532511 # num instructions producing a value +system.cpu1.iew.wb_consumers 3587094 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.598075 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.710537 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.598020 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.706006 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 1403439 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 130762 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 120016 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 13866753 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.637072 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.578145 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 1065222 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 63848 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 75650 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 7939844 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.623951 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.560784 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 10553407 76.11% 76.11% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1550482 11.18% 87.29% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 573583 4.14% 91.42% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 351937 2.54% 93.96% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 252477 1.82% 95.78% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 99182 0.72% 96.50% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 104002 0.75% 97.25% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 102635 0.74% 97.99% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 279048 2.01% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 6043541 76.12% 76.12% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 925286 11.65% 87.77% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 320402 4.04% 91.81% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 190890 2.40% 94.21% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 129096 1.63% 95.84% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 57238 0.72% 96.56% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 65164 0.82% 97.38% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 44060 0.55% 97.93% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 164167 2.07% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 13866753 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 8834118 # Number of instructions committed -system.cpu1.commit.committedOps 8834118 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 7939844 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 4954074 # Number of instructions committed +system.cpu1.commit.committedOps 4954074 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 2811640 # Number of memory references committed -system.cpu1.commit.loads 1676136 # Number of loads committed -system.cpu1.commit.membars 41495 # Number of memory barriers committed -system.cpu1.commit.branches 1262292 # Number of branches committed -system.cpu1.commit.fp_insts 92546 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 8189363 # Number of committed integer instructions. -system.cpu1.commit.function_calls 139415 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 427272 4.84% 4.84% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 5265448 59.60% 64.44% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 15610 0.18% 64.62% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.62% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 10725 0.12% 64.74% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.74% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.74% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.74% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 1763 0.02% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 1717631 19.44% 84.20% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 1136016 12.86% 97.06% # Class of committed instruction -system.cpu1.commit.op_class_0::IprAccess 259653 2.94% 100.00% # Class of committed instruction +system.cpu1.commit.refs 1585273 # Number of memory references committed +system.cpu1.commit.loads 996375 # Number of loads committed +system.cpu1.commit.membars 16576 # Number of memory barriers committed +system.cpu1.commit.branches 700739 # Number of branches committed +system.cpu1.commit.fp_insts 31280 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 4632533 # Number of committed integer instructions. +system.cpu1.commit.function_calls 77324 # Number of function calls committed. +system.cpu1.commit.op_class_0::No_OpClass 191990 3.88% 3.88% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 2969211 59.93% 63.81% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 9565 0.19% 64.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.00% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 8881 0.18% 64.18% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.18% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.18% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.18% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 1759 0.04% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 1012951 20.45% 84.66% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 589031 11.89% 96.55% # Class of committed instruction +system.cpu1.commit.op_class_0::IprAccess 170686 3.45% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 8834118 # Class of committed instruction -system.cpu1.commit.bw_lim_events 279048 # number cycles where commit BW limit reached +system.cpu1.commit.op_class_0::total 4954074 # Class of committed instruction +system.cpu1.commit.bw_lim_events 164167 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 23736453 # The number of ROB reads -system.cpu1.rob.rob_writes 20710450 # The number of ROB writes -system.cpu1.timesIdled 126022 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 861019 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3795679739 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 8410372 # Number of Instructions Simulated -system.cpu1.committedOps 8410372 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.779309 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.779309 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.562016 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.562016 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 11653751 # number of integer regfile reads -system.cpu1.int_regfile_writes 6367365 # number of integer regfile writes -system.cpu1.fp_regfile_reads 51509 # number of floating regfile reads -system.cpu1.fp_regfile_writes 51143 # number of floating regfile writes -system.cpu1.misc_regfile_reads 926936 # number of misc regfile reads -system.cpu1.misc_regfile_writes 206554 # number of misc regfile writes -system.cpu1.icache.tags.replacements 210820 # number of replacements -system.cpu1.icache.tags.tagsinuse 470.468430 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 1201520 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 211332 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 5.685462 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1879665276250 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 470.468430 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.918884 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.918884 # Average percentage of cache occupancy +system.cpu1.rob.rob_reads 13715407 # The number of ROB reads +system.cpu1.rob.rob_writes 12215098 # The number of ROB writes +system.cpu1.timesIdled 57372 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 519429 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3803095502 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 4765602 # Number of Instructions Simulated +system.cpu1.committedOps 4765602 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.812413 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.812413 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.551751 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.551751 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 6848640 # number of integer regfile reads +system.cpu1.int_regfile_writes 3746417 # number of integer regfile writes +system.cpu1.fp_regfile_reads 21244 # number of floating regfile reads +system.cpu1.fp_regfile_writes 19994 # number of floating regfile writes +system.cpu1.misc_regfile_reads 693471 # number of misc regfile reads +system.cpu1.misc_regfile_writes 115172 # number of misc regfile writes +system.cpu1.icache.tags.replacements 94727 # number of replacements +system.cpu1.icache.tags.tagsinuse 453.369242 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 794363 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 95239 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 8.340732 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1880860642000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 453.369242 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.885487 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.885487 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 1632124 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 1632124 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 1201520 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1201520 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 1201520 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1201520 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 1201520 # number of overall hits -system.cpu1.icache.overall_hits::total 1201520 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 219211 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 219211 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 219211 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 219211 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 219211 # number of overall misses -system.cpu1.icache.overall_misses::total 219211 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 2949137410 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 2949137410 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 2949137410 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 2949137410 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 2949137410 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 2949137410 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 1420731 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1420731 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1420731 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1420731 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1420731 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1420731 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.154295 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.154295 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.154295 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.154295 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.154295 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.154295 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13453.418898 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13453.418898 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13453.418898 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13453.418898 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13453.418898 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13453.418898 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 428 # number of cycles access was blocked +system.cpu1.icache.tags.tag_accesses 989361 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 989361 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 794363 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 794363 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 794363 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 794363 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 794363 # number of overall hits +system.cpu1.icache.overall_hits::total 794363 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 99697 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 99697 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 99697 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 99697 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 99697 # number of overall misses +system.cpu1.icache.overall_misses::total 99697 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1381976879 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 1381976879 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 1381976879 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 1381976879 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 1381976879 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 1381976879 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 894060 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 894060 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 894060 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 894060 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 894060 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 894060 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.111510 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.111510 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.111510 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.111510 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.111510 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.111510 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13861.769953 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13861.769953 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13861.769953 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13861.769953 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13861.769953 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13861.769953 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 350 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 21 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 23 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 20.380952 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 15.217391 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 7818 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 7818 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 7818 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 7818 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 7818 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 7818 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 211393 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 211393 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 211393 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 211393 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 211393 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 211393 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2447786762 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 2447786762 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2447786762 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 2447786762 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2447786762 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 2447786762 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.148792 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.148792 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.148792 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.148792 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.148792 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.148792 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11579.317962 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11579.317962 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11579.317962 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11579.317962 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11579.317962 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11579.317962 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 4396 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 4396 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 4396 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 4396 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 4396 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 4396 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 95301 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 95301 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 95301 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 95301 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 95301 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 95301 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 1139734069 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 1139734069 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 1139734069 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 1139734069 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 1139734069 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 1139734069 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.106594 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.106594 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.106594 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.106594 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.106594 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.106594 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11959.308601 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11959.308601 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11959.308601 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11959.308601 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11959.308601 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11959.308601 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 102235 # number of replacements -system.cpu1.dcache.tags.tagsinuse 491.253867 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 2477501 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 102637 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 24.138478 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 45814117000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 491.253867 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.959480 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.959480 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 402 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 11642464 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 11642464 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 1521331 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1521331 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 890954 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 890954 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 30283 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 30283 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 29173 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 29173 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 2412285 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 2412285 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 2412285 # number of overall hits -system.cpu1.dcache.overall_hits::total 2412285 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 196472 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 196472 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 206616 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 206616 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5011 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 5011 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 2898 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 2898 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 403088 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 403088 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 403088 # number of overall misses -system.cpu1.dcache.overall_misses::total 403088 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2745758970 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2745758970 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 6806020354 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 6806020354 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 50048997 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 50048997 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 21170434 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 21170434 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 9551779324 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 9551779324 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 9551779324 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 9551779324 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 1717803 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1717803 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1097570 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1097570 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 35294 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 35294 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 32071 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 32071 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 2815373 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 2815373 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 2815373 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 2815373 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.114374 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.114374 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.188249 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.188249 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.141979 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.141979 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.090362 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.090362 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.143174 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.143174 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.143174 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.143174 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13975.319486 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 13975.319486 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32940.432270 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 32940.432270 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9987.826182 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9987.826182 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7305.187716 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7305.187716 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23696.511243 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 23696.511243 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23696.511243 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 23696.511243 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 206242 # number of cycles access was blocked +system.cpu1.dcache.tags.replacements 45361 # number of replacements +system.cpu1.dcache.tags.tagsinuse 428.999436 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 1451630 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 45680 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 31.778240 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 1880566804000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 428.999436 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.837890 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.837890 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 319 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 319 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.623047 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 6609919 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 6609919 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 960992 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 960992 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 477143 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 477143 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 12504 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 12504 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 10799 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 10799 # 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number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 6156210526 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 6156210526 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 6156210526 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 6156210526 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 1042294 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 1042294 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 572688 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 572688 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 13660 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 13660 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 11372 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 11372 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 1614982 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 1614982 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 1614982 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 1614982 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.078003 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.078003 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.166836 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.166836 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.084627 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.084627 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.050387 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.050387 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.109504 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.109504 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.109504 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.109504 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13654.978906 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13654.978906 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 52813.160615 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 52813.160615 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12028.977509 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 12028.977509 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7211.300175 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7211.300175 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 34810.941243 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 34810.941243 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 34810.941243 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 34810.941243 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 236601 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 3728 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 6165 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 55.322425 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 38.378102 # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 67781 # number of writebacks -system.cpu1.dcache.writebacks::total 67781 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 121809 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 121809 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 169922 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 169922 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 539 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 539 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 291731 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 291731 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 291731 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 291731 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 74663 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 74663 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 36694 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 36694 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4472 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4472 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 2897 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 2897 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 111357 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 111357 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 111357 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 111357 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 836811454 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 836811454 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 998585721 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 998585721 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 34130252 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 34130252 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 15375566 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 15375566 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1835397175 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 1835397175 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1835397175 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 1835397175 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 23621500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 23621500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 617644004 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 617644004 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 641265504 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 641265504 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.043464 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.043464 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033432 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.033432 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.126707 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.126707 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.090331 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.090331 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.039553 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.039553 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.039553 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.039553 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11207.846644 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11207.846644 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27213.869325 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27213.869325 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7631.988372 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7631.988372 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5307.409734 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5307.409734 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16482.099688 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16482.099688 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16482.099688 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16482.099688 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 24956 # number of writebacks +system.cpu1.dcache.writebacks::total 24956 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 46173 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 46173 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 80581 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 80581 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 235 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 235 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 126754 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 126754 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 126754 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 126754 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 35129 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 35129 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 14964 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 14964 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 921 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 921 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 573 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 573 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 50093 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 50093 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 50093 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 50093 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 398615352 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 398615352 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 730663501 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 730663501 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 8358752 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 8358752 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 2984925 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 2984925 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1129278853 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 1129278853 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1129278853 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 1129278853 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 22397000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 22397000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 533147000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 533147000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 555544000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 555544000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033704 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033704 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.026129 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.026129 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.067423 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.067423 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.050387 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.050387 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031018 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.031018 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031018 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.031018 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11347.187566 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11347.187566 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 48828.087477 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 48828.087477 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 9075.735071 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9075.735071 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5209.293194 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5209.293194 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22543.645879 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22543.645879 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22543.645879 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22543.645879 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -2085,170 +2087,161 @@ system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6589 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 184914 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 65370 40.53% 40.53% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.08% 40.61% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1926 1.19% 41.80% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 186 0.12% 41.92% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 93691 58.08% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 161304 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 64362 49.21% 49.21% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.10% 49.31% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1926 1.47% 50.79% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 186 0.14% 50.93% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 64176 49.07% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 130781 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1863832959500 97.81% 97.81% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 63684000 0.00% 97.81% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 569763500 0.03% 97.84% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 89287000 0.00% 97.84% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 41094897500 2.16% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1905650591500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.984580 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6410 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 202830 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 72673 40.72% 40.72% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.07% 40.80% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1926 1.08% 41.87% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 6 0.00% 41.88% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 103726 58.12% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 178462 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 71304 49.29% 49.29% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.09% 49.38% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1926 1.33% 50.71% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 6 0.00% 50.72% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 71298 49.28% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 144665 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1863558813000 97.76% 97.76% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 63845500 0.00% 97.77% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 565237000 0.03% 97.80% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 3385500 0.00% 97.80% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 42015112000 2.20% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1906206393000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.981162 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.684975 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.810773 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 7 3.32% 3.32% # number of syscalls executed -system.cpu0.kern.syscall::3 17 8.06% 11.37% # number of syscalls executed -system.cpu0.kern.syscall::4 4 1.90% 13.27% # number of syscalls executed -system.cpu0.kern.syscall::6 29 13.74% 27.01% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.47% 27.49% # number of syscalls executed -system.cpu0.kern.syscall::17 10 4.74% 32.23% # number of syscalls executed -system.cpu0.kern.syscall::19 7 3.32% 35.55% # number of syscalls executed -system.cpu0.kern.syscall::20 4 1.90% 37.44% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.47% 37.91% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.42% 39.34% # number of syscalls executed -system.cpu0.kern.syscall::33 8 3.79% 43.13% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.95% 44.08% # number of syscalls executed -system.cpu0.kern.syscall::45 37 17.54% 61.61% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.42% 63.03% # number of syscalls executed -system.cpu0.kern.syscall::48 8 3.79% 66.82% # number of syscalls executed -system.cpu0.kern.syscall::54 9 4.27% 71.09% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.47% 71.56% # number of syscalls executed -system.cpu0.kern.syscall::59 5 2.37% 73.93% # number of syscalls executed -system.cpu0.kern.syscall::71 27 12.80% 86.73% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.42% 88.15% # number of syscalls executed -system.cpu0.kern.syscall::74 7 3.32% 91.47% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.47% 91.94% # number of syscalls executed -system.cpu0.kern.syscall::90 2 0.95% 92.89% # number of syscalls executed -system.cpu0.kern.syscall::92 7 3.32% 96.21% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.95% 97.16% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.95% 98.10% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.47% 98.58% # number of syscalls executed -system.cpu0.kern.syscall::144 1 0.47% 99.05% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.95% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 211 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.687369 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.810621 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed +system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed +system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed +system.cpu0.kern.syscall::6 33 14.10% 27.78% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.43% 28.21% # number of syscalls executed +system.cpu0.kern.syscall::17 10 4.27% 32.48% # number of syscalls executed +system.cpu0.kern.syscall::19 10 4.27% 36.75% # number of syscalls executed +system.cpu0.kern.syscall::20 6 2.56% 39.32% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.43% 39.74% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.28% 41.03% # number of syscalls executed +system.cpu0.kern.syscall::33 8 3.42% 44.44% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.85% 45.30% # number of syscalls executed +system.cpu0.kern.syscall::45 39 16.67% 61.97% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.28% 63.25% # number of syscalls executed +system.cpu0.kern.syscall::48 10 4.27% 67.52% # number of syscalls executed +system.cpu0.kern.syscall::54 10 4.27% 71.79% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.43% 72.22% # number of syscalls executed +system.cpu0.kern.syscall::59 6 2.56% 74.79% # number of syscalls executed +system.cpu0.kern.syscall::71 27 11.54% 86.32% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.28% 87.61% # number of syscalls executed +system.cpu0.kern.syscall::74 7 2.99% 90.60% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.43% 91.03% # number of syscalls executed +system.cpu0.kern.syscall::90 3 1.28% 92.31% # number of syscalls executed +system.cpu0.kern.syscall::92 9 3.85% 96.15% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.85% 97.01% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.85% 97.86% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.43% 98.29% # number of syscalls executed +system.cpu0.kern.syscall::144 2 0.85% 99.15% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.85% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 234 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 277 0.16% 0.16% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.16% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.16% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.17% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3529 2.08% 2.24% # number of callpals executed -system.cpu0.kern.callpal::tbi 48 0.03% 2.27% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.27% # number of callpals executed -system.cpu0.kern.callpal::swpipl 154533 90.92% 93.20% # number of callpals executed -system.cpu0.kern.callpal::rdps 6537 3.85% 97.04% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 97.04% # number of callpals executed -system.cpu0.kern.callpal::wrusp 4 0.00% 97.05% # number of callpals executed -system.cpu0.kern.callpal::rdusp 8 0.00% 97.05% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 97.05% # number of callpals executed -system.cpu0.kern.callpal::rti 4527 2.66% 99.72% # number of callpals executed -system.cpu0.kern.callpal::callsys 345 0.20% 99.92% # number of callpals executed -system.cpu0.kern.callpal::imb 137 0.08% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 169959 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7072 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1287 # number of protection mode switches +system.cpu0.kern.callpal::wripir 95 0.05% 0.05% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.05% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.05% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.05% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3930 2.10% 2.15% # number of callpals executed +system.cpu0.kern.callpal::tbi 51 0.03% 2.18% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.18% # number of callpals executed +system.cpu0.kern.callpal::swpipl 171605 91.48% 93.66% # number of callpals executed +system.cpu0.kern.callpal::rdps 6547 3.49% 97.15% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 97.15% # number of callpals executed +system.cpu0.kern.callpal::wrusp 4 0.00% 97.15% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.00% 97.16% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 97.16% # number of callpals executed +system.cpu0.kern.callpal::rti 4793 2.56% 99.72% # number of callpals executed +system.cpu0.kern.callpal::callsys 394 0.21% 99.93% # number of callpals executed +system.cpu0.kern.callpal::imb 139 0.07% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 187581 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7378 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1370 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1286 -system.cpu0.kern.mode_good::user 1287 +system.cpu0.kern.mode_good::kernel 1369 +system.cpu0.kern.mode_good::user 1370 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.181844 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.185552 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.307812 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1903707301000 99.90% 99.90% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1943282500 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.313100 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1904135221500 99.89% 99.89% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2071163500 0.11% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3530 # number of times the context was actually changed +system.cpu0.kern.swap_context 3931 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2439 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 54740 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 16948 36.40% 36.40% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1925 4.13% 40.53% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 277 0.59% 41.13% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 27412 58.87% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 46562 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 16579 47.26% 47.26% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1925 5.49% 52.74% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 277 0.79% 53.53% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 16302 46.47% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 35083 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1874130150000 98.36% 98.36% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 532183000 0.03% 98.39% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 125676500 0.01% 98.40% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 30535391000 1.60% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1905323400500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.978228 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2254 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 34590 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 8916 31.91% 31.91% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1925 6.89% 38.80% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 95 0.34% 39.14% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 17006 60.86% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 27942 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 8908 45.12% 45.12% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1925 9.75% 54.88% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 95 0.48% 55.36% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 8813 44.64% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 19741 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1876395415500 98.45% 98.45% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 531818000 0.03% 98.48% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 44293500 0.00% 98.48% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 28895956000 1.52% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1905867483000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.999103 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.594703 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.753468 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::2 1 0.87% 0.87% # number of syscalls executed -system.cpu1.kern.syscall::3 13 11.30% 12.17% # number of syscalls executed -system.cpu1.kern.syscall::6 13 11.30% 23.48% # number of syscalls executed -system.cpu1.kern.syscall::15 1 0.87% 24.35% # number of syscalls executed -system.cpu1.kern.syscall::17 5 4.35% 28.70% # number of syscalls executed -system.cpu1.kern.syscall::19 3 2.61% 31.30% # number of syscalls executed -system.cpu1.kern.syscall::20 2 1.74% 33.04% # number of syscalls executed -system.cpu1.kern.syscall::23 3 2.61% 35.65% # number of syscalls executed -system.cpu1.kern.syscall::24 3 2.61% 38.26% # number of syscalls executed -system.cpu1.kern.syscall::33 3 2.61% 40.87% # number of syscalls executed -system.cpu1.kern.syscall::45 17 14.78% 55.65% # number of syscalls executed -system.cpu1.kern.syscall::47 3 2.61% 58.26% # number of syscalls executed -system.cpu1.kern.syscall::48 2 1.74% 60.00% # number of syscalls executed -system.cpu1.kern.syscall::54 1 0.87% 60.87% # number of syscalls executed -system.cpu1.kern.syscall::59 2 1.74% 62.61% # number of syscalls executed -system.cpu1.kern.syscall::71 27 23.48% 86.09% # number of syscalls executed -system.cpu1.kern.syscall::74 9 7.83% 93.91% # number of syscalls executed -system.cpu1.kern.syscall::90 1 0.87% 94.78% # number of syscalls executed -system.cpu1.kern.syscall::92 2 1.74% 96.52% # number of syscalls executed -system.cpu1.kern.syscall::132 3 2.61% 99.13% # number of syscalls executed -system.cpu1.kern.syscall::144 1 0.87% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 115 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.518229 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.706499 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed +system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed +system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed +system.cpu1.kern.syscall::17 5 5.43% 27.17% # number of syscalls executed +system.cpu1.kern.syscall::23 3 3.26% 30.43% # number of syscalls executed +system.cpu1.kern.syscall::24 3 3.26% 33.70% # number of syscalls executed +system.cpu1.kern.syscall::33 3 3.26% 36.96% # number of syscalls executed +system.cpu1.kern.syscall::45 15 16.30% 53.26% # number of syscalls executed +system.cpu1.kern.syscall::47 3 3.26% 56.52% # number of syscalls executed +system.cpu1.kern.syscall::59 1 1.09% 57.61% # number of syscalls executed +system.cpu1.kern.syscall::71 27 29.35% 86.96% # number of syscalls executed +system.cpu1.kern.syscall::74 9 9.78% 96.74% # number of syscalls executed +system.cpu1.kern.syscall::132 3 3.26% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 92 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 186 0.39% 0.39% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.39% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.39% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1067 2.22% 2.61% # number of callpals executed -system.cpu1.kern.callpal::tbi 6 0.01% 2.63% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 2.64% # number of callpals executed -system.cpu1.kern.callpal::swpipl 41329 85.97% 88.61% # number of callpals executed -system.cpu1.kern.callpal::rdps 2224 4.63% 93.23% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 93.23% # number of callpals executed -system.cpu1.kern.callpal::wrusp 3 0.01% 93.24% # number of callpals executed -system.cpu1.kern.callpal::rdusp 1 0.00% 93.24% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 93.25% # number of callpals executed -system.cpu1.kern.callpal::rti 3030 6.30% 99.55% # number of callpals executed -system.cpu1.kern.callpal::callsys 172 0.36% 99.91% # number of callpals executed -system.cpu1.kern.callpal::imb 43 0.09% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 6 0.02% 0.02% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal::swpctx 298 1.04% 1.07% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.01% 1.08% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.02% 1.11% # number of callpals executed +system.cpu1.kern.callpal::swpipl 23527 82.20% 83.30% # number of callpals executed +system.cpu1.kern.callpal::rdps 2214 7.74% 91.04% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 91.04% # number of callpals executed +system.cpu1.kern.callpal::wrusp 3 0.01% 91.05% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 91.06% # number of callpals executed +system.cpu1.kern.callpal::rti 2394 8.36% 99.43% # number of callpals executed +system.cpu1.kern.callpal::callsys 121 0.42% 99.85% # number of callpals executed +system.cpu1.kern.callpal::imb 42 0.15% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 48076 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1341 # number of protection mode switches -system.cpu1.kern.mode_switch::user 460 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2398 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 662 -system.cpu1.kern.mode_good::user 460 -system.cpu1.kern.mode_good::idle 202 -system.cpu1.kern.mode_switch_good::kernel 0.493661 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 28623 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 659 # number of protection mode switches +system.cpu1.kern.mode_switch::user 367 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2036 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 386 +system.cpu1.kern.mode_good::user 367 +system.cpu1.kern.mode_good::idle 19 +system.cpu1.kern.mode_switch_good::kernel 0.585736 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.084237 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.315313 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 4271038500 0.22% 0.22% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 809340000 0.04% 0.27% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1900232555000 99.73% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1068 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.009332 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.252123 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 1444110500 0.08% 0.08% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 692193000 0.04% 0.11% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1903401131500 99.89% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 299 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal index 25fe063e3..15c215278 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal @@ -27,7 +27,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
memcluster 1, usage 0, start 392, end 16384
freeing pages 1069:16384
reserving pages 1069:1070 -
4096K Bcache detected; load hit latency 30 cycles, load miss latency 134 cycles +
4096K Bcache detected; load hit latency 30 cycles, load miss latency 140 cycles
SMP: 2 CPUs probed -- cpu_present_mask = 3
Built 1 zonelists
Kernel command line: root=/dev/hda1 console=ttyS0 diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini index 80c9d1506..17f1f9290 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini @@ -15,17 +15,18 @@ boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 cache_line_size=64 clk_domain=system.clk_domain -console=/dist/binaries/console +console=/home/stever/m5/m5_system_2.0b3/binaries/console eventq_index=0 init_param=0 -kernel=/dist/binaries/vmlinux +kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -pal=/dist/binaries/ts_osfpal -readfile=tests/halt.sh +pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal +readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh symbolfile= system_rev=1024 system_type=34 @@ -131,6 +132,7 @@ smtLSQThreshold=100 smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 +socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false @@ -632,7 +634,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/disks/linux-latest.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img read_only=true [system.disk2] @@ -655,7 +657,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/disks/linux-bigswap2.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -741,9 +743,9 @@ warn_access= pio=system.membus.default [system.physmem] -type=SimpleDRAM +type=DRAMCtrl activation_limit=4 -addr_mapping=RaBaChCo +addr_mapping=RoRaBaChCo banks_per_rank=8 burst_length=8 channels=1 @@ -754,27 +756,33 @@ device_rowbuffer_size=1024 devices_per_rank=8 eventq_index=0 in_addr_map=true +max_accesses_per_row=16 mem_sched_policy=frfcfs +min_writes_per_switch=16 null=false -page_policy=open +page_policy=open_adaptive range=0:134217727 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 +tCK=1250 tCL=13750 tRAS=35000 tRCD=13750 tREFI=7800000 -tRFC=300000 +tRFC=260000 tRP=13750 -tRRD=6250 +tRRD=6000 +tRTP=7500 +tRTW=2500 +tWR=15000 tWTR=7500 -tXAW=40000 -write_buffer_size=32 -write_high_thresh_perc=70 -write_low_thresh_perc=0 +tXAW=30000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 port=system.membus.master[1] [system.simple_disk] @@ -787,7 +795,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage eventq_index=0 -image_file=/dist/disks/linux-latest.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout index 6b0c7bafe..e834a5489 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout @@ -1,12 +1,14 @@ +Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3/simout +Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 16:27:55 -gem5 started Jan 22 2014 19:25:00 -gem5 executing on u200540-lin -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 +gem5 compiled Jun 21 2014 10:36:29 +gem5 started Jun 21 2014 13:05:52 +gem5 executing on phenom +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/binaries/vmlinux +info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1860197780500 because m5_exit instruction encountered +Exiting @ tick 1860172195000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index eda12d3cf..f07e7eac0 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,127 +1,127 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.860188 # Number of seconds simulated -sim_ticks 1860187818000 # Number of ticks simulated -final_tick 1860187818000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.860172 # Number of seconds simulated +sim_ticks 1860172195000 # Number of ticks simulated +final_tick 1860172195000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 129673 # Simulator instruction rate (inst/s) -host_op_rate 129673 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4553007725 # Simulator tick rate (ticks/s) -host_mem_usage 348812 # Number of bytes of host memory used -host_seconds 408.56 # Real time elapsed on the host -sim_insts 52979638 # Number of instructions simulated -sim_ops 52979638 # Number of ops (including micro ops) simulated +host_inst_rate 152063 # Simulator instruction rate (inst/s) +host_op_rate 152063 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5340733222 # Simulator tick rate (ticks/s) +host_mem_usage 304984 # Number of bytes of host memory used +host_seconds 348.30 # Real time elapsed on the host +sim_insts 52963419 # Number of instructions simulated +sim_ops 52963419 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 963200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24881344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 965120 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24879104 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory -system.physmem.bytes_read::total 28496832 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 963200 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 963200 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7516608 # Number of bytes written to this memory -system.physmem.bytes_written::total 7516608 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15050 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388771 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 28496512 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 965120 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 965120 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7515712 # Number of bytes written to this memory +system.physmem.bytes_written::total 7515712 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15080 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388736 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory -system.physmem.num_reads::total 445263 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117447 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117447 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 517797 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13375716 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1425817 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15319331 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 517797 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 517797 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4040779 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4040779 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4040779 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 517797 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13375716 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1425817 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19360110 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 445263 # Number of read requests accepted -system.physmem.writeReqs 117447 # Number of write requests accepted -system.physmem.readBursts 445263 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 117447 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 28490624 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6208 # Total number of bytes read from write queue -system.physmem.bytesWritten 7515520 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 28496832 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7516608 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 97 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 445258 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117433 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117433 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 518834 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13374624 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1425829 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15319287 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 518834 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 518834 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4040331 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4040331 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4040331 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 518834 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13374624 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1425829 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19359618 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 445258 # Number of read requests accepted +system.physmem.writeReqs 117433 # Number of write requests accepted +system.physmem.readBursts 445258 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 117433 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 28490432 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6080 # Total number of bytes read from write queue +system.physmem.bytesWritten 7513664 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 28496512 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7515712 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 95 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 171 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 28211 # Per bank write bursts -system.physmem.perBankRdBursts::1 27992 # Per bank write bursts -system.physmem.perBankRdBursts::2 28433 # Per bank write bursts -system.physmem.perBankRdBursts::3 27987 # Per bank write bursts -system.physmem.perBankRdBursts::4 27796 # Per bank write bursts -system.physmem.perBankRdBursts::5 27217 # Per bank write bursts -system.physmem.perBankRdBursts::6 27269 # Per bank write bursts -system.physmem.perBankRdBursts::7 27319 # Per bank write bursts -system.physmem.perBankRdBursts::8 27690 # Per bank write bursts -system.physmem.perBankRdBursts::9 27272 # Per bank write bursts -system.physmem.perBankRdBursts::10 28021 # Per bank write bursts -system.physmem.perBankRdBursts::11 27509 # Per bank write bursts -system.physmem.perBankRdBursts::12 27548 # Per bank write bursts -system.physmem.perBankRdBursts::13 28237 # Per bank write bursts -system.physmem.perBankRdBursts::14 28335 # Per bank write bursts -system.physmem.perBankRdBursts::15 28330 # Per bank write bursts -system.physmem.perBankWrBursts::0 7921 # Per bank write bursts -system.physmem.perBankWrBursts::1 7511 # Per bank write bursts -system.physmem.perBankWrBursts::2 7946 # Per bank write bursts -system.physmem.perBankWrBursts::3 7492 # Per bank write bursts -system.physmem.perBankWrBursts::4 7346 # Per bank write bursts -system.physmem.perBankWrBursts::5 6678 # Per bank write bursts -system.physmem.perBankWrBursts::6 6778 # Per bank write bursts -system.physmem.perBankWrBursts::7 6711 # Per bank write bursts -system.physmem.perBankWrBursts::8 7130 # Per bank write bursts -system.physmem.perBankWrBursts::9 6681 # Per bank write bursts -system.physmem.perBankWrBursts::10 7414 # Per bank write bursts -system.physmem.perBankWrBursts::11 6966 # Per bank write bursts -system.physmem.perBankWrBursts::12 7109 # Per bank write bursts -system.physmem.perBankWrBursts::13 7879 # Per bank write bursts -system.physmem.perBankWrBursts::14 8056 # Per bank write bursts -system.physmem.perBankWrBursts::15 7812 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 176 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 28223 # Per bank write bursts +system.physmem.perBankRdBursts::1 27968 # Per bank write bursts +system.physmem.perBankRdBursts::2 28292 # Per bank write bursts +system.physmem.perBankRdBursts::3 27927 # Per bank write bursts +system.physmem.perBankRdBursts::4 27805 # Per bank write bursts +system.physmem.perBankRdBursts::5 27242 # Per bank write bursts +system.physmem.perBankRdBursts::6 27352 # Per bank write bursts +system.physmem.perBankRdBursts::7 27274 # Per bank write bursts +system.physmem.perBankRdBursts::8 27691 # Per bank write bursts +system.physmem.perBankRdBursts::9 27508 # Per bank write bursts +system.physmem.perBankRdBursts::10 27933 # Per bank write bursts +system.physmem.perBankRdBursts::11 27527 # Per bank write bursts +system.physmem.perBankRdBursts::12 27552 # Per bank write bursts +system.physmem.perBankRdBursts::13 28225 # Per bank write bursts +system.physmem.perBankRdBursts::14 28330 # Per bank write bursts +system.physmem.perBankRdBursts::15 28314 # Per bank write bursts +system.physmem.perBankWrBursts::0 7932 # Per bank write bursts +system.physmem.perBankWrBursts::1 7496 # Per bank write bursts +system.physmem.perBankWrBursts::2 7821 # Per bank write bursts +system.physmem.perBankWrBursts::3 7427 # Per bank write bursts +system.physmem.perBankWrBursts::4 7353 # Per bank write bursts +system.physmem.perBankWrBursts::5 6703 # Per bank write bursts +system.physmem.perBankWrBursts::6 6854 # Per bank write bursts +system.physmem.perBankWrBursts::7 6665 # Per bank write bursts +system.physmem.perBankWrBursts::8 7118 # Per bank write bursts +system.physmem.perBankWrBursts::9 6889 # Per bank write bursts +system.physmem.perBankWrBursts::10 7323 # Per bank write bursts +system.physmem.perBankWrBursts::11 6981 # Per bank write bursts +system.physmem.perBankWrBursts::12 7116 # Per bank write bursts +system.physmem.perBankWrBursts::13 7874 # Per bank write bursts +system.physmem.perBankWrBursts::14 8055 # Per bank write bursts +system.physmem.perBankWrBursts::15 7794 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 11 # Number of times write queue was full causing retry -system.physmem.totGap 1860182401000 # Total gap between requests +system.physmem.numWrRetry 10 # Number of times write queue was full causing retry +system.physmem.totGap 1860166839000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 445263 # Read request sizes (log2) +system.physmem.readPktSize::6 445258 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 117447 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 316668 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 59729 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 27667 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 5430 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2043 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 4389 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 3993 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 3992 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2540 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2192 # What read queue length does an incoming req see +system.physmem.writePktSize::6 117433 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 317162 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 38754 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 44609 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9021 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2051 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 4407 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 3954 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 3974 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2513 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2195 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 2171 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2086 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1617 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1588 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1906 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1882 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 2139 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1226 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 986 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 905 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 11 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 2106 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1630 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1618 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1898 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1857 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 2113 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1232 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 984 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 899 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -148,128 +148,128 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2272 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4755 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4891 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5082 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5274 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5526 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6873 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6071 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6268 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5967 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 924 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 916 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 938 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 867 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 935 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 954 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1048 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 998 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1359 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1592 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1859 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 2023 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1831 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1695 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 1731 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 1870 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 1643 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 821 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 17 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 63749 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 564.805095 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 351.189585 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 419.649920 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 13350 20.94% 20.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10335 16.21% 37.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4789 7.51% 44.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2797 4.39% 49.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2437 3.82% 52.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1576 2.47% 55.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1469 2.30% 57.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1613 2.53% 60.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 25383 39.82% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 63749 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6887 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 64.637723 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 16.523346 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2544.314640 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 6884 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1086 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4772 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4799 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4937 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5563 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5819 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6253 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6876 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6083 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 966 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 924 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 969 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 901 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 939 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 988 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1058 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 973 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1414 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1656 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1874 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1977 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1860 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1689 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 1697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 1803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 1633 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 837 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 395 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 207 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 16 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 63680 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 565.384925 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 351.672479 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 419.574374 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13299 20.88% 20.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10397 16.33% 37.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4628 7.27% 44.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2746 4.31% 48.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2553 4.01% 52.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1655 2.60% 55.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1376 2.16% 57.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1696 2.66% 60.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 25330 39.78% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 63680 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6888 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 64.625581 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 16.554610 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2544.325145 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 6885 99.96% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.01% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6887 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6887 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.050966 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.814496 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 3.834643 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 5493 79.76% 79.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 28 0.41% 80.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 690 10.02% 90.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 216 3.14% 93.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 116 1.68% 95.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 20 0.29% 95.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 25 0.36% 95.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 93 1.35% 97.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 19 0.28% 97.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 44 0.64% 97.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 11 0.16% 98.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 7 0.10% 98.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 8 0.12% 98.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 16 0.23% 98.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 2 0.03% 98.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 14 0.20% 98.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 9 0.13% 98.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::33 1 0.01% 98.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34 1 0.01% 98.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::35 3 0.04% 98.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36 2 0.03% 99.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::37 1 0.01% 99.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38 1 0.01% 99.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::39 2 0.03% 99.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40 7 0.10% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::41 4 0.06% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42 2 0.03% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::43 3 0.04% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44 1 0.01% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::45 4 0.06% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46 3 0.04% 99.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::47 3 0.04% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48 7 0.10% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50 4 0.06% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::51 1 0.01% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::53 1 0.01% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::54 1 0.01% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56 7 0.10% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::57 17 0.25% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6887 # Writes before turning the bus around for reads -system.physmem.totQLat 8647566500 # Total ticks spent queuing -system.physmem.totMemAccLat 16994429000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2225830000 # Total ticks spent in databus transfers -system.physmem.avgQLat 19425.49 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6888 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6888 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.044280 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.812634 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 3.762583 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 5511 80.01% 80.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 31 0.45% 80.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 662 9.61% 90.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 220 3.19% 93.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 110 1.60% 94.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 25 0.36% 95.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 25 0.36% 95.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 91 1.32% 96.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 22 0.32% 97.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 31 0.45% 97.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 12 0.17% 97.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 22 0.32% 98.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 6 0.09% 98.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 14 0.20% 98.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 3 0.04% 98.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 16 0.23% 98.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 12 0.17% 98.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34 7 0.10% 99.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::35 1 0.01% 99.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36 1 0.01% 99.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::37 3 0.04% 99.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38 4 0.06% 99.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::39 4 0.06% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40 4 0.06% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::41 6 0.09% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::43 3 0.04% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::46 3 0.04% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::47 7 0.10% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48 2 0.03% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::49 1 0.01% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50 2 0.03% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::51 2 0.03% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52 1 0.01% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::53 1 0.01% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::54 1 0.01% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::55 1 0.01% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56 8 0.12% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::57 12 0.17% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::58 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6888 # Writes before turning the bus around for reads +system.physmem.totQLat 8740437500 # Total ticks spent queuing +system.physmem.totMemAccLat 17087243750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2225815000 # Total ticks spent in databus transfers +system.physmem.avgQLat 19634.24 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 38175.49 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 38384.24 # Average memory access latency per DRAM burst system.physmem.avgRdBW 15.32 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 4.04 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 15.32 # Average system read bandwidth in MiByte/s @@ -278,64 +278,65 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.70 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.02 # Average write queue length when enqueuing -system.physmem.readRowHits 403062 # Number of row buffer hits during reads -system.physmem.writeRowHits 95784 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.54 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 81.56 # Row buffer hit rate for writes -system.physmem.avgGap 3305756.79 # Average gap between requests -system.physmem.pageHitRate 88.67 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 1761433244000 # Time in different power states -system.physmem.memoryStateTime::REF 62115560000 # Time in different power states +system.physmem.avgRdQLen 1.65 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.75 # Average write queue length when enqueuing +system.physmem.readRowHits 403028 # Number of row buffer hits during reads +system.physmem.writeRowHits 95855 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.53 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 81.63 # Row buffer hit rate for writes +system.physmem.avgGap 3305840.75 # Average gap between requests +system.physmem.pageHitRate 88.68 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 1761575145500 # Time in different power states +system.physmem.memoryStateTime::REF 62115040000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 36633312250 # Time in different power states +system.physmem.memoryStateTime::ACT 36476358250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 19402968 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 295944 # Transaction distribution -system.membus.trans_dist::ReadResp 295866 # Transaction distribution +system.membus.throughput 19402477 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 295985 # Transaction distribution +system.membus.trans_dist::ReadResp 295900 # Transaction distribution system.membus.trans_dist::WriteReq 9597 # Transaction distribution system.membus.trans_dist::WriteResp 9597 # Transaction distribution -system.membus.trans_dist::Writeback 117447 # Transaction distribution -system.membus.trans_dist::UpgradeReq 174 # Transaction distribution -system.membus.trans_dist::UpgradeResp 174 # Transaction distribution -system.membus.trans_dist::ReadExReq 156883 # Transaction distribution -system.membus.trans_dist::ReadExResp 156883 # Transaction distribution -system.membus.trans_dist::BadAddressError 78 # Transaction distribution +system.membus.trans_dist::Writeback 117433 # Transaction distribution +system.membus.trans_dist::UpgradeReq 178 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution +system.membus.trans_dist::UpgradeResp 179 # Transaction distribution +system.membus.trans_dist::ReadExReq 156844 # Transaction distribution +system.membus.trans_dist::ReadExResp 156844 # Transaction distribution +system.membus.trans_dist::BadAddressError 85 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33054 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884195 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 156 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884181 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 170 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917405 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124679 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124679 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 1042084 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44140 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30704384 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30748524 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30703168 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30747308 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309056 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 5309056 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 36057580 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 36057580 # Total data (bytes) +system.membus.tot_pkt_size::total 36056364 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 36056364 # Total data (bytes) system.membus.snoop_data_through_bus 35584 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 29864500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 29838500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1548275500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1526200750 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 98000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 104500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3770327047 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3755175800 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 376611244 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 376659242 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.261115 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.260971 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1710335896000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.261115 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.078820 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.078820 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1710335831000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.260971 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078811 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078811 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -349,14 +350,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21272883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21272883 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 12456693929 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 12456693929 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 12477966812 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 12477966812 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 12477966812 # number of overall miss cycles -system.iocache.overall_miss_latency::total 12477966812 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21134383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21134383 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 12441682213 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 12441682213 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 12462816596 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 12462816596 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 12462816596 # number of overall miss cycles +system.iocache.overall_miss_latency::total 12462816596 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -373,19 +374,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122964.641618 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 122964.641618 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 299785.664445 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 299785.664445 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 299052.529946 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 299052.529946 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 299052.529946 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 299052.529946 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 365915 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122164.063584 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 122164.063584 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 299424.389031 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 299424.389031 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 298689.433098 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 298689.433098 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 298689.433098 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 298689.433098 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 366119 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 28370 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 28395 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 12.897956 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 12.893784 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -399,14 +400,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12274883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12274883 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10293819441 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 10293819441 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 10306094324 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 10306094324 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 10306094324 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 10306094324 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12137383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12137383 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10278710729 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 10278710729 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 10290848112 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 10290848112 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 10290848112 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 10290848112 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -415,14 +416,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70953.080925 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 70953.080925 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 247733.428981 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 247733.428981 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 247000.463128 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 247000.463128 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 247000.463128 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 247000.463128 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70158.283237 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 70158.283237 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 247369.819239 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 247369.819239 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 246635.065596 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 246635.065596 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 246635.065596 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 246635.065596 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -436,36 +437,36 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.branchPred.lookups 13846630 # Number of BP lookups -system.cpu.branchPred.condPredicted 11622667 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 398238 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9513264 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5817388 # Number of BTB hits +system.cpu.branchPred.lookups 13973676 # Number of BP lookups +system.cpu.branchPred.condPredicted 11739131 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 397652 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9590938 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5932533 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 61.150284 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 900921 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 39034 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 61.855608 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 905503 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 38808 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9912884 # DTB read hits -system.cpu.dtb.read_misses 41215 # DTB read misses -system.cpu.dtb.read_acv 553 # DTB read access violations -system.cpu.dtb.read_accesses 941108 # DTB read accesses -system.cpu.dtb.write_hits 6599017 # DTB write hits -system.cpu.dtb.write_misses 10339 # DTB write misses -system.cpu.dtb.write_acv 401 # DTB write access violations -system.cpu.dtb.write_accesses 338138 # DTB write accesses -system.cpu.dtb.data_hits 16511901 # DTB hits -system.cpu.dtb.data_misses 51554 # DTB misses -system.cpu.dtb.data_acv 954 # DTB access violations -system.cpu.dtb.data_accesses 1279246 # DTB accesses -system.cpu.itb.fetch_hits 1308304 # ITB hits -system.cpu.itb.fetch_misses 36786 # ITB misses -system.cpu.itb.fetch_acv 1079 # ITB acv -system.cpu.itb.fetch_accesses 1345090 # ITB accesses +system.cpu.dtb.read_hits 10112222 # DTB read hits +system.cpu.dtb.read_misses 41745 # DTB read misses +system.cpu.dtb.read_acv 542 # DTB read access violations +system.cpu.dtb.read_accesses 945441 # DTB read accesses +system.cpu.dtb.write_hits 6611008 # DTB write hits +system.cpu.dtb.write_misses 10791 # DTB write misses +system.cpu.dtb.write_acv 413 # DTB write access violations +system.cpu.dtb.write_accesses 339727 # DTB write accesses +system.cpu.dtb.data_hits 16723230 # DTB hits +system.cpu.dtb.data_misses 52536 # DTB misses +system.cpu.dtb.data_acv 955 # DTB access violations +system.cpu.dtb.data_accesses 1285168 # DTB accesses +system.cpu.itb.fetch_hits 1309723 # ITB hits +system.cpu.itb.fetch_misses 39683 # ITB misses +system.cpu.itb.fetch_acv 1073 # ITB acv +system.cpu.itb.fetch_accesses 1349406 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -478,303 +479,304 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 121969353 # number of cpu cycles simulated +system.cpu.numCycles 121578156 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 28022459 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 70674133 # Number of instructions fetch has processed -system.cpu.fetch.Branches 13846630 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 6718309 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 13243332 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1983249 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 37995640 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 32164 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 254581 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 364654 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 235 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8542175 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 264688 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 81194854 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.870426 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.213908 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 28154197 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 72069959 # Number of instructions fetch has processed +system.cpu.fetch.Branches 13973676 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6838036 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 13462286 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2111809 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 36504135 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 32813 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 258219 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 367287 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 202 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8654218 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 283642 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 80169891 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.898965 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.245398 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 67951522 83.69% 83.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 854853 1.05% 84.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1698258 2.09% 86.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 823227 1.01% 87.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2753963 3.39% 91.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 558188 0.69% 91.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 642929 0.79% 92.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1006595 1.24% 93.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4905319 6.04% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 66707605 83.21% 83.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 850391 1.06% 84.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1701562 2.12% 86.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 829510 1.03% 87.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2814732 3.51% 90.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 566680 0.71% 91.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 649069 0.81% 92.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1061564 1.32% 93.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4988778 6.22% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 81194854 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.113525 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.579442 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 29206421 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 37679452 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 12104138 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 965352 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1239490 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 585042 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 42720 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 69357398 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 129450 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1239490 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 30354385 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 13996332 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 19984766 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 11324382 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4295497 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 65588313 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 7118 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 505148 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1530678 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 43795306 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 79617271 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 79438234 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 166586 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38180209 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5615089 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1682372 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 239607 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12205686 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10422971 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6895231 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1319326 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 854507 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 58152614 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2049745 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 56795087 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 97937 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6861282 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3503589 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1388801 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 81194854 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.699491 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.361721 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 80169891 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.114936 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.592787 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 28969141 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 36597720 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 12749238 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 505228 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1348563 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 587502 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 42619 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 70583559 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 129875 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1348563 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 29902418 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 12633582 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 20046715 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 11807818 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4430793 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 66640171 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 8986 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 787429 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 47943 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 1601274 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 44565634 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 80920867 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 80741427 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 166989 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38166970 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 6398656 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1681821 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 238696 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 9832739 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10696003 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 7004082 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1336985 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 877203 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 58981840 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2047452 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 57223975 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 117650 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 7712570 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4365148 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1386476 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 80169891 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.713784 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.404933 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 56519522 69.61% 69.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10856431 13.37% 82.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5145956 6.34% 89.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3402319 4.19% 93.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2626681 3.24% 96.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1459376 1.80% 98.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 753323 0.93% 99.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 333723 0.41% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 97523 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 56166624 70.06% 70.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10391261 12.96% 83.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 4679899 5.84% 88.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3142763 3.92% 92.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2796032 3.49% 96.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1647190 2.05% 98.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 895238 1.12% 99.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 353951 0.44% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 96933 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 81194854 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 80169891 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 92642 11.69% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 372744 47.05% 58.74% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 326922 41.26% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 98738 11.92% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 400158 48.30% 60.22% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 329520 39.78% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 38726894 68.19% 68.20% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 61723 0.11% 68.31% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10344006 18.21% 86.57% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6676923 11.76% 98.33% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 949012 1.67% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 38901419 67.98% 67.99% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 61759 0.11% 68.10% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 25607 0.04% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10584317 18.50% 86.65% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6690891 11.69% 98.34% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 949060 1.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 56795087 # Type of FU issued -system.cpu.iq.rate 0.465650 # Inst issue rate -system.cpu.iq.fu_busy_cnt 792308 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013950 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 194982001 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 66741051 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 55566428 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 693271 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 336387 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 327889 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 57217918 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 362191 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 598643 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 57223975 # Type of FU issued +system.cpu.iq.rate 0.470676 # Inst issue rate +system.cpu.iq.fu_busy_cnt 828416 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014477 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 194870458 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 68419457 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 55733530 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 693448 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 335810 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 328249 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 57682446 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 362659 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 614531 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1330641 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3245 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14147 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 517313 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1606237 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3745 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 13777 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 627539 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 17932 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 166827 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 18239 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 375591 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1239490 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 10213175 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 697716 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 63724678 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 681593 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10422971 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6895231 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1805950 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 512370 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 16905 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14147 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 202448 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 409860 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 612308 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 56329043 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 9982328 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 466043 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1348563 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 9312966 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 978337 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 64604997 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 590069 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10696003 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 7004082 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1802911 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 468863 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 377382 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 13777 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 204854 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 411482 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 616336 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 56685901 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 10182131 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 538073 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3522319 # number of nop insts executed -system.cpu.iew.exec_refs 16606918 # number of memory reference insts executed -system.cpu.iew.exec_branches 8922931 # Number of branches executed -system.cpu.iew.exec_stores 6624590 # Number of stores executed -system.cpu.iew.exec_rate 0.461829 # Inst execution rate -system.cpu.iew.wb_sent 56008659 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 55894317 # cumulative count of insts written-back -system.cpu.iew.wb_producers 27713107 # num instructions producing a value -system.cpu.iew.wb_consumers 37520284 # num instructions consuming a value +system.cpu.iew.exec_nop 3575705 # number of nop insts executed +system.cpu.iew.exec_refs 16819167 # number of memory reference insts executed +system.cpu.iew.exec_branches 8947461 # Number of branches executed +system.cpu.iew.exec_stores 6637036 # Number of stores executed +system.cpu.iew.exec_rate 0.466251 # Inst execution rate +system.cpu.iew.wb_sent 56177988 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 56061779 # cumulative count of insts written-back +system.cpu.iew.wb_producers 28606216 # num instructions producing a value +system.cpu.iew.wb_consumers 39617780 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.458265 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.738617 # average fanout of values written-back +system.cpu.iew.wb_rate 0.461117 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.722055 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 7436889 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 660944 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 566942 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 79955364 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.702522 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.631936 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 8325898 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 660976 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 566478 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 78821328 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.712415 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.665597 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 59166975 74.00% 74.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8627079 10.79% 84.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4603678 5.76% 90.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2536989 3.17% 93.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1507337 1.89% 95.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 611638 0.76% 96.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 523619 0.65% 97.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 528614 0.66% 97.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1849435 2.31% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 58682621 74.45% 74.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8193641 10.40% 84.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4257107 5.40% 90.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2319840 2.94% 93.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1767395 2.24% 95.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 615421 0.78% 96.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 496583 0.63% 96.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 549859 0.70% 97.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1938861 2.46% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 79955364 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56170432 # Number of instructions committed -system.cpu.commit.committedOps 56170432 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 78821328 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56153459 # Number of instructions committed +system.cpu.commit.committedOps 56153459 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15470248 # Number of memory references committed -system.cpu.commit.loads 9092330 # Number of loads committed -system.cpu.commit.membars 226348 # Number of memory barriers committed -system.cpu.commit.branches 8439871 # Number of branches committed +system.cpu.commit.refs 15466309 # Number of memory references committed +system.cpu.commit.loads 9089766 # Number of loads committed +system.cpu.commit.membars 226357 # Number of memory barriers committed +system.cpu.commit.branches 8438044 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52020070 # Number of committed integer instructions. -system.cpu.commit.function_calls 740568 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 3198067 5.69% 5.69% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 36230888 64.50% 70.20% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 60673 0.11% 70.30% # Class of committed instruction +system.cpu.commit.int_insts 52003822 # Number of committed integer instructions. +system.cpu.commit.function_calls 740374 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 3197313 5.69% 5.69% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 36218566 64.50% 70.19% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 60658 0.11% 70.30% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.30% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 25607 0.05% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 3636 0.01% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 9318678 16.59% 86.95% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 6383871 11.37% 98.31% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 949012 1.69% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 3636 0.01% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 9316123 16.59% 86.94% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 6382496 11.37% 98.31% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 949060 1.69% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 56170432 # Class of committed instruction -system.cpu.commit.bw_lim_events 1849435 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 56153459 # Class of committed instruction +system.cpu.commit.bw_lim_events 1938861 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 141463709 # The number of ROB reads -system.cpu.rob.rob_writes 128455843 # The number of ROB writes -system.cpu.timesIdled 1197783 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 40774499 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3598399845 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 52979638 # Number of Instructions Simulated -system.cpu.committedOps 52979638 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.302193 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.302193 # CPI: Total CPI of All Threads -system.cpu.ipc 0.434368 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.434368 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 73867254 # number of integer regfile reads -system.cpu.int_regfile_writes 40307997 # number of integer regfile writes -system.cpu.fp_regfile_reads 166020 # number of floating regfile reads -system.cpu.fp_regfile_writes 167441 # number of floating regfile writes -system.cpu.misc_regfile_reads 2027897 # number of misc regfile reads -system.cpu.misc_regfile_writes 938938 # number of misc regfile writes +system.cpu.rob.rob_reads 141112277 # The number of ROB reads +system.cpu.rob.rob_writes 130308588 # The number of ROB writes +system.cpu.timesIdled 1194216 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 41408265 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3598759795 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 52963419 # Number of Instructions Simulated +system.cpu.committedOps 52963419 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 2.295512 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.295512 # CPI: Total CPI of All Threads +system.cpu.ipc 0.435633 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.435633 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 74250743 # number of integer regfile reads +system.cpu.int_regfile_writes 40442410 # number of integer regfile writes +system.cpu.fp_regfile_reads 166399 # number of floating regfile reads +system.cpu.fp_regfile_writes 167429 # number of floating regfile writes +system.cpu.misc_regfile_reads 2028427 # number of misc regfile reads +system.cpu.misc_regfile_writes 938976 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -806,7 +808,7 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.iobus.throughput 1454556 # Throughput (bytes/s) +system.iobus.throughput 1454569 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution system.iobus.trans_dist::WriteReq 51149 # Transaction distribution @@ -866,241 +868,245 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 380172568 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 380163354 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23457000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 43172756 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 43205758 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.throughput 111944057 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2118154 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2118059 # Transaction distribution +system.cpu.toL2Bus.throughput 111909594 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2117185 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2117083 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9597 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9597 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 840946 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 62 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 840753 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 64 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 64 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 342489 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 300938 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 78 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2020220 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3677927 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5698147 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64643392 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143586284 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 208229676 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 208219628 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 17344 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 2480508998 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::UpgradeResp 66 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 342629 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 301078 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 85 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2018148 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3678150 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5696298 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64577024 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143586668 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 208163692 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 208153644 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 17472 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 2479804999 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1518532368 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1516964420 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2189805164 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2185370157 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.icache.tags.replacements 1009436 # number of replacements -system.cpu.icache.tags.tagsinuse 509.668112 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 7476172 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1009944 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 7.402561 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 26651967250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.668112 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.995446 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.995446 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1008400 # number of replacements +system.cpu.icache.tags.tagsinuse 509.648597 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 7589401 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1008908 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 7.522392 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 26586363250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.648597 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.995407 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.995407 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 314 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 9552342 # Number of tag accesses -system.cpu.icache.tags.data_accesses 9552342 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 7476173 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7476173 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7476173 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7476173 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7476173 # number of overall hits -system.cpu.icache.overall_hits::total 7476173 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1066002 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1066002 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1066002 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1066002 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1066002 # number of overall misses -system.cpu.icache.overall_misses::total 1066002 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14786308436 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14786308436 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14786308436 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14786308436 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14786308436 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14786308436 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8542175 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8542175 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8542175 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8542175 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8542175 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8542175 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124793 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.124793 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.124793 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.124793 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.124793 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.124793 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13870.807406 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13870.807406 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13870.807406 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13870.807406 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13870.807406 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13870.807406 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 4221 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 9663349 # Number of tag accesses +system.cpu.icache.tags.data_accesses 9663349 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 7589402 # 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average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58348.822962 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58562.427136 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64075.443074 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58348.822962 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58562.427136 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1182,168 +1196,168 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1401230 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.994514 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 11803041 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1401742 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 8.420266 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 25812000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.994514 # Average occupied blocks per requestor +system.cpu.dcache.tags.replacements 1401429 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.994598 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 11820645 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1401941 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 8.431628 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 25377000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.994598 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999989 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 417 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 91 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 415 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 95 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63715251 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63715251 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7198260 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7198260 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4203038 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4203038 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 186010 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 186010 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 215511 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 215511 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 11401298 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 11401298 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 11401298 # number of overall hits -system.cpu.dcache.overall_hits::total 11401298 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1808147 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1808147 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1944666 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1944666 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 22743 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22743 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 63732446 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63732446 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7221951 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7221951 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4197394 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4197394 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 185535 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 185535 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 215521 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 215521 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 11419345 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 11419345 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 11419345 # number of overall hits +system.cpu.dcache.overall_hits::total 11419345 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1789877 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1789877 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1948925 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1948925 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 23421 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 23421 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3752813 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3752813 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3752813 # number of overall misses -system.cpu.dcache.overall_misses::total 3752813 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 40323855155 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 40323855155 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 76523868035 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 76523868035 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 322545000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 322545000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 26000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 26000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 116847723190 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 116847723190 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 116847723190 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 116847723190 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9006407 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9006407 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6147704 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6147704 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 208753 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 208753 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 215513 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 215513 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15154111 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15154111 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15154111 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15154111 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.200762 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.200762 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316324 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.316324 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.108947 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.108947 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_misses::cpu.data 3738802 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3738802 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3738802 # number of overall misses +system.cpu.dcache.overall_misses::total 3738802 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 40163370133 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 40163370133 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 77928512640 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 77928512640 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 358310999 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 358310999 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 38001 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 38001 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 118091882773 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 118091882773 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 118091882773 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 118091882773 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9011828 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9011828 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6146319 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6146319 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 208956 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 208956 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 215523 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 215523 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15158147 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15158147 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15158147 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15158147 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.198614 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.198614 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.317088 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.317088 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.112086 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.112086 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000009 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000009 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.247643 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.247643 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.247643 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.247643 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22301.204025 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 22301.204025 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39350.648407 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39350.648407 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14182.165941 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14182.165941 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31136.036672 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31136.036672 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31136.036672 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31136.036672 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 3013190 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 829 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 80012 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 37.659226 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 118.428571 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.246653 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.246653 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.246653 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.246653 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22439.178856 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 22439.178856 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39985.383039 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39985.383039 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15298.706247 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15298.706247 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 19000.500000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 19000.500000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31585.487216 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31585.487216 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31585.487216 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31585.487216 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 3437281 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 992 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 114395 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 8 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.047476 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 124 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 840946 # number of writebacks -system.cpu.dcache.writebacks::total 840946 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 724204 # 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number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2354295 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2354295 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2354295 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1084028 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1084028 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300479 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 300479 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17582 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17582 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1384285 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1384285 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1384285 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1384285 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27275514507 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 27275514507 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11674414609 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11674414609 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 201282500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 201282500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 22000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 38949929116 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 38949929116 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 38949929116 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 38949929116 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424067500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424067500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997567998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997567998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421635498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421635498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120352 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120352 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048854 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048854 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.084296 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.084296 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 1384507 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1384507 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1384507 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1384507 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27275332511 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 27275332511 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11834545572 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11834545572 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 200445001 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 200445001 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 33999 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 33999 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 39109878083 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 39109878083 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 39109878083 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 39109878083 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424085500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424085500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997539998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997539998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421625498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421625498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120289 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120289 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048888 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048888 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.084142 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.084142 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000009 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091347 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091347 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091347 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091347 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25163.236911 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25163.236911 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38870.403104 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38870.403104 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11438.455419 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11438.455419 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28137.218214 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28137.218214 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28137.218214 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 28137.218214 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091337 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091337 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091337 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091337 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25161.095941 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25161.095941 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39385.599566 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39385.599566 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11400.580196 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11400.580196 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 16999.500000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 16999.500000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28248.234269 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28248.234269 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28248.234269 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28248.234269 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1352,28 +1366,28 @@ system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6439 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211003 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74661 40.97% 40.97% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6440 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211015 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74666 40.97% 40.97% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1879 1.03% 42.07% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105563 57.93% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182234 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73294 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::31 105570 57.93% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182246 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73299 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1879 1.26% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73294 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148598 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1817873983000 97.73% 97.73% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 64184500 0.00% 97.73% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 553817500 0.03% 97.76% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 41694992500 2.24% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1860186977500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::31 73299 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148608 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1817910535000 97.73% 97.73% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 64222000 0.00% 97.73% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 554846000 0.03% 97.76% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 41641763000 2.24% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1860171366000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981692 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694315 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815424 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694317 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815425 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -1412,7 +1426,7 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175119 91.23% 93.43% # number of callpals executed +system.cpu.kern.callpal::swpipl 175131 91.23% 93.44% # number of callpals executed system.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed @@ -1421,20 +1435,20 @@ system.cpu.kern.callpal::whami 2 0.00% 96.98% # nu system.cpu.kern.callpal::rti 5104 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 191963 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5852 # number of protection mode switches +system.cpu.kern.callpal::total 191975 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5851 # number of protection mode switches system.cpu.kern.mode_switch::user 1740 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2094 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches system.cpu.kern.mode_good::kernel 1910 system.cpu.kern.mode_good::user 1740 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.326384 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.326440 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081184 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::total 0.394384 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29561208000 1.59% 1.59% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2704677000 0.15% 1.73% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1827921084500 98.27% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::kernel 29515260500 1.59% 1.59% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2703792500 0.15% 1.73% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1827952305000 98.27% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal index f09f72d29..075c19401 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal @@ -24,7 +24,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
memcluster 1, usage 0, start 392, end 16384
freeing pages 1069:16384
reserving pages 1069:1070 -
4096K Bcache detected; load hit latency 30 cycles, load miss latency 134 cycles +
4096K Bcache detected; load hit latency 30 cycles, load miss latency 140 cycles
SMP: 1 CPUs probed -- cpu_present_mask = 1
Built 1 zonelists
Kernel command line: root=/dev/hda1 console=ttyS0 diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini index 933f62fba..e60af9d92 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini @@ -15,17 +15,18 @@ boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 cache_line_size=64 clk_domain=system.clk_domain -console=/dist/binaries/console +console=/home/stever/m5/m5_system_2.0b3/binaries/console eventq_index=0 init_param=0 -kernel=/dist/binaries/vmlinux +kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux load_addr_mask=1099511627775 +load_offset=0 mem_mode=atomic mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -pal=/dist/binaries/ts_osfpal -readfile=tests/halt.sh +pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal +readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh symbolfile= system_rev=1024 system_type=34 @@ -58,6 +59,7 @@ voltage_domain=system.voltage_domain [system.cpu0] type=AtomicSimpleCPU children=dcache dtb icache interrupts isa itb tracer +branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 @@ -85,6 +87,7 @@ simpoint_profile_file=simpoint.bb.gz simpoint_start_insts= simulate_data_stalls=false simulate_inst_stalls=false +socket_id=0 switched_out=false system=system tracer=system.cpu0.tracer @@ -189,6 +192,7 @@ eventq_index=0 [system.cpu1] type=TimingSimpleCPU children=dtb isa itb tracer +branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 @@ -210,6 +214,7 @@ numThreads=1 profile=0 progress_interval=0 simpoint_start_insts= +socket_id=0 switched_out=true system=system tracer=system.cpu1.tracer @@ -310,6 +315,7 @@ smtLSQThreshold=100 smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 +socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=true @@ -689,7 +695,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/disks/linux-latest.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img read_only=true [system.disk2] @@ -712,7 +718,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/disks/linux-bigswap2.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -833,9 +839,9 @@ warn_access= pio=system.membus.default [system.physmem] -type=SimpleDRAM +type=DRAMCtrl activation_limit=4 -addr_mapping=RaBaChCo +addr_mapping=RoRaBaChCo banks_per_rank=8 burst_length=8 channels=1 @@ -846,27 +852,33 @@ device_rowbuffer_size=1024 devices_per_rank=8 eventq_index=0 in_addr_map=true +max_accesses_per_row=16 mem_sched_policy=frfcfs +min_writes_per_switch=16 null=false -page_policy=open +page_policy=open_adaptive range=0:134217727 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 +tCK=1250 tCL=13750 tRAS=35000 tRCD=13750 tREFI=7800000 -tRFC=300000 +tRFC=260000 tRP=13750 -tRRD=6250 +tRRD=6000 +tRTP=7500 +tRTW=2500 +tWR=15000 tWTR=7500 -tXAW=40000 -write_buffer_size=32 -write_high_thresh_perc=70 -write_low_thresh_perc=0 +tXAW=30000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 port=system.membus.master[1] [system.simple_disk] @@ -879,7 +891,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage eventq_index=0 -image_file=/dist/disks/linux-latest.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout index ecd39bc4a..f92b070f8 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full/simout +Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 16:27:55 -gem5 started Jan 22 2014 19:37:21 -gem5 executing on u200540-lin -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full +gem5 compiled Jun 21 2014 10:36:29 +gem5 started Jun 21 2014 13:11:51 +gem5 executing on phenom +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full Global frequency set at 1000000000000 ticks per second 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt index d0b0c157e..de36b122c 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt @@ -1,147 +1,147 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.843672 # Number of seconds simulated -sim_ticks 1843672389000 # Number of ticks simulated -final_tick 1843672389000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.842688 # Number of seconds simulated +sim_ticks 1842688380000 # Number of ticks simulated +final_tick 1842688380000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 195444 # Simulator instruction rate (inst/s) -host_op_rate 195444 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4916161077 # Simulator tick rate (ticks/s) -host_mem_usage 347768 # Number of bytes of host memory used -host_seconds 375.02 # Real time elapsed on the host -sim_insts 73296119 # Number of instructions simulated -sim_ops 73296119 # Number of ops (including micro ops) simulated +host_inst_rate 219315 # Simulator instruction rate (inst/s) +host_op_rate 219315 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5608158508 # Simulator tick rate (ticks/s) +host_mem_usage 303992 # Number of bytes of host memory used +host_seconds 328.57 # Real time elapsed on the host +sim_insts 72060922 # Number of instructions simulated +sim_ops 72060922 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 488384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 20120896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 480512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 20113024 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 147840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2228608 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 281856 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2520448 # Number of bytes read from this memory -system.physmem.bytes_read::total 28440384 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 488384 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 147840 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 281856 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 918080 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7465920 # Number of bytes written to this memory -system.physmem.bytes_written::total 7465920 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 7631 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 314389 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu1.inst 147456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2236096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 291264 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2520128 # Number of bytes read from this memory +system.physmem.bytes_read::total 28440832 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 480512 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 147456 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 291264 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 919232 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7466176 # Number of bytes written to this memory +system.physmem.bytes_written::total 7466176 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 7508 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 314266 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2310 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 34822 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 4404 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 39382 # Number of read requests responded to by this memory -system.physmem.num_reads::total 444381 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 116655 # Number of write requests responded to by this memory -system.physmem.num_writes::total 116655 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 264897 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 10913488 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1438624 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 80188 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1208787 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 152877 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 1367080 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15425942 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 264897 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 80188 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 152877 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 497963 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4049483 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4049483 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4049483 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 264897 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 10913488 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1438624 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 80188 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1208787 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 152877 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1367080 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19475425 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 98065 # Number of read requests accepted -system.physmem.writeReqs 44647 # Number of write requests accepted -system.physmem.readBursts 98065 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 44647 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 6274880 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 1280 # Total number of bytes read from write queue -system.physmem.bytesWritten 2856000 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 6276160 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 2857408 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 20 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::cpu1.inst 2304 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 34939 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 4551 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 39377 # Number of read requests responded to by this memory +system.physmem.num_reads::total 444388 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 116659 # Number of write requests responded to by this memory +system.physmem.num_writes::total 116659 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 260767 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 10915044 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1439393 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 80022 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1213497 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 158065 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 1367637 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15434423 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 260767 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 80022 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 158065 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 498854 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4051784 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4051784 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4051784 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 260767 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 10915044 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1439393 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 80022 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1213497 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 158065 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1367637 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19486207 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 98062 # Number of read requests accepted +system.physmem.writeReqs 44473 # Number of write requests accepted +system.physmem.readBursts 98062 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 44473 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 6274816 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 1152 # Total number of bytes read from write queue +system.physmem.bytesWritten 2845184 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 6275968 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 2846272 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 18 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 43 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 6107 # Per bank write bursts -system.physmem.perBankRdBursts::1 5922 # Per bank write bursts -system.physmem.perBankRdBursts::2 6220 # Per bank write bursts -system.physmem.perBankRdBursts::3 6321 # Per bank write bursts -system.physmem.perBankRdBursts::4 5635 # Per bank write bursts -system.physmem.perBankRdBursts::5 6235 # Per bank write bursts -system.physmem.perBankRdBursts::6 5931 # Per bank write bursts -system.physmem.perBankRdBursts::7 6044 # Per bank write bursts -system.physmem.perBankRdBursts::8 6533 # Per bank write bursts -system.physmem.perBankRdBursts::9 6108 # Per bank write bursts -system.physmem.perBankRdBursts::10 6507 # Per bank write bursts -system.physmem.perBankRdBursts::11 5966 # Per bank write bursts -system.physmem.perBankRdBursts::12 5866 # Per bank write bursts -system.physmem.perBankRdBursts::13 6273 # Per bank write bursts -system.physmem.perBankRdBursts::14 6336 # Per bank write bursts -system.physmem.perBankRdBursts::15 6041 # Per bank write bursts -system.physmem.perBankWrBursts::0 2748 # Per bank write bursts -system.physmem.perBankWrBursts::1 2555 # Per bank write bursts -system.physmem.perBankWrBursts::2 2839 # Per bank write bursts -system.physmem.perBankWrBursts::3 3065 # Per bank write bursts -system.physmem.perBankWrBursts::4 2620 # Per bank write bursts -system.physmem.perBankWrBursts::5 2963 # Per bank write bursts -system.physmem.perBankWrBursts::6 2854 # Per bank write bursts -system.physmem.perBankWrBursts::7 2670 # Per bank write bursts -system.physmem.perBankWrBursts::8 3259 # Per bank write bursts -system.physmem.perBankWrBursts::9 2627 # Per bank write bursts -system.physmem.perBankWrBursts::10 3029 # Per bank write bursts -system.physmem.perBankWrBursts::11 2539 # Per bank write bursts -system.physmem.perBankWrBursts::12 2431 # Per bank write bursts -system.physmem.perBankWrBursts::13 2744 # Per bank write bursts -system.physmem.perBankWrBursts::14 2948 # Per bank write bursts -system.physmem.perBankWrBursts::15 2734 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 40 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 6096 # Per bank write bursts +system.physmem.perBankRdBursts::1 5927 # Per bank write bursts +system.physmem.perBankRdBursts::2 6222 # Per bank write bursts +system.physmem.perBankRdBursts::3 6258 # Per bank write bursts +system.physmem.perBankRdBursts::4 5693 # Per bank write bursts +system.physmem.perBankRdBursts::5 6247 # Per bank write bursts +system.physmem.perBankRdBursts::6 5971 # Per bank write bursts +system.physmem.perBankRdBursts::7 5980 # Per bank write bursts +system.physmem.perBankRdBursts::8 6426 # Per bank write bursts +system.physmem.perBankRdBursts::9 5994 # Per bank write bursts +system.physmem.perBankRdBursts::10 6527 # Per bank write bursts +system.physmem.perBankRdBursts::11 6117 # Per bank write bursts +system.physmem.perBankRdBursts::12 5881 # Per bank write bursts +system.physmem.perBankRdBursts::13 6322 # Per bank write bursts +system.physmem.perBankRdBursts::14 6340 # Per bank write bursts +system.physmem.perBankRdBursts::15 6043 # Per bank write bursts +system.physmem.perBankWrBursts::0 2729 # Per bank write bursts +system.physmem.perBankWrBursts::1 2556 # Per bank write bursts +system.physmem.perBankWrBursts::2 2841 # Per bank write bursts +system.physmem.perBankWrBursts::3 3001 # Per bank write bursts +system.physmem.perBankWrBursts::4 2678 # Per bank write bursts +system.physmem.perBankWrBursts::5 2962 # Per bank write bursts +system.physmem.perBankWrBursts::6 2867 # Per bank write bursts +system.physmem.perBankWrBursts::7 2601 # Per bank write bursts +system.physmem.perBankWrBursts::8 3150 # Per bank write bursts +system.physmem.perBankWrBursts::9 2533 # Per bank write bursts +system.physmem.perBankWrBursts::10 3049 # Per bank write bursts +system.physmem.perBankWrBursts::11 2640 # Per bank write bursts +system.physmem.perBankWrBursts::12 2384 # Per bank write bursts +system.physmem.perBankWrBursts::13 2771 # Per bank write bursts +system.physmem.perBankWrBursts::14 2950 # Per bank write bursts +system.physmem.perBankWrBursts::15 2744 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 2 # Number of times write queue was full causing retry -system.physmem.totGap 1842660063500 # Total gap between requests +system.physmem.numWrRetry 8 # Number of times write queue was full causing retry +system.physmem.totGap 1841676054500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 98065 # Read request sizes (log2) +system.physmem.readPktSize::6 98062 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 44647 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 65397 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 7824 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 8078 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2035 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 831 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1795 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1629 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1651 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1059 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 913 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 873 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 850 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 660 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 661 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 817 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 795 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 896 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 513 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 393 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 373 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 44473 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 65686 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 7740 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 8102 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2064 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 855 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1814 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1613 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1627 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1004 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 871 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 858 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 847 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 653 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 645 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 779 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 766 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 872 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 494 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 391 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 362 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -153,12 +153,12 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 76 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 43 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 42 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 41 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 38 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 36 # What write queue length does an incoming req see @@ -168,368 +168,385 @@ system.physmem.wrQLenPdf::11 35 # Wh system.physmem.wrQLenPdf::12 35 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 35 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 569 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 590 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1447 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 1573 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 1674 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 1688 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 1720 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1786 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1841 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 1914 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 2036 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 2069 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 2187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 2080 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 2119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 2107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 2073 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 340 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 302 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 363 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 393 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 364 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 474 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 505 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 461 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 518 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 667 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 827 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 929 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 857 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 863 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 793 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 814 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 721 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 371 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 4 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 21868 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 417.545272 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 236.447646 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 397.078129 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 6878 31.45% 31.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 4663 21.32% 52.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 1715 7.84% 60.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 976 4.46% 65.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 897 4.10% 69.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 495 2.26% 71.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 365 1.67% 73.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 382 1.75% 74.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5497 25.14% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 21868 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 2618 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 37.446906 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 907.093650 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 2616 99.92% 99.92% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 586 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 612 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1386 # What write queue length does an incoming req see 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length does an incoming req see +system.physmem.wrQLenPdf::31 2144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 2115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 371 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 340 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 362 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 364 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 402 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 384 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 456 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 479 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 463 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 497 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 562 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 666 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 784 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 853 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 771 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 700 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 689 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 741 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 691 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 362 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 16 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 21822 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 417.926863 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 236.963090 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 396.574874 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 6839 31.34% 31.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 4667 21.39% 52.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 1650 7.56% 60.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1022 4.68% 64.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 930 4.26% 69.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 496 2.27% 71.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 383 1.76% 73.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 375 1.72% 74.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 5460 25.02% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 21822 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 2614 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 37.504973 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 907.786867 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 2612 99.92% 99.92% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.04% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::45056-47103 1 0.04% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 2618 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 2618 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.045455 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.392541 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 4.534822 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-1 25 0.95% 0.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::2-3 9 0.34% 1.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-5 2 0.08% 1.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::6-7 3 0.11% 1.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-9 2 0.08% 1.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::10-11 1 0.04% 1.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::14-15 1 0.04% 1.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-17 1908 72.88% 74.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18-19 472 18.03% 92.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-21 41 1.57% 94.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22-23 56 2.14% 96.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-25 26 0.99% 97.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26-27 16 0.61% 97.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-29 10 0.38% 98.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30-31 14 0.53% 98.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-33 7 0.27% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-37 1 0.04% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38-39 1 0.04% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-41 3 0.11% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-45 4 0.15% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-53 1 0.04% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::54-55 1 0.04% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-57 11 0.42% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::58-59 1 0.04% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-61 1 0.04% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-65 1 0.04% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 2618 # Writes before turning the bus around for reads -system.physmem.totQLat 2942753000 # Total ticks spent queuing -system.physmem.totMemAccLat 4781096750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 490225000 # Total ticks spent in databus transfers -system.physmem.avgQLat 30014.31 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 2614 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 2614 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.006886 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.398766 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 4.165807 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::1 24 0.92% 0.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::2 7 0.27% 1.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::3 2 0.08% 1.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4 1 0.04% 1.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::5 1 0.04% 1.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::7 3 0.11% 1.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8 2 0.08% 1.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::10 1 0.04% 1.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::13 1 0.04% 1.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::15 1 0.04% 1.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 1860 71.16% 72.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 26 0.99% 73.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 431 16.49% 90.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 74 2.83% 93.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 23 0.88% 93.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 9 0.34% 94.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 11 0.42% 94.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 40 1.53% 96.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 8 0.31% 96.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 18 0.69% 97.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 8 0.31% 97.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 7 0.27% 97.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 3 0.11% 97.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 5 0.19% 98.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 6 0.23% 98.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 9 0.34% 98.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 5 0.19% 98.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33 1 0.04% 98.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34 1 0.04% 99.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::35 1 0.04% 99.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36 1 0.04% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::37 1 0.04% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::39 4 0.15% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::41 3 0.11% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42 2 0.08% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::43 1 0.04% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::47 1 0.04% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48 4 0.15% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::51 1 0.04% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::53 1 0.04% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56 3 0.11% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::57 2 0.08% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::58 1 0.04% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 2614 # Writes before turning the bus around for reads +system.physmem.totQLat 2880597750 # Total ticks spent queuing +system.physmem.totMemAccLat 4718922750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 490220000 # Total ticks spent in databus transfers +system.physmem.avgQLat 29380.66 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 48764.31 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.40 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.55 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.40 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.55 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 48130.66 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.41 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.54 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.41 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.54 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.17 # Average read queue length when enqueuing -system.physmem.avgWrQLen 4.22 # Average write queue length when enqueuing -system.physmem.readRowHits 85384 # Number of row buffer hits during reads -system.physmem.writeRowHits 35418 # Number of row buffer hits during writes +system.physmem.avgRdQLen 1.11 # Average read queue length when enqueuing +system.physmem.avgWrQLen 4.05 # Average write queue length when enqueuing +system.physmem.readRowHits 85382 # Number of row buffer hits during reads +system.physmem.writeRowHits 35296 # Number of row buffer hits during writes system.physmem.readRowHitRate 87.09 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.33 # Row buffer hit rate for writes -system.physmem.avgGap 12911738.77 # Average gap between requests -system.physmem.pageHitRate 84.66 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 1768578867000 # Time in different power states -system.physmem.memoryStateTime::REF 61564100000 # Time in different power states +system.physmem.writeRowHitRate 79.37 # Row buffer hit rate for writes +system.physmem.avgGap 12920868.94 # Average gap between requests +system.physmem.pageHitRate 84.68 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 1767714784750 # Time in different power states +system.physmem.memoryStateTime::REF 61531340000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 13524513000 # Time in different power states +system.physmem.memoryStateTime::ACT 13440274000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 19519346 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 44419 # Transaction distribution -system.membus.trans_dist::ReadResp 44389 # Transaction distribution -system.membus.trans_dist::WriteReq 3765 # Transaction distribution -system.membus.trans_dist::WriteResp 3765 # Transaction distribution -system.membus.trans_dist::Writeback 44647 # Transaction distribution -system.membus.trans_dist::UpgradeReq 46 # Transaction distribution -system.membus.trans_dist::UpgradeResp 46 # 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snoop data (bytes) -system.membus.reqLayer0.occupancy 12506000 # Layer occupancy (ticks) +system.membus.throughput 19530148 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 44582 # Transaction distribution +system.membus.trans_dist::ReadResp 44547 # Transaction distribution +system.membus.trans_dist::WriteReq 3734 # Transaction distribution +system.membus.trans_dist::WriteResp 3734 # Transaction distribution +system.membus.trans_dist::Writeback 44473 # Transaction distribution +system.membus.trans_dist::UpgradeReq 43 # Transaction distribution +system.membus.trans_dist::UpgradeResp 43 # Transaction distribution +system.membus.trans_dist::ReadExReq 56556 # Transaction distribution +system.membus.trans_dist::ReadExResp 56556 # Transaction distribution +system.membus.trans_dist::BadAddressError 35 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 13238 # Packet count per connected master and slave (bytes) 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60853.407986 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 55063.729279 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63124.038673 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 62541.408724 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 59308.991257 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -640,14 +657,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of 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Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078431 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078431 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -661,14 +678,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 9418062 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 9418062 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 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-system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.404624 # mshr miss rate for ReadReq accesses -system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 0.412784 # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::total 0.412784 # mshr miss rate for WriteReq accesses -system.iocache.demand_mshr_miss_rate::tsunami.ide 0.412750 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.412750 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::tsunami.ide 0.412750 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.412750 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 82529.457143 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 82529.457143 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 247952.801889 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 247952.801889 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 247280.427360 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 247280.427360 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 247280.427360 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 247280.427360 # average overall mshr miss latency +system.iocache.ReadReq_mshr_misses::tsunami.ide 69 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 69 # number of ReadReq MSHR misses +system.iocache.WriteReq_mshr_misses::tsunami.ide 16896 # number of WriteReq MSHR misses +system.iocache.WriteReq_mshr_misses::total 16896 # number of WriteReq MSHR misses +system.iocache.demand_mshr_misses::tsunami.ide 16965 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 16965 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 16965 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 16965 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5714463 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 5714463 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 4167935030 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 4167935030 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 4173649493 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 4173649493 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 4173649493 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 4173649493 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.398844 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.398844 # mshr miss rate for ReadReq accesses +system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 0.406623 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total 0.406623 # mshr miss rate for WriteReq accesses +system.iocache.demand_mshr_miss_rate::tsunami.ide 0.406591 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.406591 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::tsunami.ide 0.406591 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.406591 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 82818.304348 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 82818.304348 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 246681.760772 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 246681.760772 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 246015.295785 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 246015.295785 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 246015.295785 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 246015.295785 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -752,22 +769,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 4916751 # DTB read hits -system.cpu0.dtb.read_misses 6099 # DTB read misses +system.cpu0.dtb.read_hits 4913708 # DTB read hits +system.cpu0.dtb.read_misses 6100 # DTB read misses system.cpu0.dtb.read_acv 126 # DTB read access violations -system.cpu0.dtb.read_accesses 428233 # DTB read accesses -system.cpu0.dtb.write_hits 3511411 # DTB write hits -system.cpu0.dtb.write_misses 670 # DTB write misses +system.cpu0.dtb.read_accesses 428235 # DTB read accesses +system.cpu0.dtb.write_hits 3510172 # DTB write hits +system.cpu0.dtb.write_misses 671 # DTB write misses system.cpu0.dtb.write_acv 84 # DTB write access violations -system.cpu0.dtb.write_accesses 163777 # DTB write accesses -system.cpu0.dtb.data_hits 8428162 # DTB hits -system.cpu0.dtb.data_misses 6769 # DTB misses +system.cpu0.dtb.write_accesses 163990 # DTB write accesses +system.cpu0.dtb.data_hits 8423880 # DTB hits +system.cpu0.dtb.data_misses 6771 # DTB misses system.cpu0.dtb.data_acv 210 # DTB access violations -system.cpu0.dtb.data_accesses 592010 # DTB accesses -system.cpu0.itb.fetch_hits 2761691 # ITB hits +system.cpu0.dtb.data_accesses 592225 # DTB accesses +system.cpu0.itb.fetch_hits 2758823 # ITB hits system.cpu0.itb.fetch_misses 3034 # ITB misses system.cpu0.itb.fetch_acv 104 # ITB acv -system.cpu0.itb.fetch_accesses 2764725 # ITB accesses +system.cpu0.itb.fetch_accesses 2761857 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -780,87 +797,87 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 928579533 # number of cpu cycles simulated +system.cpu0.numCycles 928196841 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 33817210 # Number of instructions committed -system.cpu0.committedOps 33817210 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 31677975 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 169596 # Number of float alu accesses -system.cpu0.num_func_calls 812570 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4683135 # number of instructions that are conditional controls -system.cpu0.num_int_insts 31677975 # number of integer instructions -system.cpu0.num_fp_insts 169596 # number of float instructions -system.cpu0.num_int_register_reads 44495639 # number of times the integer registers were read -system.cpu0.num_int_register_writes 23114141 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 87595 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 89102 # number of times the floating registers were written -system.cpu0.num_mem_refs 8458293 # number of memory refs -system.cpu0.num_load_insts 4938120 # Number of load instructions -system.cpu0.num_store_insts 3520173 # Number of store instructions -system.cpu0.num_idle_cycles 904460149.841647 # Number of idle cycles -system.cpu0.num_busy_cycles 24119383.158353 # Number of busy cycles -system.cpu0.not_idle_fraction 0.025974 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.974026 # Percentage of idle cycles -system.cpu0.Branches 5759211 # Number of branches fetched -system.cpu0.op_class::No_OpClass 1618304 4.78% 4.78% # Class of executed instruction -system.cpu0.op_class::IntAlu 23033604 68.10% 72.88% # Class of executed instruction -system.cpu0.op_class::IntMult 32432 0.10% 72.98% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 72.98% # Class of executed instruction -system.cpu0.op_class::FloatAdd 12174 0.04% 73.01% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 73.01% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 73.01% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 73.01% # Class of executed instruction -system.cpu0.op_class::FloatDiv 1606 0.00% 73.02% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 73.02% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 73.02% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 73.02% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 73.02% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 73.02% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 73.02% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 73.02% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 73.02% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 73.02% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 73.02% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 73.02% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 73.02% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 73.02% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 73.02% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 73.02% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 73.02% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 73.02% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 73.02% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 73.02% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 73.02% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 73.02% # Class of executed instruction -system.cpu0.op_class::MemRead 5072252 15.00% 88.02% # Class of executed instruction -system.cpu0.op_class::MemWrite 3523323 10.42% 98.43% # Class of executed instruction -system.cpu0.op_class::IprAccess 530494 1.57% 100.00% # Class of executed instruction +system.cpu0.committedInsts 33463552 # Number of instructions committed +system.cpu0.committedOps 33463552 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 31328637 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 169756 # Number of float alu accesses +system.cpu0.num_func_calls 812549 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4574772 # number of instructions that are conditional controls +system.cpu0.num_int_insts 31328637 # number of integer instructions +system.cpu0.num_fp_insts 169756 # number of float instructions +system.cpu0.num_int_register_reads 43916482 # number of times the integer registers were read +system.cpu0.num_int_register_writes 22873823 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 87693 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 89172 # number of times the floating registers were written +system.cpu0.num_mem_refs 8454037 # number of memory refs +system.cpu0.num_load_insts 4935095 # Number of load instructions +system.cpu0.num_store_insts 3518942 # Number of store instructions +system.cpu0.num_idle_cycles 904607153.884767 # Number of idle cycles +system.cpu0.num_busy_cycles 23589687.115233 # Number of busy cycles +system.cpu0.not_idle_fraction 0.025415 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.974585 # Percentage of idle cycles +system.cpu0.Branches 5650356 # Number of branches fetched +system.cpu0.op_class::No_OpClass 1614853 4.82% 4.82% # Class of executed instruction +system.cpu0.op_class::IntAlu 22689020 67.79% 72.61% # Class of executed instruction +system.cpu0.op_class::IntMult 32419 0.10% 72.71% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 72.71% # Class of executed instruction +system.cpu0.op_class::FloatAdd 12179 0.04% 72.75% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 72.75% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 72.75% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 72.75% # Class of executed instruction +system.cpu0.op_class::FloatDiv 1606 0.00% 72.75% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 72.75% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 72.75% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 72.75% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 72.75% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 72.75% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 72.75% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 72.75% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 72.75% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 72.75% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 72.75% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 72.75% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 72.75% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 72.75% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 72.75% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 72.75% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 72.75% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 72.75% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 72.75% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 72.75% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 72.75% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 72.75% # Class of executed instruction +system.cpu0.op_class::MemRead 5069147 15.15% 87.90% # Class of executed instruction +system.cpu0.op_class::MemWrite 3522084 10.52% 98.42% # Class of executed instruction +system.cpu0.op_class::IprAccess 529225 1.58% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 33824189 # Class of executed instruction +system.cpu0.op_class::total 33470533 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6417 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 211389 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 74803 40.97% 40.97% # number of times we switched to this ipl +system.cpu0.kern.inst.quiesce 6420 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 211388 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 74806 40.97% 40.97% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1880 1.03% 42.11% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 105703 57.89% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 182589 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 73436 49.30% 49.30% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count::22 1879 1.03% 42.11% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 105697 57.89% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 182585 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 73439 49.30% 49.30% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1880 1.26% 50.70% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 73436 49.30% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 148955 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1820445327500 98.74% 98.74% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 38826000 0.00% 98.74% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 365496000 0.02% 98.76% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 22821970000 1.24% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1843671619500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.981725 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good::22 1879 1.26% 50.70% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 73439 49.30% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 148960 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1819515986000 98.74% 98.74% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 38828500 0.00% 98.74% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 364353500 0.02% 98.76% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 22768442500 1.24% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1842687610500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.981726 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.694739 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.815794 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.694807 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.815839 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -896,33 +913,33 @@ system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu0.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed +system.cpu0.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu0.kern.callpal::swpipl 175328 91.20% 93.41% # number of callpals executed -system.cpu0.kern.callpal::rdps 6784 3.53% 96.94% # number of callpals executed +system.cpu0.kern.callpal::swpipl 175326 91.20% 93.41% # number of callpals executed +system.cpu0.kern.callpal::rdps 6783 3.53% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::rdusp 9 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::whami 2 0.00% 96.95% # number of callpals executed -system.cpu0.kern.callpal::rti 5177 2.69% 99.64% # number of callpals executed +system.cpu0.kern.callpal::rti 5176 2.69% 99.64% # number of callpals executed system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 192243 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 5923 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1739 # number of protection mode switches -system.cpu0.kern.mode_switch::idle 2094 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1908 -system.cpu0.kern.mode_good::user 1739 -system.cpu0.kern.mode_good::idle 169 -system.cpu0.kern.mode_switch_good::kernel 0.322134 # fraction of useful protection mode switches +system.cpu0.kern.callpal::total 192241 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 5922 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1737 # number of protection mode switches +system.cpu0.kern.mode_switch::idle 2096 # number of protection mode switches +system.cpu0.kern.mode_good::kernel 1907 +system.cpu0.kern.mode_good::user 1737 +system.cpu0.kern.mode_good::idle 170 +system.cpu0.kern.mode_switch_good::kernel 0.322020 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::idle 0.080707 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.391144 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 29786667000 1.62% 1.62% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2578002500 0.14% 1.76% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::idle 1811306945500 98.24% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 4175 # number of times the context was actually changed +system.cpu0.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::total 0.390979 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 29751992000 1.61% 1.61% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2580511000 0.14% 1.75% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::idle 1810355103000 98.25% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.swap_context 4177 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -954,460 +971,460 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.throughput 110441912 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 785832 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 785787 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 3765 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 3765 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 372222 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 16 # Transaction distribution +system.toL2Bus.throughput 110521342 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 787621 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 787571 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 3734 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 3734 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 372342 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 13 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 150766 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 133614 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 30 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 848294 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1370287 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 2218581 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 27145024 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 55347363 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 82492387 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 203607824 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 10880 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 2138460500 # Layer occupancy (ticks) +system.toL2Bus.trans_dist::UpgradeResp 14 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 150591 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 133695 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 35 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 851659 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1370714 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 2222373 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 27252672 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 55368420 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 82621092 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 203645448 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 10944 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 2139903500 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 247500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 243000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1910550337 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1918103434 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 2233740752 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 2234598905 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.iobus.throughput 1468369 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 2983 # Transaction distribution -system.iobus.trans_dist::ReadResp 2983 # Transaction distribution -system.iobus.trans_dist::WriteReq 20917 # Transaction distribution -system.iobus.trans_dist::WriteResp 20917 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 2330 # Packet count per connected master and slave (bytes) +system.iobus.throughput 1469149 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 2954 # Transaction distribution +system.iobus.trans_dist::ReadResp 2954 # Transaction distribution +system.iobus.trans_dist::WriteReq 20630 # Transaction distribution +system.iobus.trans_dist::WriteResp 20630 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 2332 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 136 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 66 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 8382 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 2408 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 13356 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 34444 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 34444 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 47800 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 9320 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 8304 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 2378 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 22 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 13238 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 33930 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 33930 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 47168 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 9328 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 544 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 61 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 4191 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 1568 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 31 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 15715 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 1099184 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 1099184 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 1114899 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 2707192 # Total data (bytes) -system.iobus.reqLayer0.occupancy 2199000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 4152 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 1550 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 17 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 15652 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 1082792 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 1082792 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 1098444 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 2707184 # Total data (bytes) +system.iobus.reqLayer0.occupancy 2201000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer22.occupancy 57000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6246000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6188000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 1819000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 1792000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 20000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 13000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 156921520 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 154562743 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 9591000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 9504000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 17887000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 17636750 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.icache.tags.replacements 950608 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.189792 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 43374256 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 951119 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 45.603396 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 10403794250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 251.164377 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 98.345392 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 161.680023 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.490555 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.192081 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.315781 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998418 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 951958 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.193866 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 42822968 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 952469 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 44.959960 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 10341081250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 254.383910 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 92.394710 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 164.415245 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.496844 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.180458 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.321124 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.998426 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 447 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 45292775 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 45292775 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 33297051 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 7835821 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 2241384 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 43374256 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 33297051 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 7835821 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 2241384 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 43374256 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 33297051 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 7835821 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 2241384 # number of overall hits -system.cpu0.icache.overall_hits::total 43374256 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 527138 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 127089 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 313001 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 967228 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 527138 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 127089 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 313001 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 967228 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 527138 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 127089 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 313001 # number of overall misses -system.cpu0.icache.overall_misses::total 967228 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1805503003 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4394679722 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6200182725 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 1805503003 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 4394679722 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 6200182725 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 1805503003 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 4394679722 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 6200182725 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 33824189 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 7962910 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 2554385 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 44341484 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 33824189 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 7962910 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 2554385 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 44341484 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 33824189 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 7962910 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 2554385 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 44341484 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015585 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015960 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.122535 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.021813 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015585 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015960 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.122535 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.021813 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015585 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015960 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.122535 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.021813 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14206.603270 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14040.465436 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 6410.259758 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14206.603270 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14040.465436 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 6410.259758 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14206.603270 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14040.465436 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 6410.259758 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 2211 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 139 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.906475 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.icache.tags.tag_accesses 44744661 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 44744661 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 32943729 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 7613321 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 2265918 # 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number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 97990 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 253501 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 351491 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 44495 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 88964 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 133459 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 2159 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 5429 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7588 # number of LoadLockedReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 1 # number of StoreCondReq MSHR misses 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-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1543938740 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2600534498 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4144473238 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 24229750 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 66769000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 90998750 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_misses::cpu1.data 142485 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 342465 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 484950 # number of demand (read+write) MSHR misses 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miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 66182251 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 90338251 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 11000 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 11000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3590648240 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 6837055396 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 10427703636 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3590648240 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 6837055396 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10427703636 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 296463000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 311893000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 608356000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 365040500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 428466000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 793506500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 661503500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 740359000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1401862500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.083594 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.085963 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.039385 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.050470 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.047127 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021680 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.100678 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.099820 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.037504 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3586353240 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 6854038231 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10440391471 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3586353240 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 6854038231 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10440391471 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 290678000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 312039500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 602717500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 359850500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 427676500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 787527000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 650528500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 739716000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1390244500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.082864 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.086114 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.039386 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.050732 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.047029 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021694 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.100479 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.098740 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.037343 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000019 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.069519 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.070737 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.032158 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.069519 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.070737 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.032158 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 20648.179535 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16797.792678 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17884.127168 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34917.310989 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 29164.763848 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31071.742023 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11181.241347 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12266.948374 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11957.785808 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.069181 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.070824 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.032167 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.069181 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.070824 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.032167 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 20743.108991 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16776.418010 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17882.267233 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34919.339027 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 29238.787476 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31132.673548 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11188.513201 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12190.504881 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11905.409989 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25049.869122 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20028.049576 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21513.105947 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25049.869122 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20028.049576 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21513.105947 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25170.040636 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20013.835665 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21528.799816 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25170.040636 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20013.835665 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21528.799816 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1422,22 +1439,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1205243 # DTB read hits +system.cpu1.dtb.read_hits 1201953 # DTB read hits system.cpu1.dtb.read_misses 1367 # DTB read misses system.cpu1.dtb.read_acv 34 # DTB read access violations system.cpu1.dtb.read_accesses 142945 # DTB read accesses -system.cpu1.dtb.write_hits 897974 # DTB write hits +system.cpu1.dtb.write_hits 898873 # DTB write hits system.cpu1.dtb.write_misses 185 # DTB write misses system.cpu1.dtb.write_acv 23 # DTB write access violations -system.cpu1.dtb.write_accesses 58533 # DTB write accesses -system.cpu1.dtb.data_hits 2103217 # DTB hits +system.cpu1.dtb.write_accesses 58321 # DTB write accesses +system.cpu1.dtb.data_hits 2100826 # DTB hits system.cpu1.dtb.data_misses 1552 # DTB misses system.cpu1.dtb.data_acv 57 # DTB access violations -system.cpu1.dtb.data_accesses 201478 # DTB accesses -system.cpu1.itb.fetch_hits 859888 # ITB hits +system.cpu1.dtb.data_accesses 201266 # DTB accesses +system.cpu1.itb.fetch_hits 861128 # ITB hits system.cpu1.itb.fetch_misses 693 # ITB misses system.cpu1.itb.fetch_acv 30 # ITB acv -system.cpu1.itb.fetch_accesses 860581 # ITB accesses +system.cpu1.itb.fetch_accesses 861821 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1450,64 +1467,64 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 953622390 # number of cpu cycles simulated +system.cpu1.numCycles 953604102 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7961300 # Number of instructions committed -system.cpu1.committedOps 7961300 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 7416956 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 45099 # Number of float alu accesses -system.cpu1.num_func_calls 213358 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1019863 # number of instructions that are conditional controls -system.cpu1.num_int_insts 7416956 # number of integer instructions -system.cpu1.num_fp_insts 45099 # number of float instructions -system.cpu1.num_int_register_reads 10395465 # number of times the integer registers were read -system.cpu1.num_int_register_writes 5394572 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 24307 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 24707 # number of times the floating registers were written -system.cpu1.num_mem_refs 2110464 # number of memory refs -system.cpu1.num_load_insts 1210140 # Number of load instructions -system.cpu1.num_store_insts 900324 # Number of store instructions -system.cpu1.num_idle_cycles 923192460.103175 # Number of idle cycles -system.cpu1.num_busy_cycles 30429929.896825 # Number of busy cycles -system.cpu1.not_idle_fraction 0.031910 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.968090 # Percentage of idle cycles -system.cpu1.Branches 1300058 # Number of branches fetched -system.cpu1.op_class::No_OpClass 413905 5.20% 5.20% # Class of executed instruction -system.cpu1.op_class::IntAlu 5261386 66.07% 71.27% # Class of executed instruction -system.cpu1.op_class::IntMult 8416 0.11% 71.38% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 71.38% # Class of executed instruction -system.cpu1.op_class::FloatAdd 5003 0.06% 71.44% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 71.44% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 71.44% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 71.44% # Class of executed instruction -system.cpu1.op_class::FloatDiv 810 0.01% 71.45% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::MemRead 1239389 15.56% 87.01% # Class of executed instruction -system.cpu1.op_class::MemWrite 901545 11.32% 98.34% # Class of executed instruction -system.cpu1.op_class::IprAccess 132455 1.66% 100.00% # Class of executed instruction +system.cpu1.committedInsts 7738659 # Number of instructions committed +system.cpu1.committedOps 7738659 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 7195320 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 44971 # Number of float alu accesses +system.cpu1.num_func_calls 212104 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 948894 # number of instructions that are conditional controls +system.cpu1.num_int_insts 7195320 # number of integer instructions +system.cpu1.num_fp_insts 44971 # number of float instructions +system.cpu1.num_int_register_reads 10028277 # number of times the integer registers were read +system.cpu1.num_int_register_writes 5244710 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 24303 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 24579 # number of times the floating registers were written +system.cpu1.num_mem_refs 2108049 # number of memory refs +system.cpu1.num_load_insts 1206835 # Number of load instructions +system.cpu1.num_store_insts 901214 # Number of store instructions +system.cpu1.num_idle_cycles 922268722.786044 # Number of idle cycles +system.cpu1.num_busy_cycles 31335379.213956 # Number of busy cycles +system.cpu1.not_idle_fraction 0.032860 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.967140 # Percentage of idle cycles +system.cpu1.Branches 1227675 # Number of branches fetched +system.cpu1.op_class::No_OpClass 413043 5.34% 5.34% # Class of executed instruction +system.cpu1.op_class::IntAlu 5041451 65.13% 70.47% # Class of executed instruction +system.cpu1.op_class::IntMult 8548 0.11% 70.58% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 70.58% # Class of executed instruction +system.cpu1.op_class::FloatAdd 4999 0.06% 70.64% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 70.64% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 70.64% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 70.64% # Class of executed instruction +system.cpu1.op_class::FloatDiv 810 0.01% 70.65% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 70.65% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 70.65% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 70.65% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 70.65% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 70.65% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 70.65% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 70.65% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 70.65% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 70.65% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 70.65% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 70.65% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 70.65% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 70.65% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 70.65% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 70.65% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 70.65% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 70.65% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 70.65% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 70.65% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 70.65% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 70.65% # Class of executed instruction +system.cpu1.op_class::MemRead 1235944 15.97% 86.62% # Class of executed instruction +system.cpu1.op_class::MemWrite 902434 11.66% 98.28% # Class of executed instruction +system.cpu1.op_class::IprAccess 133039 1.72% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 7962909 # Class of executed instruction +system.cpu1.op_class::total 7740268 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed @@ -1525,35 +1542,35 @@ system.cpu1.kern.mode_ticks::kernel 0 # nu system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu1.kern.swap_context 0 # number of times the context was actually changed -system.cpu2.branchPred.lookups 9178120 # Number of BP lookups -system.cpu2.branchPred.condPredicted 8499449 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 123200 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 7695654 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 6571533 # Number of BTB hits +system.cpu2.branchPred.lookups 8997141 # Number of BP lookups +system.cpu2.branchPred.condPredicted 8310458 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 125233 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 7551874 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 6369180 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 85.392781 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 282084 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 12342 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 84.339066 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 284910 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 13175 # Number of incorrect RAS predictions. system.cpu2.dtb.fetch_hits 0 # ITB hits system.cpu2.dtb.fetch_misses 0 # ITB misses system.cpu2.dtb.fetch_acv 0 # ITB acv system.cpu2.dtb.fetch_accesses 0 # ITB accesses -system.cpu2.dtb.read_hits 3191151 # DTB read hits -system.cpu2.dtb.read_misses 11650 # DTB read misses -system.cpu2.dtb.read_acv 122 # DTB read access violations -system.cpu2.dtb.read_accesses 216295 # DTB read accesses -system.cpu2.dtb.write_hits 2013879 # DTB write hits -system.cpu2.dtb.write_misses 2626 # DTB write misses -system.cpu2.dtb.write_acv 104 # DTB write access violations -system.cpu2.dtb.write_accesses 81955 # DTB write accesses -system.cpu2.dtb.data_hits 5205030 # DTB hits -system.cpu2.dtb.data_misses 14276 # DTB misses +system.cpu2.dtb.read_hits 3232647 # DTB read hits +system.cpu2.dtb.read_misses 11674 # DTB read misses +system.cpu2.dtb.read_acv 117 # DTB read access violations +system.cpu2.dtb.read_accesses 217551 # DTB read accesses +system.cpu2.dtb.write_hits 2020818 # DTB write hits +system.cpu2.dtb.write_misses 2669 # DTB write misses +system.cpu2.dtb.write_acv 109 # DTB write access violations +system.cpu2.dtb.write_accesses 82591 # DTB write accesses +system.cpu2.dtb.data_hits 5253465 # DTB hits +system.cpu2.dtb.data_misses 14343 # DTB misses system.cpu2.dtb.data_acv 226 # DTB access violations -system.cpu2.dtb.data_accesses 298250 # DTB accesses -system.cpu2.itb.fetch_hits 370022 # ITB hits -system.cpu2.itb.fetch_misses 5569 # ITB misses -system.cpu2.itb.fetch_acv 246 # ITB acv -system.cpu2.itb.fetch_accesses 375591 # ITB accesses +system.cpu2.dtb.data_accesses 300142 # DTB accesses +system.cpu2.itb.fetch_hits 371576 # ITB hits +system.cpu2.itb.fetch_misses 5695 # ITB misses +system.cpu2.itb.fetch_acv 235 # ITB acv +system.cpu2.itb.fetch_accesses 377271 # ITB accesses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.read_acv 0 # DTB read access violations @@ -1566,304 +1583,305 @@ system.cpu2.itb.data_hits 0 # DT system.cpu2.itb.data_misses 0 # DTB misses system.cpu2.itb.data_acv 0 # DTB access violations system.cpu2.itb.data_accesses 0 # DTB accesses -system.cpu2.numCycles 31335688 # number of cpu cycles simulated +system.cpu2.numCycles 31002313 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 8331242 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 37157937 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 9178120 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 6853617 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 8899845 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 601293 # Number of cycles fetch has spent squashing -system.cpu2.fetch.BlockedCycles 9656250 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 10264 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 1927 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 62491 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 87858 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 258 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 2554389 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 85437 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 27441825 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.354062 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.292990 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 8393929 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 36824229 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 8997141 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 6654090 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 8723757 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 635832 # Number of cycles fetch has spent squashing +system.cpu2.fetch.BlockedCycles 9323842 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 10747 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 1941 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 64126 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 88179 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 311 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 2581223 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 87099 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 27026118 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.362542 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.315525 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 18541980 67.57% 67.57% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 269924 0.98% 68.55% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 430608 1.57% 70.12% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 5041958 18.37% 88.49% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 762355 2.78% 91.27% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 165901 0.60% 91.88% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 191104 0.70% 92.57% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 428586 1.56% 94.14% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 1609409 5.86% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 18302361 67.72% 67.72% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 270640 1.00% 68.72% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 435105 1.61% 70.33% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 4809867 17.80% 88.13% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 769933 2.85% 90.98% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 167503 0.62% 91.60% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 192346 0.71% 92.31% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 444449 1.64% 93.95% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 1633914 6.05% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 27441825 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.292897 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.185802 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 8480872 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 9736053 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 8290323 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 308881 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 379812 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 165178 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 12521 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 36770346 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 39237 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 379812 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 8839767 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 2783657 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 5759458 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 8162466 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 1270789 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 35635356 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 2433 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 230404 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 445807 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 23881418 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 44614948 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 44558512 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 52675 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 22098169 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 1783249 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 500707 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 58904 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3714662 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 3352351 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 2102718 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 368829 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 261079 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 33144056 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 620028 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 32694445 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 35243 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 2135274 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 1079120 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 437376 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 27441825 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.191409 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.576872 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 27026118 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.290209 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.187790 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 8441173 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 9512814 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 8253964 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 165145 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 407122 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 167309 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 12818 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 36409694 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 40311 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 407122 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 8734574 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 2556870 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 5774789 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 8067686 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 1239186 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 35224318 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 3572 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 388506 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 20310 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 316059 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 23620864 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 44017646 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 43961139 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 52746 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 21667069 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 1953795 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 502665 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 59694 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 2961257 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 3405802 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 2124807 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 397929 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 274147 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 32669106 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 622861 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 32140552 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 36002 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 2321360 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 1217953 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 439629 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 27026118 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.189240 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.607686 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 15111094 55.07% 55.07% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 3067205 11.18% 66.24% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 1556680 5.67% 71.92% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 5872597 21.40% 93.32% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 904620 3.30% 96.61% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 481374 1.75% 98.37% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 286422 1.04% 99.41% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 142457 0.52% 99.93% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 19376 0.07% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 15119064 55.94% 55.94% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 2962463 10.96% 66.90% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 1396485 5.17% 72.07% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 5591038 20.69% 92.76% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 885243 3.28% 96.03% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 550698 2.04% 98.07% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 348435 1.29% 99.36% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 154603 0.57% 99.93% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 18089 0.07% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 27441825 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 27026118 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 33866 13.68% 13.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 13.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 13.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 13.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 13.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 13.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 13.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 13.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 13.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 13.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 13.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 13.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 13.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 13.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 13.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 13.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 13.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 13.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 13.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 13.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 13.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 13.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 13.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 13.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 13.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 13.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 13.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 13.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 112679 45.53% 59.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 100956 40.79% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 38019 14.73% 14.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 14.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 14.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 14.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 14.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 14.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 14.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 14.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 14.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 14.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 14.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 14.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 14.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 14.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 14.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 14.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 14.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 14.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 14.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 14.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 14.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 14.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 14.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 14.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 14.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 14.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 14.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 14.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 117677 45.59% 60.31% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 102444 39.69% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 2440 0.01% 0.01% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 27019317 82.64% 82.65% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 20282 0.06% 82.71% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 82.71% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 8426 0.03% 82.74% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 82.74% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 82.74% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 82.74% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 1220 0.00% 82.74% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 82.74% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 82.74% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 82.74% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 82.74% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 82.74% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 82.74% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 82.74% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 82.74% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 82.74% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 82.74% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 82.74% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 82.74% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 82.74% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 82.74% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 82.74% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 82.74% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 82.74% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 82.74% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 82.74% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 82.74% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 82.74% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 3318398 10.15% 92.89% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 2035966 6.23% 99.12% # Type of FU issued -system.cpu2.iq.FU_type_0::IprAccess 288396 0.88% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 26413495 82.18% 82.19% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 20160 0.06% 82.25% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 82.25% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 8429 0.03% 82.28% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 82.28% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 82.28% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 82.28% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 1220 0.00% 82.28% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 82.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 82.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 82.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 82.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 82.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 82.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 82.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 82.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 82.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 82.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 82.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 82.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 82.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 82.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 82.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 82.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 82.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 82.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 82.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 82.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 82.28% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 3362943 10.46% 92.74% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 2042777 6.36% 99.10% # Type of FU issued +system.cpu2.iq.FU_type_0::IprAccess 289088 0.90% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 32694445 # Type of FU issued -system.cpu2.iq.rate 1.043361 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 247501 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.007570 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 92879210 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 35788610 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 32300559 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 234249 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 114557 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 110717 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 32817438 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 122068 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 187489 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 32140552 # Type of FU issued +system.cpu2.iq.rate 1.036715 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 258140 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.008032 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 91366801 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 35502508 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 31706710 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 234563 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 114868 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 110893 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 32274032 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 122220 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 191624 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 409544 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 984 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 3929 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 155635 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 457264 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1199 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 4154 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 177923 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 4136 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 26287 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 4195 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 54966 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 379812 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 2011431 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 204809 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 35034427 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 220433 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 3352351 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 2102718 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 550753 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 142349 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 2108 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 3929 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 63003 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 127121 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 190124 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 32537756 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 3211080 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 156689 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 407122 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 1875775 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 219548 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 34577439 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 209711 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 3405802 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 2124807 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 553318 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 48768 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 120434 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 4154 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 65270 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 127814 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 193084 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 31975437 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 3252613 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 165115 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 1270343 # number of nop insts executed -system.cpu2.iew.exec_refs 5232018 # number of memory reference insts executed -system.cpu2.iew.exec_branches 7610407 # Number of branches executed -system.cpu2.iew.exec_stores 2020938 # Number of stores executed -system.cpu2.iew.exec_rate 1.038361 # Inst execution rate -system.cpu2.iew.wb_sent 32444193 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 32411276 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 18891849 # num instructions producing a value -system.cpu2.iew.wb_consumers 22089477 # num instructions consuming a value +system.cpu2.iew.exec_nop 1285472 # number of nop insts executed +system.cpu2.iew.exec_refs 5280547 # number of memory reference insts executed +system.cpu2.iew.exec_branches 7393667 # Number of branches executed +system.cpu2.iew.exec_stores 2027934 # Number of stores executed +system.cpu2.iew.exec_rate 1.031389 # Inst execution rate +system.cpu2.iew.wb_sent 31851458 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 31817603 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 18729651 # num instructions producing a value +system.cpu2.iew.wb_consumers 22311181 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.034325 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.855242 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.026298 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.839474 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 2305077 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 182652 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 175963 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 27062013 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.207707 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.849174 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 2502130 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 183232 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 177866 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 26618996 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.203206 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.875540 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 16121128 59.57% 59.57% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 2330838 8.61% 68.18% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1224813 4.53% 72.71% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 5615394 20.75% 93.46% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 503174 1.86% 95.32% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 185895 0.69% 96.01% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 176248 0.65% 96.66% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 179513 0.66% 97.32% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 725010 2.68% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 16042703 60.27% 60.27% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 2256116 8.48% 68.74% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1167560 4.39% 73.13% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 5327635 20.01% 93.14% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 518833 1.95% 95.09% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 187130 0.70% 95.80% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 168998 0.63% 96.43% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 171142 0.64% 97.07% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 778879 2.93% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 27062013 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 32682976 # Number of instructions committed -system.cpu2.commit.committedOps 32682976 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 26618996 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 32028137 # Number of instructions committed +system.cpu2.commit.committedOps 32028137 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 4889890 # Number of memory references committed -system.cpu2.commit.loads 2942807 # Number of loads committed -system.cpu2.commit.membars 63964 # Number of memory barriers committed -system.cpu2.commit.branches 7465437 # Number of branches committed -system.cpu2.commit.fp_insts 109562 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 31237309 # Number of committed integer instructions. -system.cpu2.commit.function_calls 229028 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 1167807 3.57% 3.57% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 26241804 80.29% 83.87% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 19886 0.06% 83.93% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 0 0.00% 83.93% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 8426 0.03% 83.95% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 83.95% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 83.95% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 83.95% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 1220 0.00% 83.96% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 83.96% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 83.96% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 83.96% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 83.96% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 83.96% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 83.96% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 83.96% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 83.96% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 83.96% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 83.96% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 83.96% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 83.96% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 83.96% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 83.96% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 83.96% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 83.96% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 83.96% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 83.96% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 83.96% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 83.96% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 83.96% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 3006771 9.20% 93.16% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 1948666 5.96% 99.12% # Class of committed instruction -system.cpu2.commit.op_class_0::IprAccess 288396 0.88% 100.00% # Class of committed instruction +system.cpu2.commit.refs 4895422 # Number of memory references committed +system.cpu2.commit.loads 2948538 # Number of loads committed +system.cpu2.commit.membars 64184 # Number of memory barriers committed +system.cpu2.commit.branches 7237241 # Number of branches committed +system.cpu2.commit.fp_insts 109664 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 30577389 # Number of committed integer instructions. +system.cpu2.commit.function_calls 229570 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 1171866 3.66% 3.66% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 25576585 79.86% 83.52% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 19753 0.06% 83.58% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 83.58% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 8429 0.03% 83.60% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 83.60% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 83.60% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 83.60% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 1220 0.00% 83.61% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 83.61% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 83.61% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 83.61% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 83.61% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 83.61% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 83.61% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 83.61% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 83.61% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 83.61% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 83.61% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 83.61% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 83.61% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 83.61% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 83.61% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 83.61% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 83.61% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 83.61% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 83.61% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 83.61% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 83.61% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 83.61% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 3012722 9.41% 93.01% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 1948474 6.08% 99.10% # Class of committed instruction +system.cpu2.commit.op_class_0::IprAccess 289088 0.90% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 32682976 # Class of committed instruction -system.cpu2.commit.bw_lim_events 725010 # number cycles where commit BW limit reached +system.cpu2.commit.op_class_0::total 32028137 # Class of committed instruction +system.cpu2.commit.bw_lim_events 778879 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 61251181 # The number of ROB reads -system.cpu2.rob.rob_writes 70355425 # The number of ROB writes -system.cpu2.timesIdled 245354 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 3893863 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 1748379581 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 31517609 # Number of Instructions Simulated -system.cpu2.committedOps 31517609 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 0.994228 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.994228 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.005806 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.005806 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 42812311 # number of integer regfile reads -system.cpu2.int_regfile_writes 22772429 # number of integer regfile writes -system.cpu2.fp_regfile_reads 67678 # number of floating regfile reads -system.cpu2.fp_regfile_writes 67966 # number of floating regfile writes -system.cpu2.misc_regfile_reads 5406368 # number of misc regfile reads -system.cpu2.misc_regfile_writes 257490 # number of misc regfile writes +system.cpu2.rob.rob_reads 60296509 # The number of ROB reads +system.cpu2.rob.rob_writes 69467378 # The number of ROB writes +system.cpu2.timesIdled 246541 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 3976195 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 1746763449 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 30858711 # Number of Instructions Simulated +system.cpu2.committedOps 30858711 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.004654 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.004654 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.995368 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.995368 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 42053824 # number of integer regfile reads +system.cpu2.int_regfile_writes 22390255 # number of integer regfile writes +system.cpu2.fp_regfile_reads 67731 # number of floating regfile reads +system.cpu2.fp_regfile_writes 68085 # number of floating regfile writes +system.cpu2.misc_regfile_reads 5172203 # number of misc regfile reads +system.cpu2.misc_regfile_writes 258202 # number of misc regfile writes system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu2.kern.inst.hwrei 0 # number of hwrei instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini index add5f9d75..be87396c4 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini @@ -12,8 +12,8 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu cpu_clk_domain intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain atags_addr=256 -boot_loader=/dist/binaries/boot.arm -boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +boot_loader=/home/stever/m5/m5_system_2.0b3/binaries/boot.arm +boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain @@ -30,19 +30,19 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 load_offset=0 machine_type=RealView_PBX mem_mode=timing mem_ranges=0:134217727 -memories=system.physmem system.realview.nvmem +memories=system.realview.nvmem system.physmem multi_proc=true num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=tests/halt.sh +readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -85,7 +85,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/disks/linux-arm-ael.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-arm-ael.img read_only=true [system.clk_domain] @@ -172,6 +172,7 @@ smtLSQThreshold=100 smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 +socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false @@ -228,6 +229,7 @@ numThreads=1 profile=0 progress_interval=0 simpoint_start_insts= +socket_id=0 switched_out=false system=system tracer=system.cpu.checker.tracer @@ -980,9 +982,9 @@ warn_access=warn pio=system.membus.default [system.physmem] -type=SimpleDRAM +type=DRAMCtrl activation_limit=4 -addr_mapping=RaBaChCo +addr_mapping=RoRaBaChCo banks_per_rank=8 burst_length=8 channels=1 @@ -993,27 +995,33 @@ device_rowbuffer_size=1024 devices_per_rank=8 eventq_index=0 in_addr_map=true +max_accesses_per_row=16 mem_sched_policy=frfcfs +min_writes_per_switch=16 null=false -page_policy=open +page_policy=open_adaptive range=0:134217727 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 +tCK=1250 tCL=13750 tRAS=35000 tRCD=13750 tREFI=7800000 -tRFC=300000 +tRFC=260000 tRP=13750 -tRRD=6250 +tRRD=6000 +tRTP=7500 +tRTW=2500 +tWR=15000 tWTR=7500 -tXAW=40000 -write_buffer_size=32 -write_high_thresh_perc=70 -write_low_thresh_perc=0 +tXAW=30000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 port=system.membus.master[6] [system.realview] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr index 43698041c..ec581702f 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr @@ -10,20 +10,21 @@ warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr dccimvac' unimplemented warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented -warn: 6176053500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708 -warn: 6184767500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8 -warn: 6220839500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608 -warn: 6236327500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8 -warn: 6779610500: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8 +warn: 6127336500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708 +warn: 6135886500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8 +warn: 6171724500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608 +warn: 6187045500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8 +warn: 6729690500: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8 warn: LCD dual screen mode not supported -warn: 51874115000: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04 -warn: 2476169247000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0 -warn: 2490093200000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 -warn: 2491309014500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2a4, checker: 0 -warn: 2512521404000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 -warn: 2513043156000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 -warn: 2517323856500: Instruction results do not match! (Values may not actually be integers) Inst: 0x4001f92c, checker: 0x4001ef10 -warn: 2518814467000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0 -warn: 2519896624000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0 -warn: 2519897721500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0 -warn: 2520452967000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2fc, checker: 0 +warn: 51815926000: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04 +warn: 2464496392000: Instruction results do not match! (Values may not actually be integers) Inst: 0x2, checker: 0 +warn: 2490035144500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 +warn: 2491240940500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2a4, checker: 0 +warn: 2491596722500: Instruction results do not match! (Values may not actually be integers) Inst: 0x2, checker: 0 +warn: 2505538162500: Instruction results do not match! (Values may not actually be integers) Inst: 0x2, checker: 0 +warn: 2507237495000: Instruction results do not match! (Values may not actually be integers) Inst: 0x2, checker: 0 +warn: 2512436106000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 +warn: 2512950831500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 +warn: 2518637805000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0 +warn: 2519704735000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0 +warn: 2519705958000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout index a26501a59..964505e0a 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout @@ -1,15 +1,15 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2014 12:08:08 -gem5 started Jan 23 2014 18:47:40 -gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker +gem5 compiled Jun 21 2014 11:22:42 +gem5 started Jun 21 2014 21:27:42 +gem5 executing on phenom +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 - 0: system.cpu.checker.isa: ISA system set to: 0x645a800 0x645a800 - 0: system.cpu.isa: ISA system set to: 0x645a800 0x645a800 +info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux.arm.smp.fb.2.6.38.8 + 0: system.cpu.checker.isa: ISA system set to: 0x639d990 0x639d990 + 0: system.cpu.isa: ISA system set to: 0x639d990 0x639d990 info: Using bootloader at address 0x80000000 info: Using kernel entry physical address at 0x8000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2526146947500 because m5_exit instruction encountered +Exiting @ tick 2525888859000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 7fa449dce..76ba3533e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,137 +1,149 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.526192 # Number of seconds simulated -sim_ticks 2526192217500 # Number of ticks simulated -final_tick 2526192217500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.525889 # Number of seconds simulated +sim_ticks 2525888859000 # Number of ticks simulated +final_tick 2525888859000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 45758 # Simulator instruction rate (inst/s) -host_op_rate 58877 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1916680323 # Simulator tick rate (ticks/s) -host_mem_usage 469072 # Number of bytes of host memory used -host_seconds 1318.00 # Real time elapsed on the host -sim_insts 60309034 # Number of instructions simulated -sim_ops 77600502 # Number of ops (including micro ops) simulated +host_inst_rate 55568 # Simulator instruction rate (inst/s) +host_op_rate 71500 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2327295647 # Simulator tick rate (ticks/s) +host_mem_usage 420424 # Number of bytes of host memory used +host_seconds 1085.33 # Real time elapsed on the host +sim_insts 60309513 # Number of instructions simulated +sim_ops 77601128 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 796992 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9095192 # Number of bytes read from this memory -system.physmem.bytes_read::total 129433368 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 796992 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 796992 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3784320 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 3072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 797248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9094168 # Number of bytes read from this memory +system.physmem.bytes_read::total 129432216 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 797248 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 797248 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3785024 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6800392 # Number of bytes written to this memory +system.physmem.bytes_written::total 6801096 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 53 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12453 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142148 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096864 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59130 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 48 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12457 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142132 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096846 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59141 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813148 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47319307 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1343 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 315491 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3600356 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51236548 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 315491 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 315491 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1498033 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1193920 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2691954 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1498033 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47319307 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1343 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 315491 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4794277 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53928501 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15096864 # Number of read requests accepted -system.physmem.writeReqs 813148 # Number of write requests accepted -system.physmem.readBursts 15096864 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 813148 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 961540928 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 4658368 # Total number of bytes read from write queue -system.physmem.bytesWritten 6820736 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 129433368 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6800392 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 72787 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 706544 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4695 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 943480 # Per bank write bursts -system.physmem.perBankRdBursts::1 937980 # Per bank write bursts -system.physmem.perBankRdBursts::2 937559 # Per bank write bursts -system.physmem.perBankRdBursts::3 937528 # Per bank write bursts -system.physmem.perBankRdBursts::4 943087 # Per bank write bursts -system.physmem.perBankRdBursts::5 937982 # Per bank write bursts -system.physmem.perBankRdBursts::6 937070 # Per bank write bursts -system.physmem.perBankRdBursts::7 936990 # Per bank write bursts -system.physmem.perBankRdBursts::8 943982 # Per bank write bursts -system.physmem.perBankRdBursts::9 938303 # Per bank write bursts -system.physmem.perBankRdBursts::10 937119 # Per bank write bursts -system.physmem.perBankRdBursts::11 936407 # Per bank write bursts -system.physmem.perBankRdBursts::12 943924 # Per bank write bursts -system.physmem.perBankRdBursts::13 938214 # Per bank write bursts -system.physmem.perBankRdBursts::14 937241 # Per bank write bursts -system.physmem.perBankRdBursts::15 937211 # Per bank write bursts -system.physmem.perBankWrBursts::0 6601 # Per bank write bursts -system.physmem.perBankWrBursts::1 6388 # Per bank write bursts -system.physmem.perBankWrBursts::2 6528 # Per bank write bursts -system.physmem.perBankWrBursts::3 6554 # Per bank write bursts -system.physmem.perBankWrBursts::4 6464 # Per bank write bursts -system.physmem.perBankWrBursts::5 6726 # Per bank write bursts -system.physmem.perBankWrBursts::6 6713 # Per bank write bursts -system.physmem.perBankWrBursts::7 6652 # Per bank write bursts -system.physmem.perBankWrBursts::8 7031 # Per bank write bursts -system.physmem.perBankWrBursts::9 6803 # Per bank write bursts -system.physmem.perBankWrBursts::10 6461 # Per bank write bursts -system.physmem.perBankWrBursts::11 6104 # Per bank write bursts -system.physmem.perBankWrBursts::12 7064 # Per bank write bursts -system.physmem.perBankWrBursts::13 6684 # Per bank write bursts -system.physmem.perBankWrBursts::14 6965 # Per bank write bursts -system.physmem.perBankWrBursts::15 6836 # Per bank write bursts +system.physmem.num_writes::total 813159 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47324990 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1216 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 25 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 315631 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3600383 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51242245 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 315631 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 315631 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1498492 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1194064 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2692556 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1498492 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47324990 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1216 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 315631 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4794447 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53934801 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15096846 # Number of read requests accepted +system.physmem.writeReqs 813159 # Number of write requests accepted +system.physmem.readBursts 15096846 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 813159 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 961407104 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 4791040 # Total number of bytes read from write queue +system.physmem.bytesWritten 6818432 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 129432216 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6801096 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 74860 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 706594 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4696 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 943526 # Per bank write bursts +system.physmem.perBankRdBursts::1 937990 # Per bank write bursts +system.physmem.perBankRdBursts::2 937469 # Per bank write bursts +system.physmem.perBankRdBursts::3 937431 # Per bank write bursts +system.physmem.perBankRdBursts::4 943079 # Per bank write bursts +system.physmem.perBankRdBursts::5 938170 # Per bank write bursts +system.physmem.perBankRdBursts::6 937203 # Per bank write bursts +system.physmem.perBankRdBursts::7 936910 # Per bank write bursts +system.physmem.perBankRdBursts::8 943866 # Per bank write bursts +system.physmem.perBankRdBursts::9 938107 # Per bank write bursts +system.physmem.perBankRdBursts::10 936563 # Per bank write bursts +system.physmem.perBankRdBursts::11 936045 # Per bank write bursts +system.physmem.perBankRdBursts::12 943886 # Per bank write bursts +system.physmem.perBankRdBursts::13 937531 # Per bank write bursts +system.physmem.perBankRdBursts::14 937186 # Per bank write bursts +system.physmem.perBankRdBursts::15 937024 # Per bank write bursts +system.physmem.perBankWrBursts::0 6617 # Per bank write bursts +system.physmem.perBankWrBursts::1 6376 # Per bank write bursts +system.physmem.perBankWrBursts::2 6529 # Per bank write bursts +system.physmem.perBankWrBursts::3 6558 # Per bank write bursts +system.physmem.perBankWrBursts::4 6459 # Per bank write bursts +system.physmem.perBankWrBursts::5 6705 # Per bank write bursts +system.physmem.perBankWrBursts::6 6711 # Per bank write bursts +system.physmem.perBankWrBursts::7 6649 # Per bank write bursts +system.physmem.perBankWrBursts::8 7036 # Per bank write bursts +system.physmem.perBankWrBursts::9 6794 # Per bank write bursts +system.physmem.perBankWrBursts::10 6454 # Per bank write bursts +system.physmem.perBankWrBursts::11 6111 # Per bank write bursts +system.physmem.perBankWrBursts::12 7073 # Per bank write bursts +system.physmem.perBankWrBursts::13 6679 # Per bank write bursts +system.physmem.perBankWrBursts::14 6963 # Per bank write bursts +system.physmem.perBankWrBursts::15 6824 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2526191083500 # Total gap between requests +system.physmem.totGap 2525887732500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 38 # Read request sizes (log2) system.physmem.readPktSize::3 14942208 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 154618 # Read request sizes (log2) +system.physmem.readPktSize::6 154600 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 754018 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 59130 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1056388 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 996212 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 954030 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1063517 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 957350 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1019929 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2630220 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2535649 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3302007 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 132277 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 114408 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 104766 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 100921 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 19448 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 18562 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 18244 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 130 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59141 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1057329 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 995712 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 953847 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1057444 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 956989 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1015779 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2635918 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2545995 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3318157 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 125455 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 108163 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 99319 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 95398 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 19431 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 18601 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 18316 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 110 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -159,28 +171,28 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2638 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2876 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4413 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6437 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2592 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4314 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6296 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6465 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 6394 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6386 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6781 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6447 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6429 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6438 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6345 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6465 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6388 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6736 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6476 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6428 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6463 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6391 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6379 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6746 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6351 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see @@ -208,50 +220,49 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 995555 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 972.685250 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 907.127186 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 202.423056 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22972 2.31% 2.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 19885 2.00% 4.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8241 0.83% 5.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2302 0.23% 5.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2369 0.24% 5.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1811 0.18% 5.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8514 0.86% 6.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 964 0.10% 6.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 928497 93.26% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 995555 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6226 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2413.115644 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 115125.420570 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-524287 6222 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 995372 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 972.727318 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 907.205467 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 202.336600 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22984 2.31% 2.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 19752 1.98% 4.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8337 0.84% 5.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2265 0.23% 5.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2301 0.23% 5.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1840 0.18% 5.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8587 0.86% 6.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 978 0.10% 6.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 928328 93.26% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 995372 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6241 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2406.981894 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 114987.414706 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-524287 6237 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.03% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2.09715e+06-2.62144e+06 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6226 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6226 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.117571 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.060113 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.446555 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3515 56.46% 56.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 41 0.66% 57.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 1615 25.94% 83.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 842 13.52% 96.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 76 1.22% 97.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 41 0.66% 98.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 38 0.61% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 41 0.66% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 16 0.26% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6226 # Writes before turning the bus around for reads -system.physmem.totQLat 389908010000 # Total ticks spent queuing -system.physmem.totMemAccLat 671609453750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 75120385000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25952.21 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6241 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6241 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.070662 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.017388 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.386394 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3585 57.44% 57.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 32 0.51% 57.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 1616 25.89% 83.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 845 13.54% 97.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 54 0.87% 98.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 36 0.58% 98.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 33 0.53% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 31 0.50% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 9 0.14% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6241 # Writes before turning the bus around for reads +system.physmem.totQLat 389024977250 # Total ticks spent queuing +system.physmem.totMemAccLat 670687214750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 75109930000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25897.04 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44702.21 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 380.63 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 44647.04 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 380.62 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.70 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 51.24 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.69 # Average system write bandwidth in MiByte/s @@ -259,75 +270,63 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 2.99 # Data bus utilization in percentage system.physmem.busUtilRead 2.97 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 6.80 # Average read queue length when enqueuing -system.physmem.avgWrQLen 27.01 # Average write queue length when enqueuing -system.physmem.readRowHits 14044000 # Number of row buffer hits during reads -system.physmem.writeRowHits 91096 # Number of row buffer hits during writes +system.physmem.avgRdQLen 6.85 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.12 # Average write queue length when enqueuing +system.physmem.readRowHits 14042089 # Number of row buffer hits during reads +system.physmem.writeRowHits 91063 # Number of row buffer hits during writes system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads system.physmem.writeRowHitRate 85.45 # Row buffer hit rate for writes -system.physmem.avgGap 158779.96 # Average gap between requests +system.physmem.avgGap 158760.96 # Average gap between requests system.physmem.pageHitRate 93.42 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2186359463750 # Time in different power states -system.physmem.memoryStateTime::REF 84354920000 # Time in different power states +system.physmem.memoryStateTime::IDLE 2186215098000 # Time in different power states +system.physmem.memoryStateTime::REF 84344780000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 255472398750 # Time in different power states +system.physmem.memoryStateTime::ACT 255323240750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54877773 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16149486 # Transaction distribution -system.membus.trans_dist::ReadResp 16149486 # Transaction distribution +system.membus.throughput 54884184 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16149487 # Transaction distribution +system.membus.trans_dist::ReadResp 16149487 # Transaction distribution system.membus.trans_dist::WriteReq 763349 # Transaction distribution system.membus.trans_dist::WriteResp 763349 # Transaction distribution -system.membus.trans_dist::Writeback 59130 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4692 # Transaction distribution +system.membus.trans_dist::Writeback 59141 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4693 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4695 # Transaction distribution -system.membus.trans_dist::ReadExReq 131451 # Transaction distribution -system.membus.trans_dist::ReadExResp 131451 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383044 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::UpgradeResp 4696 # Transaction distribution +system.membus.trans_dist::ReadExReq 131431 # Transaction distribution +system.membus.trans_dist::ReadExResp 131431 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383042 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3760 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885868 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272676 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885845 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272651 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29884416 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 29884416 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34157092 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390454 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 34157067 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390450 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7520 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16696096 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19094138 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16695648 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19093686 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119537664 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 119537664 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 138631802 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 138631802 # Total data (bytes) +system.membus.tot_pkt_size::total 138631350 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 138631350 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1486816000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1486861000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3620500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3602500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17362899000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17311099000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4734189076 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4710414902 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 36898450149 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 36916757411 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.5 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -335,13 +334,13 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 48265574 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16125556 # Transaction distribution -system.iobus.trans_dist::ReadResp 16125556 # Transaction distribution +system.iobus.throughput 48271369 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16125555 # Transaction distribution +system.iobus.trans_dist::ReadResp 16125555 # Transaction distribution system.iobus.trans_dist::WriteReq 8174 # Transaction distribution system.iobus.trans_dist::WriteResp 8174 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7936 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7934 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 516 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1024 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -363,12 +362,12 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2383044 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2383042 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 29884416 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 29884416 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 32267460 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 32267458 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15872 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15868 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1032 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2048 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -390,14 +389,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390454 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390450 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 119537664 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 119537664 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 121928118 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 121928118 # Total data (bytes) +system.iobus.tot_pkt_size::total 121928114 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 121928114 # Total data (bytes) system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3973000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 3972000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 516000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -443,20 +442,20 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 14942208000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374870000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374868000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 37675624851 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 37649719589 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 14753661 # Number of BP lookups -system.cpu.branchPred.condPredicted 11836576 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 705670 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9513727 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7668660 # Number of BTB hits +system.cpu.branchPred.lookups 14910337 # Number of BP lookups +system.cpu.branchPred.condPredicted 11976867 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 705848 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9580478 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7742107 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.606265 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1399145 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72578 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 80.811281 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1408303 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 72648 # Number of incorrect RAS predictions. system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -480,9 +479,9 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 14987453 # DTB read hits -system.cpu.checker.dtb.read_misses 7308 # DTB read misses -system.cpu.checker.dtb.write_hits 11227597 # DTB write hits +system.cpu.checker.dtb.read_hits 14987595 # DTB read hits +system.cpu.checker.dtb.read_misses 7306 # DTB read misses +system.cpu.checker.dtb.write_hits 11227720 # DTB write hits system.cpu.checker.dtb.write_misses 2191 # DTB write misses system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -493,12 +492,12 @@ system.cpu.checker.dtb.align_faults 0 # Nu system.cpu.checker.dtb.prefetch_faults 180 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 14994761 # DTB read accesses -system.cpu.checker.dtb.write_accesses 11229788 # DTB write accesses +system.cpu.checker.dtb.read_accesses 14994901 # DTB read accesses +system.cpu.checker.dtb.write_accesses 11229911 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 26215050 # DTB hits -system.cpu.checker.dtb.misses 9499 # DTB misses -system.cpu.checker.dtb.accesses 26224549 # DTB accesses +system.cpu.checker.dtb.hits 26215315 # DTB hits +system.cpu.checker.dtb.misses 9497 # DTB misses +system.cpu.checker.dtb.accesses 26224812 # DTB accesses system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -520,7 +519,7 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.itb.inst_hits 61483008 # ITB inst hits +system.cpu.checker.itb.inst_hits 61483491 # ITB inst hits system.cpu.checker.itb.inst_misses 4473 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -537,11 +536,11 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 61487481 # ITB inst accesses -system.cpu.checker.itb.hits 61483008 # DTB hits +system.cpu.checker.itb.inst_accesses 61487964 # ITB inst accesses +system.cpu.checker.itb.hits 61483491 # DTB hits system.cpu.checker.itb.misses 4473 # DTB misses -system.cpu.checker.itb.accesses 61487481 # DTB accesses -system.cpu.checker.numCycles 77886295 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 61487964 # DTB accesses +system.cpu.checker.numCycles 77886925 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits @@ -567,25 +566,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51183231 # DTB read hits -system.cpu.dtb.read_misses 65223 # DTB read misses -system.cpu.dtb.write_hits 11700953 # DTB write hits -system.cpu.dtb.write_misses 15725 # DTB write misses +system.cpu.dtb.read_hits 51097792 # DTB read hits +system.cpu.dtb.read_misses 64987 # DTB read misses +system.cpu.dtb.write_hits 11709971 # DTB write hits +system.cpu.dtb.write_misses 15921 # DTB write misses system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3479 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2504 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 408 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 3472 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2569 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 428 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1339 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51248454 # DTB read accesses -system.cpu.dtb.write_accesses 11716678 # DTB write accesses +system.cpu.dtb.perms_faults 1363 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51162779 # DTB read accesses +system.cpu.dtb.write_accesses 11725892 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 62884184 # DTB hits -system.cpu.dtb.misses 80948 # DTB misses -system.cpu.dtb.accesses 62965132 # DTB accesses +system.cpu.dtb.hits 62807763 # DTB hits +system.cpu.dtb.misses 80908 # DTB misses +system.cpu.dtb.accesses 62888671 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -607,8 +606,8 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 11525561 # ITB inst hits -system.cpu.itb.inst_misses 11159 # ITB inst misses +system.cpu.itb.inst_hits 11575507 # ITB inst hits +system.cpu.itb.inst_misses 11335 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -617,265 +616,266 @@ system.cpu.itb.flush_tlb 4 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2509 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2514 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2978 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2954 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 11536720 # ITB inst accesses -system.cpu.itb.hits 11525561 # DTB hits -system.cpu.itb.misses 11159 # DTB misses -system.cpu.itb.accesses 11536720 # DTB accesses -system.cpu.numCycles 477128882 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 11586842 # ITB inst accesses +system.cpu.itb.hits 11575507 # DTB hits +system.cpu.itb.misses 11335 # DTB misses +system.cpu.itb.accesses 11586842 # DTB accesses +system.cpu.numCycles 476238509 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 29759197 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 90327124 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14753661 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9067805 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 20158177 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4657193 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 122600 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 98301886 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2694 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 86268 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 2686675 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 550 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11522069 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 710692 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5197 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 154327188 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.729776 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.081128 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 29789702 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 91027179 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14910337 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9150410 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 20302096 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4754274 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 125108 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 93772455 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2699 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 88682 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 2727734 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 553 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11572027 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 712397 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5390 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 150113292 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.756026 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.113644 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 134184573 86.95% 86.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1304702 0.85% 87.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1713961 1.11% 88.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2295969 1.49% 90.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2111581 1.37% 91.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1105061 0.72% 92.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2556088 1.66% 94.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 746376 0.48% 94.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8308877 5.38% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 129826802 86.49% 86.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1312716 0.87% 87.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1720953 1.15% 88.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2304331 1.54% 90.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2116294 1.41% 91.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1112529 0.74% 92.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2605432 1.74% 93.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 752346 0.50% 94.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8361889 5.57% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 154327188 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.030922 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.189314 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 31784305 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 100158613 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18079626 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1265080 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3039564 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1958546 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 172069 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 107310478 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 569843 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3039564 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 33522780 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 38730372 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 55131073 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 17590016 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6313383 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102310347 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 498 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 999968 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4068660 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 821 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 106387059 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 473967662 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 432826370 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10390 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78726997 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27660061 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1170574 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1076856 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12635163 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 19719056 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13304976 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1944651 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2472247 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 95130107 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1987847 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 122918672 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 165693 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 18947879 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 47268855 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 505540 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 154327188 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.796481 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.515149 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 150113292 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.031309 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.191138 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31268958 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 96222513 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18495001 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 992442 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3134378 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1970530 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 172531 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 108153308 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 572201 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3134378 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 32906794 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 14229038 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 56831984 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 17995352 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 25015746 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 103064055 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1610 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 17097046 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 19764397 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 2757051 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 1781 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 107250734 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 477314257 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 435890251 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 10500 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78727504 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 28523229 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1172187 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1078501 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 11007211 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 19896895 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13369840 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2003415 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2457274 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 95806828 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1986007 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 122955094 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 190842 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 19616274 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 49695395 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 503680 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 150113292 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.819082 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.543742 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 109964387 71.25% 71.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 14401004 9.33% 80.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 6880878 4.46% 85.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5675452 3.68% 88.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12310168 7.98% 96.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2806019 1.82% 98.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1694480 1.10% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 466491 0.30% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 128309 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 106692829 71.07% 71.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13471343 8.97% 80.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 6554897 4.37% 84.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5548193 3.70% 88.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12665338 8.44% 96.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2805396 1.87% 98.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1723552 1.15% 99.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 514218 0.34% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 137526 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 154327188 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 150113292 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 61903 0.70% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8364845 94.62% 95.32% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 413343 4.68% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 66740 0.75% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 6 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8421993 94.18% 94.93% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 453824 5.07% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 28518 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 57967032 47.16% 47.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93290 0.08% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 13 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 14 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52507324 42.72% 89.98% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12320347 10.02% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58064867 47.22% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93414 0.08% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 15 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 16 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52433900 42.64% 89.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12332230 10.03% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 122918672 # Type of FU issued -system.cpu.iq.rate 0.257622 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8840095 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071918 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 409227562 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 116082546 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85482417 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23345 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12482 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10295 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 131717793 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12456 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 625155 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 122955094 # Type of FU issued +system.cpu.iq.rate 0.258180 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8942563 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.072730 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 405214220 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 117427083 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85619955 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23208 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12528 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10296 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 131856805 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12334 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 652625 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4064409 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6818 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30381 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1573005 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4242114 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 5511 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 31676 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1637740 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107982 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 680619 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 33981236 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 675243 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3039564 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 30259815 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 434333 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 97340803 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 205354 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 19719056 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13304976 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1415400 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 113322 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3328 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30381 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 350453 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 269952 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 620405 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 120843569 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 51870507 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2075103 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3134378 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 11621778 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1344860 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 98019144 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 177250 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 19896895 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13369840 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1412264 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 282212 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 925122 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 31676 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 351157 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 270951 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 622108 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 120868290 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 51786364 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2086804 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 222849 # number of nop insts executed -system.cpu.iew.exec_refs 64083354 # number of memory reference insts executed -system.cpu.iew.exec_branches 11822089 # Number of branches executed -system.cpu.iew.exec_stores 12212847 # Number of stores executed -system.cpu.iew.exec_rate 0.253272 # Inst execution rate -system.cpu.iew.wb_sent 119902421 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85492712 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47017508 # num instructions producing a value -system.cpu.iew.wb_consumers 87566112 # num instructions consuming a value +system.cpu.iew.exec_nop 226309 # number of nop insts executed +system.cpu.iew.exec_refs 64008543 # number of memory reference insts executed +system.cpu.iew.exec_branches 11843747 # Number of branches executed +system.cpu.iew.exec_stores 12222179 # Number of stores executed +system.cpu.iew.exec_rate 0.253798 # Inst execution rate +system.cpu.iew.wb_sent 119919333 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85630251 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47892202 # num instructions producing a value +system.cpu.iew.wb_consumers 88557277 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.179182 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.536937 # average fanout of values written-back +system.cpu.iew.wb_rate 0.179805 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.540805 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 18682974 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1482307 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 536093 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 151287624 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.513928 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.489816 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 19373634 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1482327 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 535963 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 146978914 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.528998 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.513466 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 122817908 81.18% 81.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 14643914 9.68% 90.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3918754 2.59% 93.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2134639 1.41% 94.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1621396 1.07% 95.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 973729 0.64% 96.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1595383 1.05% 97.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 716191 0.47% 98.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2865710 1.89% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 118714103 80.77% 80.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 14514329 9.88% 90.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3718532 2.53% 93.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2215097 1.51% 94.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1629859 1.11% 95.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1057435 0.72% 96.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1495738 1.02% 97.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 696782 0.47% 98.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2937039 2.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 151287624 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60459415 # Number of instructions committed -system.cpu.commit.committedOps 77750883 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 146978914 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60459894 # Number of instructions committed +system.cpu.commit.committedOps 77751509 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27386618 # Number of memory references committed -system.cpu.commit.loads 15654647 # Number of loads committed -system.cpu.commit.membars 403571 # Number of memory barriers committed -system.cpu.commit.branches 10306311 # Number of branches committed +system.cpu.commit.refs 27386881 # Number of memory references committed +system.cpu.commit.loads 15654781 # Number of loads committed +system.cpu.commit.membars 403574 # Number of memory barriers committed +system.cpu.commit.branches 10306383 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 69190973 # Number of committed integer instructions. -system.cpu.commit.function_calls 991245 # Number of function calls committed. +system.cpu.commit.int_insts 69191543 # Number of committed integer instructions. +system.cpu.commit.function_calls 991261 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 50274217 64.66% 64.66% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 50274580 64.66% 64.66% # Class of committed instruction system.cpu.commit.op_class_0::IntMult 87935 0.11% 64.77% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 64.77% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 64.77% # Class of committed instruction @@ -904,319 +904,319 @@ system.cpu.commit.op_class_0::SimdFloatMisc 2113 0.00% 64.78% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 64.78% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.78% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.78% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 15654647 20.13% 84.91% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 11731971 15.09% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 15654781 20.13% 84.91% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 11732100 15.09% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 77750883 # Class of committed instruction -system.cpu.commit.bw_lim_events 2865710 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 77751509 # Class of committed instruction +system.cpu.commit.bw_lim_events 2937039 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 243007370 # The number of ROB reads -system.cpu.rob.rob_writes 195993770 # The number of ROB writes -system.cpu.timesIdled 1776375 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 322801694 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4575172520 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60309034 # Number of Instructions Simulated -system.cpu.committedOps 77600502 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.911400 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.911400 # CPI: Total CPI of All Threads -system.cpu.ipc 0.126400 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.126400 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 548643018 # number of integer regfile reads -system.cpu.int_regfile_writes 87545925 # number of integer regfile writes -system.cpu.fp_regfile_reads 8332 # number of floating regfile reads -system.cpu.fp_regfile_writes 2902 # number of floating regfile writes -system.cpu.misc_regfile_reads 268108891 # number of misc regfile reads -system.cpu.misc_regfile_writes 1173224 # number of misc regfile writes -system.cpu.toL2Bus.throughput 58876928 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2658786 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2658785 # Transaction distribution +system.cpu.rob.rob_reads 239318561 # The number of ROB reads +system.cpu.rob.rob_writes 197472000 # The number of ROB writes +system.cpu.timesIdled 1764819 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 326125217 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4575456172 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60309513 # Number of Instructions Simulated +system.cpu.committedOps 77601128 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 7.896574 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.896574 # CPI: Total CPI of All Threads +system.cpu.ipc 0.126637 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.126637 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 548833946 # number of integer regfile reads +system.cpu.int_regfile_writes 87707846 # number of integer regfile writes +system.cpu.fp_regfile_reads 8328 # number of floating regfile reads +system.cpu.fp_regfile_writes 2914 # number of floating regfile writes +system.cpu.misc_regfile_reads 264312368 # number of misc regfile reads +system.cpu.misc_regfile_writes 1173237 # number of misc regfile writes +system.cpu.toL2Bus.throughput 58892733 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2658790 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2658789 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 763349 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 763349 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 607456 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 607940 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2966 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 12 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2978 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 246178 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 246178 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1963155 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5795994 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30467 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128822 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7918438 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62783488 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85496634 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 41888 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 215832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 148537842 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 148537842 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 196596 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3128822166 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 11 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2977 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 246105 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 246105 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1961974 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5797376 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30926 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128827 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7919103 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62745984 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85556470 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 42736 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 216536 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 148561726 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 148561726 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 194772 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3129487727 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1475557763 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1474700416 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2549946762 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2550487184 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 19999491 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 20248986 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 74967796 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 74797546 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 981488 # number of replacements -system.cpu.icache.tags.tagsinuse 511.574363 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 10460581 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 982000 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 10.652323 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 6957426250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.574363 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999169 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999169 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 980898 # number of replacements +system.cpu.icache.tags.tagsinuse 511.584882 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 10510158 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 981410 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 10.709243 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 6868426250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.584882 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999189 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999189 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 222 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 155 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 214 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 160 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 12503981 # Number of tag accesses -system.cpu.icache.tags.data_accesses 12503981 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 10460581 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 10460581 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 10460581 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 10460581 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 10460581 # number of overall hits -system.cpu.icache.overall_hits::total 10460581 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1061360 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1061360 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1061360 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1061360 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1061360 # number of overall misses -system.cpu.icache.overall_misses::total 1061360 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14265779687 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14265779687 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14265779687 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14265779687 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14265779687 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14265779687 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11521941 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11521941 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11521941 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11521941 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11521941 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11521941 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092116 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.092116 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.092116 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.092116 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.092116 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.092116 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13441.037619 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13441.037619 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13441.037619 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13441.037619 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13441.037619 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13441.037619 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 7028 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 352 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 19.965909 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.tags.tag_accesses 12553342 # Number of tag accesses +system.cpu.icache.tags.data_accesses 12553342 # Number of data accesses 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-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000982 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000191 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012572 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026805 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015971 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.984828 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.984828 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.250000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541161 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541161 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000982 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000191 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012572 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223476 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.092514 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000982 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000191 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012572 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223476 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.092514 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 72339.622642 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 202750 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59907.517029 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62695.679707 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61238.056496 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001.342349 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.342349 # average UpgradeReq mshr miss latency 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+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 734971750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8800481519 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9538875269 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 6435500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166942048250 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166948483750 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 17498078150 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 17498078150 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 6435500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184440126400 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184446561900 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000887 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000094 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012584 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026779 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015969 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.985502 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.985502 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.272727 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.272727 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541236 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541236 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000887 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000094 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012584 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223293 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.092489 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000887 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000094 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012584 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223293 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.092489 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 69812.500000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 71000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59579.422017 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62212.229110 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60819.279287 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.368115 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.368115 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61479.110215 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61479.110215 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 72339.622642 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 202750 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59907.517029 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61569.236181 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61443.560236 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 72339.622642 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 202750 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59907.517029 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61569.236181 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61443.560236 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61088.974707 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61088.974707 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 69812.500000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 71000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59579.422017 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61172.228765 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61049.192436 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 69812.500000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 71000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59579.422017 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61172.228765 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61049.192436 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1337,168 +1337,168 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 643320 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.993245 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 21508532 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 643832 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 33.407056 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 42989250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.993245 # Average occupied blocks per requestor +system.cpu.dcache.tags.replacements 643771 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.993313 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 21491250 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 644283 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 33.356848 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 42393250 # Cycle when the warmup percentage was hit. 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# Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 13756930 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13756930 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7258142 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7258142 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 242767 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 242767 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247595 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 247595 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21015072 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21015072 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21015072 # number of overall hits -system.cpu.dcache.overall_hits::total 21015072 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 735153 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 735153 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2964059 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2964059 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13525 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13525 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 12 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 12 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3699212 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3699212 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3699212 # number of overall misses -system.cpu.dcache.overall_misses::total 3699212 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9975087313 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9975087313 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 139822431498 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 139822431498 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 185099999 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 185099999 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 193503 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 193503 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 149797518811 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 149797518811 # number of demand (read+write) miss cycles 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rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000048 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.149679 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.149679 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.149679 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.149679 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13568.722855 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13568.722855 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47172.620888 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 47172.620888 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13685.767024 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13685.767024 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16125.250000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16125.250000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 40494.440116 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 40494.440116 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 40494.440116 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 40494.440116 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 32269 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 24322 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2609 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 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ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13343.931358 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45954.568802 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 45954.568802 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13660.513599 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13660.513599 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16409.363636 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16409.363636 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 39291.924564 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 39291.924564 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39291.924564 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39291.924564 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 33676 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 25542 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2667 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 316 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.626922 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 80.829114 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 607456 # number of writebacks -system.cpu.dcache.writebacks::total 607456 # number of writebacks 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MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4962813125 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4962813125 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11330760273 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11330760273 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 145614251 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 145614251 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 169497 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 169497 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16293573398 # number of demand (read+write) MSHR miss cycles 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MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026605 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026605 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024364 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024364 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047555 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047555 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000048 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000048 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025678 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025678 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025678 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025678 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12871.767996 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12871.767996 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45495.560256 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45495.560256 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11947.345832 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11947.345832 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14124.750000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14124.750000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25674.939566 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25674.939566 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25674.939566 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 25674.939566 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 607940 # number of writebacks +system.cpu.dcache.writebacks::total 607940 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 376141 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 376141 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2719425 # number of WriteReq MSHR hits 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+system.cpu.dcache.overall_mshr_miss_latency::total 16200504652 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182335641750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182335641750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26891357119 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26891357119 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209226998869 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 209226998869 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026614 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026614 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024359 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024359 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047533 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047533 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000044 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025682 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025682 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12869.699951 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12869.699951 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45107.822722 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45107.822722 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11920.435043 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11920.435043 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14408.818182 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14408.818182 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25510.034661 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25510.034661 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25510.034661 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25510.034661 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1522,16 +1522,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1712402234851 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1712402234851 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1712402234851 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1712402234851 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1711484214589 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1711484214589 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1711484214589 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1711484214589 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83034 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 83038 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini index 518b7284a..50ac2503c 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini @@ -12,8 +12,8 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=256 -boot_loader=/dist/binaries/boot.arm -boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +boot_loader=/home/stever/m5/m5_system_2.0b3/binaries/boot.arm +boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain @@ -30,7 +30,7 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 load_offset=0 machine_type=RealView_PBX @@ -42,7 +42,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=tests/halt.sh +readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -85,7 +85,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/disks/linux-arm-ael.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-arm-ael.img read_only=true [system.clk_domain] @@ -172,6 +172,7 @@ smtLSQThreshold=100 smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 +socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false @@ -775,6 +776,7 @@ smtLSQThreshold=100 smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 +socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false @@ -1423,9 +1425,9 @@ warn_access=warn pio=system.membus.default [system.physmem] -type=SimpleDRAM +type=DRAMCtrl activation_limit=4 -addr_mapping=RaBaChCo +addr_mapping=RoRaBaChCo banks_per_rank=8 burst_length=8 channels=1 @@ -1436,27 +1438,33 @@ device_rowbuffer_size=1024 devices_per_rank=8 eventq_index=0 in_addr_map=true +max_accesses_per_row=16 mem_sched_policy=frfcfs +min_writes_per_switch=16 null=false -page_policy=open +page_policy=open_adaptive range=0:134217727 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 +tCK=1250 tCL=13750 tRAS=35000 tRCD=13750 tREFI=7800000 -tRFC=300000 +tRFC=260000 tRP=13750 -tRRD=6250 +tRRD=6000 +tRTP=7500 +tRTW=2500 +tWR=15000 tWTR=7500 -tXAW=40000 -write_buffer_size=32 -write_high_thresh_perc=70 -write_low_thresh_perc=0 +tXAW=30000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 port=system.membus.master[6] [system.realview] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout index a00c0b470..52743013f 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout @@ -1,15 +1,15 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2014 12:08:08 -gem5 started Jan 23 2014 18:56:34 -gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual +gem5 compiled Jun 21 2014 11:22:42 +gem5 started Jun 21 2014 21:27:42 +gem5 executing on phenom +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 - 0: system.cpu0.isa: ISA system set to: 0x6856800 0x6856800 - 0: system.cpu1.isa: ISA system set to: 0x6856800 0x6856800 +info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux.arm.smp.fb.2.6.38.8 + 0: system.cpu0.isa: ISA system set to: 0x628e100 0x628e100 + 0: system.cpu1.isa: ISA system set to: 0x628e100 0x628e100 info: Using bootloader at address 0x80000000 info: Using kernel entry physical address at 0x8000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2605645191500 because m5_exit instruction encountered +Exiting @ tick 2605245500000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 3626d40ac..fcbba5f01 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,155 +1,155 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.605644 # Number of seconds simulated -sim_ticks 2605643988500 # Number of ticks simulated -final_tick 2605643988500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.605246 # Number of seconds simulated +sim_ticks 2605245500000 # Number of ticks simulated +final_tick 2605245500000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 56388 # Simulator instruction rate (inst/s) -host_op_rate 72604 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2339801960 # Simulator tick rate (ticks/s) -host_mem_usage 475216 # Number of bytes of host memory used -host_seconds 1113.62 # Real time elapsed on the host -sim_insts 62794806 # Number of instructions simulated -sim_ops 80853196 # Number of ops (including micro ops) simulated +host_inst_rate 66179 # Simulator instruction rate (inst/s) +host_op_rate 85203 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2745863070 # Simulator tick rate (ticks/s) +host_mem_usage 426204 # Number of bytes of host memory used +host_seconds 948.79 # Real time elapsed on the host +sim_insts 62790043 # Number of instructions simulated +sim_ops 80839298 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 768 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 394240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4377212 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 1024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 429184 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5246712 # Number of bytes read from this memory -system.physmem.bytes_read::total 131559796 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 394240 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 429184 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 823424 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4275584 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 393536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4351548 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 427968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5241528 # Number of bytes read from this memory +system.physmem.bytes_read::total 131526900 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 393536 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 427968 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 821504 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4250944 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory -system.physmem.bytes_written::total 7304720 # Number of bytes written to this memory +system.physmem.bytes_written::total 7280080 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 12 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6160 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 68468 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 16 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6706 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 82008 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15302188 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66806 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 14 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6149 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 68067 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 13 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6687 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 81927 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15301674 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66421 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory -system.physmem.num_writes::total 824090 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 46480075 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 295 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 151302 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1679896 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 393 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 164713 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 2013595 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50490319 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 151302 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 164713 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 316016 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1640893 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6524 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 1156004 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2803422 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1640893 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 46480075 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 295 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 151302 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1686421 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 393 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 164713 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 3169600 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53293741 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15302188 # Number of read requests accepted -system.physmem.writeReqs 824090 # Number of write requests accepted -system.physmem.readBursts 15302188 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 824090 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 974626176 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 4713856 # Total number of bytes read from write queue -system.physmem.bytesWritten 7328128 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 131559796 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7304720 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 73654 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 709569 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 14159 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 956238 # Per bank write bursts -system.physmem.perBankRdBursts::1 951013 # Per bank write bursts -system.physmem.perBankRdBursts::2 950196 # Per bank write bursts -system.physmem.perBankRdBursts::3 950464 # Per bank write bursts -system.physmem.perBankRdBursts::4 956634 # Per bank write bursts -system.physmem.perBankRdBursts::5 950822 # Per bank write bursts -system.physmem.perBankRdBursts::6 949869 # Per bank write bursts -system.physmem.perBankRdBursts::7 949811 # Per bank write bursts -system.physmem.perBankRdBursts::8 956681 # Per bank write bursts -system.physmem.perBankRdBursts::9 951277 # Per bank write bursts -system.physmem.perBankRdBursts::10 949961 # Per bank write bursts -system.physmem.perBankRdBursts::11 949024 # Per bank write bursts -system.physmem.perBankRdBursts::12 956331 # Per bank write bursts -system.physmem.perBankRdBursts::13 950586 # Per bank write bursts -system.physmem.perBankRdBursts::14 950041 # Per bank write bursts -system.physmem.perBankRdBursts::15 949586 # Per bank write bursts -system.physmem.perBankWrBursts::0 7062 # Per bank write bursts -system.physmem.perBankWrBursts::1 6963 # Per bank write bursts -system.physmem.perBankWrBursts::2 7126 # Per bank write bursts -system.physmem.perBankWrBursts::3 7116 # Per bank write bursts -system.physmem.perBankWrBursts::4 7811 # Per bank write bursts -system.physmem.perBankWrBursts::5 7409 # Per bank write bursts -system.physmem.perBankWrBursts::6 7013 # Per bank write bursts -system.physmem.perBankWrBursts::7 7004 # Per bank write bursts -system.physmem.perBankWrBursts::8 7458 # Per bank write bursts -system.physmem.perBankWrBursts::9 7561 # Per bank write bursts -system.physmem.perBankWrBursts::10 6914 # Per bank write bursts -system.physmem.perBankWrBursts::11 6583 # Per bank write bursts -system.physmem.perBankWrBursts::12 7179 # Per bank write bursts -system.physmem.perBankWrBursts::13 7101 # Per bank write bursts -system.physmem.perBankWrBursts::14 7219 # Per bank write bursts -system.physmem.perBankWrBursts::15 6983 # Per bank write bursts +system.physmem.num_writes::total 823705 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 46487184 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 344 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 25 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 151055 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1670302 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 319 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 164272 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 2011913 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50485415 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 151055 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 164272 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 315327 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1631687 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6525 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 1156181 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2794393 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1631687 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 46487184 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 344 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 151055 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1676828 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 319 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 164272 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 3168095 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53279808 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15301674 # Number of read requests accepted +system.physmem.writeReqs 823705 # Number of write requests accepted +system.physmem.readBursts 15301674 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 823705 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 974584832 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 4722304 # Total number of bytes read from write queue +system.physmem.bytesWritten 7299840 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 131526900 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7280080 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 73786 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 709619 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 14174 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 956301 # Per bank write bursts +system.physmem.perBankRdBursts::1 950868 # Per bank write bursts +system.physmem.perBankRdBursts::2 950386 # Per bank write bursts +system.physmem.perBankRdBursts::3 950557 # Per bank write bursts +system.physmem.perBankRdBursts::4 956616 # Per bank write bursts +system.physmem.perBankRdBursts::5 950990 # Per bank write bursts +system.physmem.perBankRdBursts::6 949776 # Per bank write bursts +system.physmem.perBankRdBursts::7 949548 # Per bank write bursts +system.physmem.perBankRdBursts::8 956645 # Per bank write bursts +system.physmem.perBankRdBursts::9 951285 # Per bank write bursts +system.physmem.perBankRdBursts::10 949982 # Per bank write bursts +system.physmem.perBankRdBursts::11 948991 # Per bank write bursts +system.physmem.perBankRdBursts::12 956228 # Per bank write bursts +system.physmem.perBankRdBursts::13 950424 # Per bank write bursts +system.physmem.perBankRdBursts::14 949846 # Per bank write bursts +system.physmem.perBankRdBursts::15 949445 # Per bank write bursts +system.physmem.perBankWrBursts::0 7049 # Per bank write bursts +system.physmem.perBankWrBursts::1 6917 # Per bank write bursts +system.physmem.perBankWrBursts::2 7321 # Per bank write bursts +system.physmem.perBankWrBursts::3 7203 # Per bank write bursts +system.physmem.perBankWrBursts::4 7749 # Per bank write bursts +system.physmem.perBankWrBursts::5 7300 # Per bank write bursts +system.physmem.perBankWrBursts::6 7008 # Per bank write bursts +system.physmem.perBankWrBursts::7 6995 # Per bank write bursts +system.physmem.perBankWrBursts::8 7363 # Per bank write bursts +system.physmem.perBankWrBursts::9 7456 # Per bank write bursts +system.physmem.perBankWrBursts::10 6910 # Per bank write bursts +system.physmem.perBankWrBursts::11 6580 # Per bank write bursts +system.physmem.perBankWrBursts::12 7092 # Per bank write bursts +system.physmem.perBankWrBursts::13 7012 # Per bank write bursts +system.physmem.perBankWrBursts::14 7131 # Per bank write bursts +system.physmem.perBankWrBursts::15 6974 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2605642823000 # Total gap between requests +system.physmem.totGap 2605244301000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 109 # Read request sizes (log2) system.physmem.readPktSize::3 15138816 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 163263 # Read request sizes (log2) +system.physmem.readPktSize::6 162749 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 757284 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66806 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1074226 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1009957 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 967065 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1078396 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 970167 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1034458 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2664402 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2566961 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3342237 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 136100 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 116220 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 107345 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 103465 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 19833 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 18840 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 18525 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 210 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 112 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66421 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1076672 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1007796 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 966781 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1073648 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 970528 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1031139 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2669789 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2577083 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3357471 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 128637 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 110466 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 102015 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 98116 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 19856 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 18946 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 18627 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 197 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 98 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -176,33 +176,33 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2784 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3035 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4735 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6745 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6865 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6844 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6920 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6907 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6964 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2761 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2986 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4505 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6717 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6884 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6859 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6902 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6949 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6984 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6828 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 6821 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6810 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6824 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6992 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6732 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6837 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6807 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6970 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6705 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see @@ -225,73 +225,70 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1012463 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 969.866853 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 900.909804 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 207.662919 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24967 2.47% 2.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 21104 2.08% 4.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8681 0.86% 5.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2506 0.25% 5.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2720 0.27% 5.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2029 0.20% 6.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8638 0.85% 6.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1014 0.10% 7.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 940804 92.92% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1012463 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6706 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2270.880853 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 84552.226363 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-262143 6700 99.91% 99.91% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::262144-524287 1 0.01% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::524288-786431 1 0.01% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::786432-1.04858e+06 1 0.01% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2.3593e+06-2.62144e+06 1 0.01% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2.88358e+06-3.14573e+06 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::5.24288e+06-5.50502e+06 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6706 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6706 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.074560 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.020748 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.396636 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3829 57.10% 57.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 48 0.72% 57.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 1779 26.53% 84.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 878 13.09% 97.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 53 0.79% 98.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 31 0.46% 98.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 34 0.51% 99.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 40 0.60% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 12 0.18% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6706 # Writes before turning the bus around for reads -system.physmem.totQLat 395588666000 # Total ticks spent queuing -system.physmem.totMemAccLat 681123678500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 76142670000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25976.81 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1012037 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 970.206299 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 901.657757 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 207.022901 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24841 2.45% 2.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 20798 2.06% 4.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8822 0.87% 5.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2548 0.25% 5.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2540 0.25% 5.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1879 0.19% 6.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8798 0.87% 6.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1115 0.11% 7.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 940696 92.95% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1012037 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6684 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2278.257181 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 111148.889106 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-524287 6680 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.03% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2.09715e+06-2.62144e+06 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6684 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6684 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.064632 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.010880 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.396865 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3849 57.59% 57.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 42 0.63% 58.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 1749 26.17% 84.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 863 12.91% 97.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 73 1.09% 98.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 28 0.42% 98.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 31 0.46% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 31 0.46% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 14 0.21% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 3 0.04% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6684 # Writes before turning the bus around for reads +system.physmem.totQLat 394529621500 # Total ticks spent queuing +system.physmem.totMemAccLat 680052521500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 76139440000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25908.36 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44726.81 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 374.04 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.81 # Average achieved write bandwidth in MiByte/s +system.physmem.avgMemAccLat 44658.36 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 374.09 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.80 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 50.49 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.80 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.79 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 2.94 # Data bus utilization in percentage system.physmem.busUtilRead 2.92 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 6.23 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.05 # Average write queue length when enqueuing -system.physmem.readRowHits 14234195 # Number of row buffer hits during reads -system.physmem.writeRowHits 96378 # Number of row buffer hits during writes +system.physmem.avgWrQLen 24.94 # Average write queue length when enqueuing +system.physmem.readRowHits 14233868 # Number of row buffer hits during reads +system.physmem.writeRowHits 96043 # Number of row buffer hits during writes system.physmem.readRowHitRate 93.47 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 84.16 # Row buffer hit rate for writes -system.physmem.avgGap 161577.45 # Average gap between requests +system.physmem.writeRowHitRate 84.18 # Row buffer hit rate for writes +system.physmem.avgGap 161561.74 # Average gap between requests system.physmem.pageHitRate 93.40 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2260536385250 # Time in different power states -system.physmem.memoryStateTime::REF 87007960000 # Time in different power states +system.physmem.memoryStateTime::IDLE 2261037204000 # Time in different power states +system.physmem.memoryStateTime::REF 86994700000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 258093332250 # Time in different power states +system.physmem.memoryStateTime::ACT 257208674750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory @@ -311,299 +308,300 @@ system.realview.nvmem.bw_inst_read::total 172 # I system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 147 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 172 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54224369 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16352672 # Transaction distribution -system.membus.trans_dist::ReadResp 16352672 # Transaction distribution +system.membus.throughput 54210578 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16352619 # Transaction distribution +system.membus.trans_dist::ReadResp 16352619 # Transaction distribution system.membus.trans_dist::WriteReq 769183 # Transaction distribution system.membus.trans_dist::WriteResp 769183 # Transaction distribution -system.membus.trans_dist::Writeback 66806 # Transaction distribution -system.membus.trans_dist::UpgradeReq 35949 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 18292 # Transaction distribution -system.membus.trans_dist::UpgradeResp 14159 # Transaction distribution -system.membus.trans_dist::ReadExReq 138125 # Transaction distribution -system.membus.trans_dist::ReadExResp 137746 # Transaction distribution +system.membus.trans_dist::Writeback 66421 # Transaction distribution +system.membus.trans_dist::UpgradeReq 35773 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 18321 # Transaction distribution +system.membus.trans_dist::UpgradeResp 14174 # Transaction distribution +system.membus.trans_dist::ReadExReq 137666 # Transaction distribution +system.membus.trans_dist::ReadExResp 137285 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384364 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13834 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 2042 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1976897 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4377155 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1975354 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4375612 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34654787 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 34653244 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2392677 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 27668 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 4084 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17753988 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 20178873 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17696452 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 20121337 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 141289401 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 141289401 # Total data (bytes) +system.membus.tot_pkt_size::total 141231865 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 141231865 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1487962500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1487709500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 7000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11808000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11701000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 3000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1796000 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1799000 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17659548997 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17608394498 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4847870095 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4825319244 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 37379122644 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 37398632151 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.4 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 72974 # number of replacements -system.l2c.tags.tagsinuse 53023.948009 # Cycle average of tags in use -system.l2c.tags.total_refs 1873330 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 138152 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.559920 # Average number of references to valid blocks. +system.l2c.tags.replacements 72458 # number of replacements +system.l2c.tags.tagsinuse 53011.924457 # Cycle average of tags in use +system.l2c.tags.total_refs 1875821 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 137631 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.629349 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 37706.296895 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 5.412172 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000364 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4169.126027 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2962.597547 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 11.621110 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4061.748879 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 4107.145016 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.575352 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000083 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 37713.505334 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 5.216539 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000245 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4181.052971 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2965.825646 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 11.076579 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 4028.442908 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 4106.804235 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.575462 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000080 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.063616 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.045206 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000177 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.061977 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.062670 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.809081 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65174 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 289 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3154 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 9081 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 52631 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.994476 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 18850449 # Number of tag accesses -system.l2c.tags.data_accesses 18850449 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 22712 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4441 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 393676 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 165723 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 33196 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 5802 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 607870 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 201576 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1434996 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 583128 # number of Writeback hits -system.l2c.Writeback_hits::total 583128 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1123 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 727 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1850 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 207 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 158 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 365 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 47567 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 59393 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 106960 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 22712 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4441 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 393676 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 213290 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 33196 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 5802 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 607870 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 260969 # number of demand (read+write) hits -system.l2c.demand_hits::total 1541956 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 22712 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4441 # number of overall hits -system.l2c.overall_hits::cpu0.inst 393676 # number of overall hits -system.l2c.overall_hits::cpu0.data 213290 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 33196 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 5802 # number of overall hits -system.l2c.overall_hits::cpu1.inst 607870 # number of overall hits -system.l2c.overall_hits::cpu1.data 260969 # number of overall hits -system.l2c.overall_hits::total 1541956 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 12 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 6041 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6321 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 16 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 6670 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 6363 # number of ReadReq misses -system.l2c.ReadReq_misses::total 25425 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 5691 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 4436 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 10127 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 767 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 589 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1356 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 63545 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 76877 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 140422 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 12 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 6041 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 69866 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 16 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 6670 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 83240 # number of demand (read+write) misses -system.l2c.demand_misses::total 165847 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 12 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 6041 # number of overall misses -system.l2c.overall_misses::cpu0.data 69866 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 16 # number of overall misses -system.l2c.overall_misses::cpu1.inst 6670 # number of overall misses -system.l2c.overall_misses::cpu1.data 83240 # number of overall misses -system.l2c.overall_misses::total 165847 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 1149750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 368000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 435967250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 468270999 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1231000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 485141500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 483349999 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1875478498 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 9144593 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 12320478 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 21465071 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 441981 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 3192363 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 3634344 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 4462150559 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 6003353008 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 10465503567 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 1149750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 368000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 435967250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 4930421558 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 1231000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 485141500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 6486703007 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 12340982065 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 1149750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 368000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 435967250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 4930421558 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 1231000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 485141500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 6486703007 # number of overall miss cycles -system.l2c.overall_miss_latency::total 12340982065 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 22724 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 4443 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 399717 # number of ReadReq accesses(hits+misses) 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uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000593 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000216 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015074 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036406 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000392 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010778 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030423 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.017287 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.850408 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.839932 # mshr miss rate for UpgradeReq accesses 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miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59992.112255 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 56894.860917 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 66211.538462 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60343.354907 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 65137.739949 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 61297.973081 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -794,56 +792,56 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 58718575 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2740966 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2740965 # Transaction distribution +system.toL2Bus.throughput 58770672 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2743232 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2743231 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 769183 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 769183 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 583128 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 35123 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 18657 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 53780 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 259272 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 259272 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 800244 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1073141 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 13760 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 56807 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1229764 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4820581 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 15635 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 75586 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 8085518 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 25589824 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 34686241 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 17772 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 90896 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 39333696 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 48239320 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 23208 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 132848 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 148113805 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 148113805 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 4885896 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4921313376 # Layer occupancy (ticks) +system.toL2Bus.trans_dist::Writeback 583097 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 35011 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 18701 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 53712 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 259154 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 259154 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 799809 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1073837 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 14034 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 57985 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1233533 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4820063 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 15283 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 75701 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 8090245 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 25576064 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 34728353 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 18500 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 94464 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 39453888 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 48201112 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 22492 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 132584 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 148227457 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 148227457 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 4884572 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4922251450 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1803473389 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1802620121 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1514355955 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1515652575 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 9338456 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 9436941 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 34226949 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 34537141 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 2770248418 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.occupancy 2778792830 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 3257977460 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 3257203486 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer8.occupancy 9851958 # Layer occupancy (ticks) +system.toL2Bus.respLayer8.occupancy 9681453 # Layer occupancy (ticks) system.toL2Bus.respLayer8.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer9.occupancy 42643941 # Layer occupancy (ticks) +system.toL2Bus.respLayer9.occupancy 42845398 # Layer occupancy (ticks) system.toL2Bus.respLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 47398342 # Throughput (bytes/s) +system.iobus.throughput 47405592 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 16322915 # Transaction distribution system.iobus.trans_dist::ReadResp 16322915 # Transaction distribution system.iobus.trans_dist::WriteReq 8083 # Transaction distribution @@ -953,17 +951,17 @@ system.iobus.reqLayer25.occupancy 15138816000 # La system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) system.iobus.respLayer0.occupancy 2376281000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 38174483356 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 38152801849 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) -system.cpu0.branchPred.lookups 6117114 # Number of BP lookups -system.cpu0.branchPred.condPredicted 4670626 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 296157 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 3842728 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 2949969 # Number of BTB hits +system.cpu0.branchPred.lookups 6193187 # Number of BP lookups +system.cpu0.branchPred.condPredicted 4738042 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 296192 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 3876930 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 2986045 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 76.767572 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 683314 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 28361 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 77.020864 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 687525 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 28310 # Number of incorrect RAS predictions. system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -987,25 +985,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 8969403 # DTB read hits -system.cpu0.dtb.read_misses 29343 # DTB read misses -system.cpu0.dtb.write_hits 5210557 # DTB write hits -system.cpu0.dtb.write_misses 5731 # DTB write misses +system.cpu0.dtb.read_hits 8977307 # DTB read hits +system.cpu0.dtb.read_misses 29619 # DTB read misses +system.cpu0.dtb.write_hits 5215302 # DTB write hits +system.cpu0.dtb.write_misses 5680 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1733 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1050 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 278 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 1732 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 993 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 285 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 596 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 8998746 # DTB read accesses -system.cpu0.dtb.write_accesses 5216288 # DTB write accesses +system.cpu0.dtb.perms_faults 620 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 9006926 # DTB read accesses +system.cpu0.dtb.write_accesses 5220982 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14179960 # DTB hits -system.cpu0.dtb.misses 35074 # DTB misses -system.cpu0.dtb.accesses 14215034 # DTB accesses +system.cpu0.dtb.hits 14192609 # DTB hits +system.cpu0.dtb.misses 35299 # DTB misses +system.cpu0.dtb.accesses 14227908 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1027,8 +1025,8 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 4277605 # ITB inst hits -system.cpu0.itb.inst_misses 5145 # ITB inst misses +system.cpu0.itb.inst_hits 4299863 # ITB inst hits +system.cpu0.itb.inst_misses 5195 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -1037,583 +1035,580 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1215 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1219 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1426 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1331 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 4282750 # ITB inst accesses -system.cpu0.itb.hits 4277605 # DTB hits -system.cpu0.itb.misses 5145 # DTB misses -system.cpu0.itb.accesses 4282750 # DTB accesses -system.cpu0.numCycles 70248238 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 4305058 # ITB inst accesses +system.cpu0.itb.hits 4299863 # DTB hits +system.cpu0.itb.misses 5195 # DTB misses +system.cpu0.itb.accesses 4305058 # DTB accesses +system.cpu0.numCycles 69478980 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 11931842 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 32451975 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 6117114 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3633283 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 7612739 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1460869 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 60951 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 20309232 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 6063 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 46682 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 1377400 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 299 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 4276074 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 156796 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2089 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 42393450 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.988978 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.370199 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 11944453 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 32774113 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 6193187 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3673570 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 7678957 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1502530 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 63317 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 19508655 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 6049 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 47760 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 1413705 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 248 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 4298413 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 159366 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2185 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 41753011 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.013655 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.394447 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 34788183 82.06% 82.06% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 572054 1.35% 83.41% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 825907 1.95% 85.36% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 686377 1.62% 86.98% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 779180 1.84% 88.81% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 565083 1.33% 90.15% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 677221 1.60% 91.75% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 357838 0.84% 92.59% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3141607 7.41% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 34081524 81.63% 81.63% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 576095 1.38% 83.01% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 828597 1.98% 84.99% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 688423 1.65% 86.64% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 783359 1.88% 88.52% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 570610 1.37% 89.88% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 698382 1.67% 91.56% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 360373 0.86% 92.42% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3165648 7.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 42393450 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.087079 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.461961 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 12487890 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 21493629 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 6874468 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 552722 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 984741 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 950951 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 64626 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 40558878 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 212020 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 984741 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 13064503 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 5883311 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 13498743 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 6804692 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 2157460 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 39446559 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 311 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 442642 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1180293 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 145 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 39856275 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 180582545 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 163877057 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 4135 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 31488132 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 8368142 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 460013 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 416638 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5509006 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7758217 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5771757 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1123661 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1193308 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 37348678 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 906063 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 37718806 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 82800 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6312476 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 13233696 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 257258 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 42393450 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.889732 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.506737 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 41753011 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.089138 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.471713 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 12274082 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 20961054 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 7066192 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 425731 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1025952 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 955706 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 65065 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 40945366 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 213036 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1025952 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 12760478 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 3004976 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 13648632 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 7041602 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 4271371 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 39802599 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 1199 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 1526731 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 1438820 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 1837389 # Number of times rename has blocked due to SQ full +system.cpu0.rename.FullRegisterEvents 522 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 40279465 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 182145305 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 165318292 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 4116 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 31479900 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 8799564 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 460456 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 417031 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 4293085 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7837564 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5796369 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1159621 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1213862 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 37649045 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 906994 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 37770468 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 93887 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6620221 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 14342287 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 258409 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 41753011 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.904617 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.539726 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 27027469 63.75% 63.75% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 5904750 13.93% 77.68% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3167008 7.47% 85.15% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2470651 5.83% 90.98% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2117188 4.99% 95.97% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 941206 2.22% 98.20% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 520081 1.23% 99.42% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 187957 0.44% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 57140 0.13% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 26686839 63.92% 63.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5690671 13.63% 77.55% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3035101 7.27% 84.81% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2408430 5.77% 90.58% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2094356 5.02% 95.60% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 953036 2.28% 97.88% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 611124 1.46% 99.35% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 212675 0.51% 99.85% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 60779 0.15% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 42393450 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 41753011 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 26875 2.51% 2.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 458 0.04% 2.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 836202 77.98% 80.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 208765 19.47% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 29050 2.58% 2.58% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 460 0.04% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 862862 76.64% 79.26% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 233562 20.74% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 14551 0.04% 0.04% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 22694630 60.17% 60.21% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 47979 0.13% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 14 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 10 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 14549 0.04% 0.04% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 22728130 60.17% 60.21% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 48220 0.13% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 11 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 8 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.34% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMisc 680 0.00% 60.34% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 12 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 11 0.00% 60.34% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9430195 25.00% 85.34% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5530734 14.66% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9442602 25.00% 85.34% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5536256 14.66% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 37718806 # Type of FU issued -system.cpu0.iq.rate 0.536936 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1072300 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.028429 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 119012569 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 44575137 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 34852276 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 8350 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 4654 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 3869 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 38772197 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 4358 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 316382 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 37770468 # Type of FU issued +system.cpu0.iq.rate 0.543624 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1125934 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.029810 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 118540397 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 45184408 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 34905571 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 8382 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 4748 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 3872 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 38877516 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 4337 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 330330 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1375838 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2694 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13105 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 538991 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1458060 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2363 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 13414 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 565962 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2149907 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5937 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2141820 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5981 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 984741 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 4273547 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 99764 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 38372810 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 83727 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7758217 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5771757 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 578717 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 40350 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 3282 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13105 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 151036 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 117828 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 268864 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 37337135 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9286340 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 381671 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1025952 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 2385802 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 275075 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 38676599 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 76106 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7837564 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5796369 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 579111 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 58653 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 199282 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 13414 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 149919 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 118426 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 268345 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 37387044 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9294285 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 383424 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 118069 # number of nop insts executed -system.cpu0.iew.exec_refs 14769450 # number of memory reference insts executed -system.cpu0.iew.exec_branches 4962843 # Number of branches executed -system.cpu0.iew.exec_stores 5483110 # Number of stores executed -system.cpu0.iew.exec_rate 0.531503 # Inst execution rate -system.cpu0.iew.wb_sent 37142523 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 34856145 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 18592748 # num instructions producing a value -system.cpu0.iew.wb_consumers 35683758 # num instructions consuming a value +system.cpu0.iew.exec_nop 120560 # number of nop insts executed +system.cpu0.iew.exec_refs 14782259 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4971290 # Number of branches executed +system.cpu0.iew.exec_stores 5487974 # Number of stores executed +system.cpu0.iew.exec_rate 0.538106 # Inst execution rate +system.cpu0.iew.wb_sent 37190474 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 34909443 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 18996365 # num instructions producing a value +system.cpu0.iew.wb_consumers 36943291 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.496185 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.521042 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.502446 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.514203 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6125993 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 648805 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 232656 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 41408709 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.767702 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.726975 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6443412 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 648585 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 232277 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 40727059 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.780301 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.748318 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 29445863 71.11% 71.11% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 5939620 14.34% 85.45% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1940870 4.69% 90.14% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1013361 2.45% 92.59% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 759448 1.83% 94.42% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 515426 1.24% 95.67% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 408347 0.99% 96.65% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 223076 0.54% 97.19% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1162698 2.81% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 28935599 71.05% 71.05% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 5796697 14.23% 85.28% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1842943 4.53% 89.81% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1067095 2.62% 92.43% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 737891 1.81% 94.24% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 511993 1.26% 95.49% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 448684 1.10% 96.60% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 197374 0.48% 97.08% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1188783 2.92% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 41408709 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 24071577 # Number of instructions committed -system.cpu0.commit.committedOps 31789563 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 40727059 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 24067678 # Number of instructions committed +system.cpu0.commit.committedOps 31779383 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 11615145 # Number of memory references committed -system.cpu0.commit.loads 6382379 # Number of loads committed -system.cpu0.commit.membars 231812 # Number of memory barriers committed -system.cpu0.commit.branches 4351457 # Number of branches committed +system.cpu0.commit.refs 11609911 # Number of memory references committed +system.cpu0.commit.loads 6379504 # Number of loads committed +system.cpu0.commit.membars 231786 # Number of memory barriers committed +system.cpu0.commit.branches 4350837 # Number of branches committed system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 28135168 # Number of committed integer instructions. -system.cpu0.commit.function_calls 498959 # Number of function calls committed. +system.cpu0.commit.int_insts 28125415 # Number of committed integer instructions. +system.cpu0.commit.function_calls 498912 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 20133954 63.34% 63.34% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 39784 0.13% 63.46% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 63.46% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 63.46% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 63.46% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 63.46% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 63.46% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 63.46% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 63.46% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 63.46% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 63.46% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 63.46% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 63.46% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 63.46% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 63.46% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 63.46% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 63.46% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 63.46% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 63.46% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 63.46% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 63.46% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 63.46% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 63.46% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 63.46% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 63.46% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 680 0.00% 63.46% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 63.46% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.46% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.46% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 6382379 20.08% 83.54% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 5232766 16.46% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 20129006 63.34% 63.34% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 39786 0.13% 63.47% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 63.47% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 63.47% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 63.47% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 63.47% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 63.47% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 63.47% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 63.47% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 63.47% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 63.47% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 63.47% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 63.47% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 63.47% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 63.47% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 63.47% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 63.47% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 63.47% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 63.47% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 63.47% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 63.47% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 63.47% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 63.47% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 63.47% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 63.47% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 680 0.00% 63.47% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 63.47% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.47% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.47% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 6379504 20.07% 83.54% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 5230407 16.46% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 31789563 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1162698 # number cycles where commit BW limit reached +system.cpu0.commit.op_class_0::total 31779383 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1188783 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 77292791 # The number of ROB reads -system.cpu0.rob.rob_writes 76817595 # The number of ROB writes -system.cpu0.timesIdled 365665 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 27854788 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5140997105 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 23990835 # Number of Instructions Simulated -system.cpu0.committedOps 31708821 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 2.928128 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.928128 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.341515 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.341515 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 174285855 # number of integer regfile reads -system.cpu0.int_regfile_writes 34604955 # number of integer regfile writes -system.cpu0.fp_regfile_reads 3294 # number of floating regfile reads -system.cpu0.fp_regfile_writes 912 # number of floating regfile writes -system.cpu0.misc_regfile_reads 79299010 # number of misc regfile reads -system.cpu0.misc_regfile_writes 500883 # number of misc regfile writes -system.cpu0.icache.tags.replacements 399739 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.543627 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 3844274 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 400251 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 9.604658 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 7097393250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.543627 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999109 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999109 # Average percentage of cache occupancy +system.cpu0.rob.rob_reads 76892389 # The number of ROB reads +system.cpu0.rob.rob_writes 77473478 # The number of ROB writes +system.cpu0.timesIdled 368167 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 27725969 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5140969387 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 23986936 # Number of Instructions Simulated +system.cpu0.committedOps 31698641 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 2.896534 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.896534 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.345240 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.345240 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 174527841 # number of integer regfile reads +system.cpu0.int_regfile_writes 34672219 # number of integer regfile writes +system.cpu0.fp_regfile_reads 3319 # number of floating regfile reads +system.cpu0.fp_regfile_writes 920 # number of floating regfile writes +system.cpu0.misc_regfile_reads 78617689 # number of misc regfile reads +system.cpu0.misc_regfile_writes 500675 # number of misc regfile writes +system.cpu0.icache.tags.replacements 399525 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.581560 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 3866760 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 400037 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 9.666006 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6951542250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.581560 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999183 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999183 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 133 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 207 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 169 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 209 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 168 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 4676219 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 4676219 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 3844274 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 3844274 # number of ReadReq hits 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overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12148.699234 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12148.699234 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12148.699234 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 275002 # number of replacements -system.cpu0.dcache.tags.tagsinuse 479.873805 # Cycle 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LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144959 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 144959 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 11080065 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 11080065 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 11080065 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 11080065 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.062623 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.062623 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.328894 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.328894 # miss rate for WriteReq accesses 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-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50806.576289 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 50806.576289 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10266.921717 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10266.921717 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6434.201756 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6434.201756 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 43495.366623 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 43495.366623 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 43495.366623 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 43495.366623 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 9513 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 7748 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 587 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 136 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 16.206133 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 56.970588 # average number of cycles each access was blocked +system.cpu0.dcache.tags.tag_accesses 45804428 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 45804428 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 5867272 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5867272 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3220606 # number of WriteReq hits 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accesses +system.cpu0.dcache.overall_accesses::cpu0.data 11079785 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 11079785 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.064288 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.064288 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.330352 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.330352 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.060114 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.060114 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053531 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053531 # miss rate for StoreCondReq accesses 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+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6451.374968 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6451.374968 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 40418.305355 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 40418.305355 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 40418.305355 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 40418.305355 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 9294 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 6492 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 635 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 113 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.636220 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 57.451327 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 255347 # number of writebacks -system.cpu0.dcache.writebacks::total 255347 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 203411 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 203411 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1451593 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1451593 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 468 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 468 # number of LoadLockedReq MSHR hits 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MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7747 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 320086 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 320086 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 320086 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 320086 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2397985131 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2397985131 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5338215866 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5338215866 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69513767 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 69513767 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 34349239 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 34349239 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7736200997 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 7736200997 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7736200997 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 7736200997 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13434640527 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13434640527 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1206086382 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1206086382 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14640726909 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14640726909 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030172 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030172 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027216 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027216 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056654 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056654 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053443 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053443 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028888 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.028888 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028888 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.028888 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12679.098028 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12679.098028 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40763.119696 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40763.119696 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8265.608442 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8265.608442 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4433.876210 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4433.876210 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24169.132661 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24169.132661 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24169.132661 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24169.132661 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 255545 # number of writebacks +system.cpu0.dcache.writebacks::total 255545 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 213826 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 213826 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1457949 # number of WriteReq MSHR hits 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+system.cpu0.dcache.overall_mshr_miss_latency::total 7570725619 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13434660545 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13434660545 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1206058380 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1206058380 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14640718925 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14640718925 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030187 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030187 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027207 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027207 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056953 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056953 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053531 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053531 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028893 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.028893 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028893 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.028893 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12767.720399 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12767.720399 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39389.218261 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39389.218261 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8236.364454 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8236.364454 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4450.790539 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4450.790539 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23648.762445 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23648.762445 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23648.762445 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23648.762445 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1621,15 +1616,15 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 9293378 # Number of BP lookups -system.cpu1.branchPred.condPredicted 7631598 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 415998 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 5889507 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 5046361 # Number of BTB hits +system.cpu1.branchPred.lookups 9402679 # Number of BP lookups +system.cpu1.branchPred.condPredicted 7728805 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 418099 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 6037829 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 5108046 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 85.683929 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 797302 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 43622 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 84.600707 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 802186 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 44176 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1653,25 +1648,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 42971422 # DTB read hits -system.cpu1.dtb.read_misses 37905 # DTB read misses -system.cpu1.dtb.write_hits 6976449 # DTB write hits -system.cpu1.dtb.write_misses 10883 # DTB write misses +system.cpu1.dtb.read_hits 42878527 # DTB read hits +system.cpu1.dtb.read_misses 38253 # DTB read misses +system.cpu1.dtb.write_hits 6985734 # DTB write hits +system.cpu1.dtb.write_misses 10793 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1918 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 2893 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 296 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 1922 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 2963 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 279 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 686 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 43009327 # DTB read accesses -system.cpu1.dtb.write_accesses 6987332 # DTB write accesses +system.cpu1.dtb.perms_faults 687 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 42916780 # DTB read accesses +system.cpu1.dtb.write_accesses 6996527 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 49947871 # DTB hits -system.cpu1.dtb.misses 48788 # DTB misses -system.cpu1.dtb.accesses 49996659 # DTB accesses +system.cpu1.dtb.hits 49864261 # DTB hits +system.cpu1.dtb.misses 49046 # DTB misses +system.cpu1.dtb.accesses 49913307 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1693,8 +1688,8 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 7719787 # ITB inst hits -system.cpu1.itb.inst_misses 5634 # ITB inst misses +system.cpu1.itb.inst_hits 7755980 # ITB inst hits +system.cpu1.itb.inst_misses 5491 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1703,574 +1698,579 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1369 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1362 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1538 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1507 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 7725421 # ITB inst accesses -system.cpu1.itb.hits 7719787 # DTB hits -system.cpu1.itb.misses 5634 # DTB misses -system.cpu1.itb.accesses 7725421 # DTB accesses -system.cpu1.numCycles 413693823 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 7761471 # ITB inst accesses +system.cpu1.itb.hits 7755980 # DTB hits +system.cpu1.itb.misses 5491 # DTB misses +system.cpu1.itb.accesses 7761471 # DTB accesses +system.cpu1.numCycles 413132210 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 19372544 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 61318271 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 9293378 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 5843663 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 13362487 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3346253 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 69736 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 80999073 # Number of cycles fetch has spent blocked +system.cpu1.fetch.icacheStallCycles 19420388 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 61788688 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 9402679 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 5910232 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 13466568 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3411318 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 67616 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 77041165 # Number of cycles fetch has spent blocked system.cpu1.fetch.MiscStallCycles 5941 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 42062 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 1494344 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 284 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 7717920 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 551887 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2996 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 117635394 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.638004 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.959630 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.PendingTrapStallCycles 42813 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 1523639 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 257 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 7754163 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 555305 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2851 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 113918823 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.663934 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.994464 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 104280280 88.65% 88.65% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 814710 0.69% 89.34% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 961160 0.82% 90.16% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1713171 1.46% 91.61% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1415249 1.20% 92.82% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 586962 0.50% 93.32% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1954597 1.66% 94.98% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 422243 0.36% 95.34% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 5487022 4.66% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 100459727 88.19% 88.19% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 820479 0.72% 88.91% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 969052 0.85% 89.76% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1718827 1.51% 91.27% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1427854 1.25% 92.52% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 590556 0.52% 93.04% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1988498 1.75% 94.78% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 426289 0.37% 95.16% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 5517541 4.84% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 117635394 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.022464 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.148221 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 20963679 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 81759193 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 11913295 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 809519 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2189708 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1137363 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 100954 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 71089276 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 336011 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 2189708 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 22156707 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 33902507 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 43325786 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 11473545 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 4587141 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 67137864 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 137 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 682095 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 3075433 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 1010 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 70763032 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 313108743 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 286757803 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 6623 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 50416422 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 20346610 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 765987 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 705836 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 8420477 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 12843204 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 8115826 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1055497 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1512633 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 61850161 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1179252 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 88896986 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 93979 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 13548762 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 36246660 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 279849 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 117635394 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.755699 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.498688 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 113918823 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.022759 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.149562 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 20573629 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 78271180 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 12141436 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 681674 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2250904 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1146333 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 101070 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 71648546 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 337709 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 2250904 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 21753755 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 11785871 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 44839476 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 11758144 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 21530673 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 67615561 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 613 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 15671923 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 18336953 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 1545811 # Number of times rename has blocked due to SQ full +system.cpu1.rename.FullRegisterEvents 1295 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 71310682 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 315205355 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 288681323 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 6622 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 50413608 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 20897074 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 766814 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 706637 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 7207016 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 12951593 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 8155935 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1106689 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1533453 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 62295252 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1184366 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 88905891 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 106644 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 13983630 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 37714490 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 285025 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 113918823 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.780432 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.530885 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 86772303 73.76% 73.76% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 9298113 7.90% 81.67% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4175598 3.55% 85.22% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3594840 3.06% 88.27% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 10374006 8.82% 97.09% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1994938 1.70% 98.79% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1065613 0.91% 99.69% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 281099 0.24% 99.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 78884 0.07% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 83813472 73.57% 73.57% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 8528665 7.49% 81.06% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 3988574 3.50% 84.56% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3433815 3.01% 87.58% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 10704573 9.40% 96.97% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1891022 1.66% 98.63% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1169449 1.03% 99.66% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 305487 0.27% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 83766 0.07% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 117635394 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 113918823 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 32152 0.41% 0.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 986 0.01% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 7573471 95.70% 96.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 306947 3.88% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 34951 0.44% 0.44% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 989 0.01% 0.45% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.45% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.45% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.45% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.45% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.45% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.45% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.45% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.45% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.45% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.45% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.45% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.45% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.45% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.45% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.45% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.45% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.45% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.45% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.45% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.45% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.45% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.45% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.45% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.45% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.45% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.45% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.45% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 7593663 95.44% 95.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 326577 4.10% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 14268 0.02% 0.02% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 37614404 42.31% 42.33% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 61197 0.07% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 13 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 10 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1706 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 11 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 43858329 49.34% 91.74% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7347048 8.26% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 14267 0.02% 0.02% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 37698483 42.40% 42.42% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 61348 0.07% 42.49% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.49% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.49% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.49% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.49% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.49% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.49% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.49% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.49% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.49% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.49% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.49% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.49% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 12 0.00% 42.49% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.49% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.49% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.49% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 10 0.00% 42.49% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.49% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.49% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.49% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.49% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.49% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.49% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1706 0.00% 42.49% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.49% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 10 0.00% 42.49% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.49% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 43772925 49.24% 91.72% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7357130 8.28% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 88896986 # Type of FU issued -system.cpu1.iq.rate 0.214886 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 7913556 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.089019 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 303469985 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 76586992 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 54255274 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 15534 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 8108 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6874 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 96788024 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 8250 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 355713 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 88905891 # Type of FU issued +system.cpu1.iq.rate 0.215200 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 7956180 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.089490 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 299826864 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 77472999 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 54370047 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 15424 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 8128 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6867 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 96839621 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 8183 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 371805 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2862172 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 4122 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 17485 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1111950 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2971595 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 3826 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 18443 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1153168 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 31965671 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 675853 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 31846626 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 675699 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2189708 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 26386476 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 363440 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 63133555 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 115239 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 12843204 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 8115826 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 883054 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 66097 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 4286 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 17485 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 204520 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 158639 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 363159 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 87164207 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 43354058 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1732779 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 2250904 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 9489416 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 1235015 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 63585663 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 104803 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 12951593 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 8155935 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 886916 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 232294 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 885959 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 18443 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 206591 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 158855 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 365446 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 87166570 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 43262018 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1739321 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 104142 # number of nop insts executed -system.cpu1.iew.exec_refs 50636612 # number of memory reference insts executed -system.cpu1.iew.exec_branches 7376811 # Number of branches executed -system.cpu1.iew.exec_stores 7282554 # Number of stores executed -system.cpu1.iew.exec_rate 0.210697 # Inst execution rate -system.cpu1.iew.wb_sent 86400335 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 54262148 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 30287291 # num instructions producing a value -system.cpu1.iew.wb_consumers 53873069 # num instructions consuming a value +system.cpu1.iew.exec_nop 106045 # number of nop insts executed +system.cpu1.iew.exec_refs 50553896 # number of memory reference insts executed +system.cpu1.iew.exec_branches 7398817 # Number of branches executed +system.cpu1.iew.exec_stores 7291878 # Number of stores executed +system.cpu1.iew.exec_rate 0.210990 # Inst execution rate +system.cpu1.iew.wb_sent 86399299 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 54376914 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 30829889 # num instructions producing a value +system.cpu1.iew.wb_consumers 55266228 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.131165 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.562197 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.131621 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.557843 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 13443206 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 899403 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 316783 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 115445686 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.426296 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.378874 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 13879712 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 899341 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 318567 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 111667919 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.440684 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.404622 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 97421932 84.39% 84.39% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 9594899 8.31% 92.70% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2172227 1.88% 94.58% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1301741 1.13% 95.71% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 988993 0.86% 96.56% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 587152 0.51% 97.07% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 1008803 0.87% 97.95% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 534624 0.46% 98.41% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1835315 1.59% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 93786179 83.99% 83.99% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 9487781 8.50% 92.48% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2098555 1.88% 94.36% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1338170 1.20% 95.56% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 960614 0.86% 96.42% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 571645 0.51% 96.93% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 1030883 0.92% 97.86% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 527820 0.47% 98.33% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1866272 1.67% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 115445686 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 38873610 # Number of instructions committed -system.cpu1.commit.committedOps 49214014 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 111667919 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 38872746 # Number of instructions committed +system.cpu1.commit.committedOps 49210296 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 16984908 # Number of memory references committed -system.cpu1.commit.loads 9981032 # Number of loads committed -system.cpu1.commit.membars 195536 # Number of memory barriers committed -system.cpu1.commit.branches 6424997 # Number of branches committed +system.cpu1.commit.refs 16982765 # Number of memory references committed +system.cpu1.commit.loads 9979998 # Number of loads committed +system.cpu1.commit.membars 195533 # Number of memory barriers committed +system.cpu1.commit.branches 6424967 # Number of branches committed system.cpu1.commit.fp_insts 6822 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 43926362 # Number of committed integer instructions. -system.cpu1.commit.function_calls 553376 # Number of function calls committed. +system.cpu1.commit.int_insts 43922606 # Number of committed integer instructions. +system.cpu1.commit.function_calls 553368 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 32169137 65.37% 65.37% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 58263 0.12% 65.48% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 65.48% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 65.48% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 65.48% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 65.48% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 65.48% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 65.48% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 65.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 65.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 65.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 65.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 65.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 65.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 65.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 65.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 65.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 65.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 65.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 65.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 65.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 65.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 65.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 65.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 65.48% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 32167564 65.37% 65.37% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 58261 0.12% 65.49% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 65.49% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 65.49% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 65.49% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 65.49% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 65.49% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 65.49% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 65.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 65.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 65.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 65.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 65.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 65.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 65.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 65.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 65.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 65.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 65.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 65.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 65.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 65.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 65.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 65.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 65.49% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatMisc 1706 0.00% 65.49% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 65.49% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.49% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.49% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 9981032 20.28% 85.77% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 7003876 14.23% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 9979998 20.28% 85.77% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 7002767 14.23% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 49214014 # Class of committed instruction -system.cpu1.commit.bw_lim_events 1835315 # number cycles where commit BW limit reached +system.cpu1.commit.op_class_0::total 49210296 # Class of committed instruction +system.cpu1.commit.bw_lim_events 1866272 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 175201017 # The number of ROB reads -system.cpu1.rob.rob_writes 127586843 # The number of ROB writes -system.cpu1.timesIdled 1428644 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 296058429 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 4796946974 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 38803971 # Number of Instructions Simulated -system.cpu1.committedOps 49144375 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 10.661121 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 10.661121 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.093799 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.093799 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 391634066 # number of integer regfile reads -system.cpu1.int_regfile_writes 56368159 # number of integer regfile writes -system.cpu1.fp_regfile_reads 5144 # number of floating regfile reads -system.cpu1.fp_regfile_writes 2332 # number of floating regfile writes -system.cpu1.misc_regfile_reads 202762353 # number of misc regfile reads -system.cpu1.misc_regfile_writes 723009 # number of misc regfile writes -system.cpu1.icache.tags.replacements 614589 # number of replacements -system.cpu1.icache.tags.tagsinuse 498.738252 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 7056364 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 615101 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 11.471879 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 74953244500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.738252 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974098 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.974098 # Average percentage of cache occupancy +system.cpu1.rob.rob_reads 171825162 # The number of ROB reads +system.cpu1.rob.rob_writes 128514038 # The number of ROB writes +system.cpu1.timesIdled 1427088 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 299213387 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 4796716848 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 38803107 # Number of Instructions Simulated +system.cpu1.committedOps 49140657 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 10.646885 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 10.646885 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.093924 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.093924 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 391718305 # number of integer regfile reads +system.cpu1.int_regfile_writes 56505033 # number of integer regfile writes +system.cpu1.fp_regfile_reads 5108 # number of floating regfile reads +system.cpu1.fp_regfile_writes 2336 # number of floating regfile writes +system.cpu1.misc_regfile_reads 199117817 # number of misc regfile reads +system.cpu1.misc_regfile_writes 722972 # number of misc regfile writes +system.cpu1.icache.tags.replacements 616464 # number of replacements +system.cpu1.icache.tags.tagsinuse 498.721065 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 7090163 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 616976 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 11.491797 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 74744507500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.721065 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974065 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.974065 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 8332995 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 8332995 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 7056364 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 7056364 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 7056364 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 7056364 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 7056364 # number of overall hits -system.cpu1.icache.overall_hits::total 7056364 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 661505 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 661505 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 661505 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 661505 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 661505 # number of overall misses -system.cpu1.icache.overall_misses::total 661505 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8964922762 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 8964922762 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 8964922762 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 8964922762 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 8964922762 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 8964922762 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 7717869 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 7717869 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 7717869 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 7717869 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 7717869 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 7717869 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.085711 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.085711 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.085711 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.085711 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.085711 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.085711 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13552.312926 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13552.312926 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13552.312926 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13552.312926 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13552.312926 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13552.312926 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 3582 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 212 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 16.896226 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.icache.tags.tag_accesses 8371129 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 8371129 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 7090163 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 7090163 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 7090163 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 7090163 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 7090163 # number of overall hits +system.cpu1.icache.overall_hits::total 7090163 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 663949 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 663949 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 663949 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 663949 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 663949 # number of overall misses +system.cpu1.icache.overall_misses::total 663949 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 9003300184 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 9003300184 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 9003300184 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 9003300184 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 9003300184 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 9003300184 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 7754112 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 7754112 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 7754112 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 7754112 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 7754112 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 7754112 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.085625 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.085625 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.085625 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.085625 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.085625 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.085625 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13560.228548 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13560.228548 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13560.228548 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13560.228548 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13560.228548 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13560.228548 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 3101 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 648 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 217 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.290323 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets 648 # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 46379 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 46379 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 46379 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 46379 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 46379 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 46379 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 615126 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 615126 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 615126 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 615126 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 615126 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 615126 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7320744820 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 7320744820 # number of ReadReq MSHR miss cycles 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average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11901.211817 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 46932 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 46932 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 46932 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 46932 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 46932 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 46932 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 617017 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 617017 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 617017 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 617017 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 617017 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 617017 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7343865656 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 7343865656 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7343865656 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 7343865656 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7343865656 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 7343865656 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 4135000 # number of ReadReq MSHR uncacheable cycles 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11902.209592 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11902.209592 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11902.209592 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11902.209592 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11902.209592 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11902.209592 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average 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of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 58206088 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 83999438894 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 83999438894 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 83999438894 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 83999438894 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 8916234 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 8916234 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 5837301 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 5837301 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 113991 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 113991 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 107992 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 107992 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 14753535 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 14753535 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 14753535 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 14753535 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045203 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.045203 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.268322 # miss rate for WriteReq accesses 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15155.140932 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 49730.341692 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 49730.341692 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9243.021287 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9243.021287 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5334.624507 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5334.624507 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 42654.205577 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 42654.205577 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 42654.205577 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 42654.205577 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 29593 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 18156 # number of cycles access was blocked +system.cpu1.dcache.tags.replacements 363234 # number of replacements +system.cpu1.dcache.tags.tagsinuse 485.053035 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 13011922 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 363603 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 35.786069 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 70837218250 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 485.053035 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.947369 # Average percentage of cache occupancy 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for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15207.019920 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15207.019920 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 47072.626032 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 47072.626032 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9220.988318 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9220.988318 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5340.011696 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5340.011696 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 40503.939909 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 40503.939909 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 40503.939909 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 40503.939909 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 30714 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 17665 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 3287 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 175 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.003042 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 103.748571 # average number of cycles each access was blocked +system.cpu1.dcache.blocked::no_targets 190 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.344083 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 92.973684 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 327781 # number of writebacks -system.cpu1.dcache.writebacks::total 327781 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 171674 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 171674 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1403027 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 1403027 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1467 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1467 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1574701 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1574701 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1574701 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1574701 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 231364 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 231364 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 163247 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 163247 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12720 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12720 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10911 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10911 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 394611 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 394611 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 394611 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 394611 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2878773157 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2878773157 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 7001686259 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 7001686259 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89753005 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89753005 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 36382912 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 36382912 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9880459416 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 9880459416 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9880459416 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 9880459416 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169231749012 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169231749012 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25869959988 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25869959988 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 195101709000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 195101709000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025949 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025949 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027966 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027966 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.111588 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.111588 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.101035 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.101035 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026747 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026747 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026747 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026747 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12442.614914 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12442.614914 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42890.137393 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 42890.137393 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7056.053852 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7056.053852 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3334.516726 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3334.516726 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 25038.479454 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 25038.479454 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 25038.479454 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 25038.479454 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 327552 # number of writebacks +system.cpu1.dcache.writebacks::total 327552 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 178171 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 178171 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1413840 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1413840 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1455 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1455 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1592011 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1592011 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1592011 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1592011 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 231317 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 231317 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 163155 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 163155 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12755 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12755 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10944 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10944 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 394472 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 394472 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 394472 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 394472 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2894401946 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2894401946 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 6921941032 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 6921941032 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89586755 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89586755 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 36550912 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 36550912 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9816342978 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 9816342978 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9816342978 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 9816342978 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169231628259 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169231628259 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25874415734 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25874415734 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 195106043993 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 195106043993 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025915 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025915 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027956 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027956 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112057 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112057 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.101331 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.101331 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026722 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026722 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026722 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026722 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12512.707436 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12512.707436 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42425.552585 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 42425.552585 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7023.657781 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7023.657781 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3339.812865 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3339.812865 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 24884.764896 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 24884.764896 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 24884.764896 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 24884.764896 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -2294,18 +2294,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1735350782356 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1735350782356 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1735350782356 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1735350782356 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1734300149849 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1734300149849 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1734300149849 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1734300149849 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 42636 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 42635 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 50408 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 50404 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal Binary files differindex ff60c1de9..9ab4c62df 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini index 9bc002187..f4610569d 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini @@ -12,8 +12,8 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu cpu_clk_domain intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain atags_addr=256 -boot_loader=/dist/binaries/boot.arm -boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +boot_loader=/home/stever/m5/m5_system_2.0b3/binaries/boot.arm +boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain @@ -30,7 +30,7 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 load_offset=0 machine_type=RealView_PBX @@ -42,7 +42,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=tests/halt.sh +readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -85,7 +85,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/disks/linux-arm-ael.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-arm-ael.img read_only=true [system.clk_domain] @@ -172,6 +172,7 @@ smtLSQThreshold=100 smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 +socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false @@ -831,9 +832,9 @@ warn_access=warn pio=system.membus.default [system.physmem] -type=SimpleDRAM +type=DRAMCtrl activation_limit=4 -addr_mapping=RaBaChCo +addr_mapping=RoRaBaChCo banks_per_rank=8 burst_length=8 channels=1 @@ -844,27 +845,33 @@ device_rowbuffer_size=1024 devices_per_rank=8 eventq_index=0 in_addr_map=true +max_accesses_per_row=16 mem_sched_policy=frfcfs +min_writes_per_switch=16 null=false -page_policy=open +page_policy=open_adaptive range=0:134217727 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 +tCK=1250 tCL=13750 tRAS=35000 tRCD=13750 tREFI=7800000 -tRFC=300000 +tRFC=260000 tRP=13750 -tRRD=6250 +tRRD=6000 +tRTP=7500 +tRTW=2500 +tWR=15000 tWTR=7500 -tXAW=40000 -write_buffer_size=32 -write_high_thresh_perc=70 -write_low_thresh_perc=0 +tXAW=30000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 port=system.membus.master[6] [system.realview] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout index 9a2da36f9..c786d9a25 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout @@ -1,14 +1,14 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2014 12:08:08 -gem5 started Jan 23 2014 18:42:01 -gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 +gem5 compiled Jun 21 2014 11:22:42 +gem5 started Jun 21 2014 21:27:42 +gem5 executing on phenom +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 - 0: system.cpu.isa: ISA system set to: 0x6dd8800 0x6dd8800 +info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux.arm.smp.fb.2.6.38.8 + 0: system.cpu.isa: ISA system set to: 0x4e2f380 0x4e2f380 info: Using bootloader at address 0x80000000 info: Using kernel entry physical address at 0x8000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2526146947500 because m5_exit instruction encountered +Exiting @ tick 2525888859000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 4ddd9308a..8259c3ed2 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,137 +1,137 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.526192 # Number of seconds simulated -sim_ticks 2526192217500 # Number of ticks simulated -final_tick 2526192217500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.525889 # Number of seconds simulated +sim_ticks 2525888859000 # Number of ticks simulated +final_tick 2525888859000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 56578 # Simulator instruction rate (inst/s) -host_op_rate 72800 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2369913329 # Simulator tick rate (ticks/s) -host_mem_usage 467016 # Number of bytes of host memory used -host_seconds 1065.94 # Real time elapsed on the host -sim_insts 60309034 # Number of instructions simulated -sim_ops 77600502 # Number of ops (including micro ops) simulated +host_inst_rate 66506 # Simulator instruction rate (inst/s) +host_op_rate 85575 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2785423099 # Simulator tick rate (ticks/s) +host_mem_usage 419792 # Number of bytes of host memory used +host_seconds 906.82 # Real time elapsed on the host +sim_insts 60309513 # Number of instructions simulated +sim_ops 77601128 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 796992 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9095192 # Number of bytes read from this memory -system.physmem.bytes_read::total 129433368 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 796992 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 796992 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3784320 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 3072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 797248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9094168 # Number of bytes read from this memory +system.physmem.bytes_read::total 129432216 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 797248 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 797248 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3785024 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6800392 # Number of bytes written to this memory +system.physmem.bytes_written::total 6801096 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 53 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12453 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142148 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096864 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59130 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 48 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12457 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142132 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096846 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59141 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813148 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47319307 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1343 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 315491 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3600356 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51236548 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 315491 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 315491 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1498033 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1193920 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2691954 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1498033 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47319307 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1343 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 315491 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4794277 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53928501 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15096864 # Number of read requests accepted -system.physmem.writeReqs 813148 # Number of write requests accepted -system.physmem.readBursts 15096864 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 813148 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 961540928 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 4658368 # Total number of bytes read from write queue -system.physmem.bytesWritten 6820736 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 129433368 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6800392 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 72787 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 706544 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4695 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 943480 # Per bank write bursts -system.physmem.perBankRdBursts::1 937980 # Per bank write bursts -system.physmem.perBankRdBursts::2 937559 # Per bank write bursts -system.physmem.perBankRdBursts::3 937528 # Per bank write bursts -system.physmem.perBankRdBursts::4 943087 # Per bank write bursts -system.physmem.perBankRdBursts::5 937982 # Per bank write bursts -system.physmem.perBankRdBursts::6 937070 # Per bank write bursts -system.physmem.perBankRdBursts::7 936990 # Per bank write bursts -system.physmem.perBankRdBursts::8 943982 # Per bank write bursts -system.physmem.perBankRdBursts::9 938303 # Per bank write bursts -system.physmem.perBankRdBursts::10 937119 # Per bank write bursts -system.physmem.perBankRdBursts::11 936407 # Per bank write bursts -system.physmem.perBankRdBursts::12 943924 # Per bank write bursts -system.physmem.perBankRdBursts::13 938214 # Per bank write bursts -system.physmem.perBankRdBursts::14 937241 # Per bank write bursts -system.physmem.perBankRdBursts::15 937211 # Per bank write bursts -system.physmem.perBankWrBursts::0 6601 # Per bank write bursts -system.physmem.perBankWrBursts::1 6388 # Per bank write bursts -system.physmem.perBankWrBursts::2 6528 # Per bank write bursts -system.physmem.perBankWrBursts::3 6554 # Per bank write bursts -system.physmem.perBankWrBursts::4 6464 # Per bank write bursts -system.physmem.perBankWrBursts::5 6726 # Per bank write bursts -system.physmem.perBankWrBursts::6 6713 # Per bank write bursts -system.physmem.perBankWrBursts::7 6652 # Per bank write bursts -system.physmem.perBankWrBursts::8 7031 # Per bank write bursts -system.physmem.perBankWrBursts::9 6803 # Per bank write bursts -system.physmem.perBankWrBursts::10 6461 # Per bank write bursts -system.physmem.perBankWrBursts::11 6104 # Per bank write bursts -system.physmem.perBankWrBursts::12 7064 # Per bank write bursts -system.physmem.perBankWrBursts::13 6684 # Per bank write bursts -system.physmem.perBankWrBursts::14 6965 # Per bank write bursts -system.physmem.perBankWrBursts::15 6836 # Per bank write bursts +system.physmem.num_writes::total 813159 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47324990 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1216 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 25 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 315631 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3600383 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51242245 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 315631 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 315631 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1498492 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1194064 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2692556 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1498492 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47324990 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1216 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 315631 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4794447 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53934801 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15096846 # Number of read requests accepted +system.physmem.writeReqs 813159 # Number of write requests accepted +system.physmem.readBursts 15096846 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 813159 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 961407104 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 4791040 # Total number of bytes read from write queue +system.physmem.bytesWritten 6818432 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 129432216 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6801096 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 74860 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 706594 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4696 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 943526 # Per bank write bursts +system.physmem.perBankRdBursts::1 937990 # Per bank write bursts +system.physmem.perBankRdBursts::2 937469 # Per bank write bursts +system.physmem.perBankRdBursts::3 937431 # Per bank write bursts +system.physmem.perBankRdBursts::4 943079 # Per bank write bursts +system.physmem.perBankRdBursts::5 938170 # Per bank write bursts +system.physmem.perBankRdBursts::6 937203 # Per bank write bursts +system.physmem.perBankRdBursts::7 936910 # Per bank write bursts +system.physmem.perBankRdBursts::8 943866 # Per bank write bursts +system.physmem.perBankRdBursts::9 938107 # Per bank write bursts +system.physmem.perBankRdBursts::10 936563 # Per bank write bursts +system.physmem.perBankRdBursts::11 936045 # Per bank write bursts +system.physmem.perBankRdBursts::12 943886 # Per bank write bursts +system.physmem.perBankRdBursts::13 937531 # Per bank write bursts +system.physmem.perBankRdBursts::14 937186 # Per bank write bursts +system.physmem.perBankRdBursts::15 937024 # Per bank write bursts +system.physmem.perBankWrBursts::0 6617 # Per bank write bursts +system.physmem.perBankWrBursts::1 6376 # Per bank write bursts +system.physmem.perBankWrBursts::2 6529 # Per bank write bursts +system.physmem.perBankWrBursts::3 6558 # Per bank write bursts +system.physmem.perBankWrBursts::4 6459 # Per bank write bursts +system.physmem.perBankWrBursts::5 6705 # Per bank write bursts +system.physmem.perBankWrBursts::6 6711 # Per bank write bursts +system.physmem.perBankWrBursts::7 6649 # Per bank write bursts +system.physmem.perBankWrBursts::8 7036 # Per bank write bursts +system.physmem.perBankWrBursts::9 6794 # Per bank write bursts +system.physmem.perBankWrBursts::10 6454 # Per bank write bursts +system.physmem.perBankWrBursts::11 6111 # Per bank write bursts +system.physmem.perBankWrBursts::12 7073 # Per bank write bursts +system.physmem.perBankWrBursts::13 6679 # Per bank write bursts +system.physmem.perBankWrBursts::14 6963 # Per bank write bursts +system.physmem.perBankWrBursts::15 6824 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2526191083500 # Total gap between requests +system.physmem.totGap 2525887732500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 38 # Read request sizes (log2) system.physmem.readPktSize::3 14942208 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 154618 # Read request sizes (log2) +system.physmem.readPktSize::6 154600 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 754018 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 59130 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1056388 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 996212 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 954030 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1063517 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 957350 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1019929 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2630220 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2535649 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3302007 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 132277 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 114408 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 104766 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 100921 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 19448 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 18562 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 18244 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 130 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59141 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1057329 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 995712 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 953847 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1057444 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 956989 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1015779 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2635918 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2545995 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3318157 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 125455 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 108163 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 99319 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 95398 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 19431 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 18601 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 18316 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 110 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -159,28 +159,28 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2638 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2876 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4413 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6437 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2592 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4314 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6296 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6465 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 6394 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6386 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6781 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6447 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6429 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6438 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6345 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6465 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6388 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6736 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6476 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6428 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6463 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6391 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6379 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6746 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6351 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see @@ -208,50 +208,49 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 995555 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 972.685250 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 907.127186 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 202.423056 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22972 2.31% 2.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 19885 2.00% 4.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8241 0.83% 5.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2302 0.23% 5.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2369 0.24% 5.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1811 0.18% 5.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8514 0.86% 6.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 964 0.10% 6.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 928497 93.26% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 995555 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6226 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2413.115644 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 115125.420570 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-524287 6222 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 995372 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 972.727318 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 907.205467 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 202.336600 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22984 2.31% 2.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 19752 1.98% 4.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8337 0.84% 5.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2265 0.23% 5.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2301 0.23% 5.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1840 0.18% 5.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8587 0.86% 6.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 978 0.10% 6.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 928328 93.26% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 995372 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6241 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2406.981894 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 114987.414706 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-524287 6237 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.03% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2.09715e+06-2.62144e+06 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6226 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6226 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.117571 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.060113 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.446555 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3515 56.46% 56.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 41 0.66% 57.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 1615 25.94% 83.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 842 13.52% 96.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 76 1.22% 97.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 41 0.66% 98.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 38 0.61% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 41 0.66% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 16 0.26% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6226 # Writes before turning the bus around for reads -system.physmem.totQLat 389908010000 # Total ticks spent queuing -system.physmem.totMemAccLat 671609453750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 75120385000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25952.21 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6241 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6241 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.070662 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.017388 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.386394 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3585 57.44% 57.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 32 0.51% 57.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 1616 25.89% 83.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 845 13.54% 97.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 54 0.87% 98.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 36 0.58% 98.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 33 0.53% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 31 0.50% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 9 0.14% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6241 # Writes before turning the bus around for reads +system.physmem.totQLat 389024977250 # Total ticks spent queuing +system.physmem.totMemAccLat 670687214750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 75109930000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25897.04 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44702.21 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 380.63 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 44647.04 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 380.62 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.70 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 51.24 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.69 # Average system write bandwidth in MiByte/s @@ -259,18 +258,18 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 2.99 # Data bus utilization in percentage system.physmem.busUtilRead 2.97 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 6.80 # Average read queue length when enqueuing -system.physmem.avgWrQLen 27.01 # Average write queue length when enqueuing -system.physmem.readRowHits 14044000 # Number of row buffer hits during reads -system.physmem.writeRowHits 91096 # Number of row buffer hits during writes +system.physmem.avgRdQLen 6.85 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.12 # Average write queue length when enqueuing +system.physmem.readRowHits 14042089 # Number of row buffer hits during reads +system.physmem.writeRowHits 91063 # Number of row buffer hits during writes system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads system.physmem.writeRowHitRate 85.45 # Row buffer hit rate for writes -system.physmem.avgGap 158779.96 # Average gap between requests +system.physmem.avgGap 158760.96 # Average gap between requests system.physmem.pageHitRate 93.42 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2186359463750 # Time in different power states -system.physmem.memoryStateTime::REF 84354920000 # Time in different power states +system.physmem.memoryStateTime::IDLE 2186215098000 # Time in different power states +system.physmem.memoryStateTime::REF 84344780000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 255472398750 # Time in different power states +system.physmem.memoryStateTime::ACT 255323240750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory @@ -284,50 +283,50 @@ system.realview.nvmem.bw_inst_read::cpu.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54877773 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16149486 # Transaction distribution -system.membus.trans_dist::ReadResp 16149486 # Transaction distribution +system.membus.throughput 54884184 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16149487 # Transaction distribution +system.membus.trans_dist::ReadResp 16149487 # Transaction distribution system.membus.trans_dist::WriteReq 763349 # Transaction distribution system.membus.trans_dist::WriteResp 763349 # Transaction distribution -system.membus.trans_dist::Writeback 59130 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4692 # Transaction distribution +system.membus.trans_dist::Writeback 59141 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4693 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4695 # Transaction distribution -system.membus.trans_dist::ReadExReq 131451 # Transaction distribution -system.membus.trans_dist::ReadExResp 131451 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383044 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::UpgradeResp 4696 # Transaction distribution +system.membus.trans_dist::ReadExReq 131431 # Transaction distribution +system.membus.trans_dist::ReadExResp 131431 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383042 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3760 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885868 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272676 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885845 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272651 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29884416 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 29884416 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34157092 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390454 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 34157067 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390450 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7520 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16696096 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19094138 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16695648 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19093686 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119537664 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 119537664 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 138631802 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 138631802 # Total data (bytes) +system.membus.tot_pkt_size::total 138631350 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 138631350 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1486816000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1486861000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3620500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3602500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17362899000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17311099000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4734189076 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4710414902 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 36898450149 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 36916757411 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.5 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -335,13 +334,13 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 48265574 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16125556 # Transaction distribution -system.iobus.trans_dist::ReadResp 16125556 # Transaction distribution +system.iobus.throughput 48271369 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16125555 # Transaction distribution +system.iobus.trans_dist::ReadResp 16125555 # Transaction distribution system.iobus.trans_dist::WriteReq 8174 # Transaction distribution system.iobus.trans_dist::WriteResp 8174 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7936 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7934 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 516 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1024 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -363,12 +362,12 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2383044 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2383042 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 29884416 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 29884416 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 32267460 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 32267458 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15872 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15868 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1032 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2048 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -390,14 +389,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390454 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390450 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 119537664 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 119537664 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 121928118 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 121928118 # Total data (bytes) +system.iobus.tot_pkt_size::total 121928114 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 121928114 # Total data (bytes) system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3973000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 3972000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 516000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -443,20 +442,20 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 14942208000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374870000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374868000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 37675624851 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 37649719589 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 14753661 # Number of BP lookups -system.cpu.branchPred.condPredicted 11836576 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 705670 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9513727 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7668660 # Number of BTB hits +system.cpu.branchPred.lookups 14910337 # Number of BP lookups +system.cpu.branchPred.condPredicted 11976867 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 705848 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9580478 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7742107 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.606265 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1399145 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72578 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 80.811281 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1408303 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 72648 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -480,25 +479,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51183231 # DTB read hits -system.cpu.dtb.read_misses 65223 # DTB read misses -system.cpu.dtb.write_hits 11700953 # DTB write hits -system.cpu.dtb.write_misses 15725 # DTB write misses +system.cpu.dtb.read_hits 51097792 # DTB read hits +system.cpu.dtb.read_misses 64987 # DTB read misses +system.cpu.dtb.write_hits 11709971 # DTB write hits +system.cpu.dtb.write_misses 15921 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3479 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2504 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 408 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 3472 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2569 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 428 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1339 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51248454 # DTB read accesses -system.cpu.dtb.write_accesses 11716678 # DTB write accesses +system.cpu.dtb.perms_faults 1363 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51162779 # DTB read accesses +system.cpu.dtb.write_accesses 11725892 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 62884184 # DTB hits -system.cpu.dtb.misses 80948 # DTB misses -system.cpu.dtb.accesses 62965132 # DTB accesses +system.cpu.dtb.hits 62807763 # DTB hits +system.cpu.dtb.misses 80908 # DTB misses +system.cpu.dtb.accesses 62888671 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -520,8 +519,8 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 11525561 # ITB inst hits -system.cpu.itb.inst_misses 11159 # ITB inst misses +system.cpu.itb.inst_hits 11575507 # ITB inst hits +system.cpu.itb.inst_misses 11335 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -530,265 +529,266 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2509 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2514 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2978 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2954 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 11536720 # ITB inst accesses -system.cpu.itb.hits 11525561 # DTB hits -system.cpu.itb.misses 11159 # DTB misses -system.cpu.itb.accesses 11536720 # DTB accesses -system.cpu.numCycles 477128882 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 11586842 # ITB inst accesses +system.cpu.itb.hits 11575507 # DTB hits +system.cpu.itb.misses 11335 # DTB misses +system.cpu.itb.accesses 11586842 # DTB accesses +system.cpu.numCycles 476238509 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 29759197 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 90327124 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14753661 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9067805 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 20158177 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4657193 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 122600 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 98301886 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2694 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 86268 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 2686675 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 550 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11522069 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 710692 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5197 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 154327188 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.729776 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.081128 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 29789702 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 91027179 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14910337 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9150410 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 20302096 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4754274 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 125108 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 93772455 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2699 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 88682 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 2727734 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 553 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11572027 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 712397 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5390 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 150113292 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.756026 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.113644 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 134184573 86.95% 86.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1304702 0.85% 87.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1713961 1.11% 88.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2295969 1.49% 90.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2111581 1.37% 91.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1105061 0.72% 92.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2556088 1.66% 94.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 746376 0.48% 94.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8308877 5.38% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 129826802 86.49% 86.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1312716 0.87% 87.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1720953 1.15% 88.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2304331 1.54% 90.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2116294 1.41% 91.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1112529 0.74% 92.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2605432 1.74% 93.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 752346 0.50% 94.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8361889 5.57% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 154327188 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.030922 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.189314 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 31784305 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 100158613 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18079626 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1265080 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3039564 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1958546 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 172069 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 107310478 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 569843 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3039564 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 33522780 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 38730372 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 55131073 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 17590016 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6313383 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102310347 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 498 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 999968 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4068660 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 821 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 106387059 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 473967662 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 432826370 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10390 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78726997 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27660061 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1170574 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1076856 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12635163 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 19719056 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13304976 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1944651 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2472247 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 95130107 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1987847 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 122918672 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 165693 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 18947879 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 47268855 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 505540 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 154327188 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.796481 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.515149 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 150113292 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.031309 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.191138 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31268958 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 96222513 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18495001 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 992442 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3134378 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1970530 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 172531 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 108153308 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 572201 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3134378 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 32906794 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 14229038 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 56831984 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 17995352 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 25015746 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 103064055 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1610 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 17097046 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 19764397 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 2757051 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 1781 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 107250734 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 477314257 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 435890251 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 10500 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78727504 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 28523229 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1172187 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1078501 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 11007211 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 19896895 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13369840 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2003415 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2457274 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 95806828 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1986007 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 122955094 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 190842 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 19616274 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 49695395 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 503680 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 150113292 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.819082 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.543742 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 109964387 71.25% 71.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 14401004 9.33% 80.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 6880878 4.46% 85.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5675452 3.68% 88.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12310168 7.98% 96.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2806019 1.82% 98.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1694480 1.10% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 466491 0.30% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 128309 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 106692829 71.07% 71.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13471343 8.97% 80.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 6554897 4.37% 84.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5548193 3.70% 88.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12665338 8.44% 96.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2805396 1.87% 98.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1723552 1.15% 99.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 514218 0.34% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 137526 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 154327188 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 150113292 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 61903 0.70% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8364845 94.62% 95.32% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 413343 4.68% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 66740 0.75% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 6 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8421993 94.18% 94.93% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 453824 5.07% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 28518 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 57967032 47.16% 47.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93290 0.08% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 13 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 14 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52507324 42.72% 89.98% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12320347 10.02% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58064867 47.22% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93414 0.08% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 15 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 16 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52433900 42.64% 89.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12332230 10.03% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 122918672 # Type of FU issued -system.cpu.iq.rate 0.257622 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8840095 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071918 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 409227562 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 116082546 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85482417 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23345 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12482 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10295 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 131717793 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12456 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 625155 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 122955094 # Type of FU issued +system.cpu.iq.rate 0.258180 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8942563 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.072730 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 405214220 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 117427083 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85619955 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23208 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12528 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10296 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 131856805 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12334 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 652625 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4064409 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6818 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30381 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1573005 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4242114 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 5511 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 31676 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1637740 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107982 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 680619 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 33981236 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 675243 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3039564 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 30259815 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 434333 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 97340803 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 205354 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 19719056 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13304976 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1415400 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 113322 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3328 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30381 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 350453 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 269952 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 620405 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 120843569 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 51870507 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2075103 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3134378 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 11621778 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1344860 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 98019144 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 177250 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 19896895 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13369840 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1412264 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 282212 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 925122 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 31676 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 351157 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 270951 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 622108 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 120868290 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 51786364 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2086804 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 222849 # number of nop insts executed -system.cpu.iew.exec_refs 64083354 # number of memory reference insts executed -system.cpu.iew.exec_branches 11822089 # Number of branches executed -system.cpu.iew.exec_stores 12212847 # Number of stores executed -system.cpu.iew.exec_rate 0.253272 # Inst execution rate -system.cpu.iew.wb_sent 119902421 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85492712 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47017508 # num instructions producing a value -system.cpu.iew.wb_consumers 87566112 # num instructions consuming a value +system.cpu.iew.exec_nop 226309 # number of nop insts executed +system.cpu.iew.exec_refs 64008543 # number of memory reference insts executed +system.cpu.iew.exec_branches 11843747 # Number of branches executed +system.cpu.iew.exec_stores 12222179 # Number of stores executed +system.cpu.iew.exec_rate 0.253798 # Inst execution rate +system.cpu.iew.wb_sent 119919333 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85630251 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47892202 # num instructions producing a value +system.cpu.iew.wb_consumers 88557277 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.179182 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.536937 # average fanout of values written-back +system.cpu.iew.wb_rate 0.179805 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.540805 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 18682974 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1482307 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 536093 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 151287624 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.513928 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.489816 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 19373634 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1482327 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 535963 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 146978914 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.528998 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.513466 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 122817908 81.18% 81.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 14643914 9.68% 90.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3918754 2.59% 93.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2134639 1.41% 94.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1621396 1.07% 95.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 973729 0.64% 96.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1595383 1.05% 97.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 716191 0.47% 98.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2865710 1.89% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 118714103 80.77% 80.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 14514329 9.88% 90.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3718532 2.53% 93.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2215097 1.51% 94.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1629859 1.11% 95.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1057435 0.72% 96.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1495738 1.02% 97.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 696782 0.47% 98.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2937039 2.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 151287624 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60459415 # Number of instructions committed -system.cpu.commit.committedOps 77750883 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 146978914 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60459894 # Number of instructions committed +system.cpu.commit.committedOps 77751509 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27386618 # Number of memory references committed -system.cpu.commit.loads 15654647 # Number of loads committed -system.cpu.commit.membars 403571 # Number of memory barriers committed -system.cpu.commit.branches 10306311 # Number of branches committed +system.cpu.commit.refs 27386881 # Number of memory references committed +system.cpu.commit.loads 15654781 # Number of loads committed +system.cpu.commit.membars 403574 # Number of memory barriers committed +system.cpu.commit.branches 10306383 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 69190973 # Number of committed integer instructions. -system.cpu.commit.function_calls 991245 # Number of function calls committed. +system.cpu.commit.int_insts 69191543 # Number of committed integer instructions. +system.cpu.commit.function_calls 991261 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 50274217 64.66% 64.66% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 50274580 64.66% 64.66% # Class of committed instruction system.cpu.commit.op_class_0::IntMult 87935 0.11% 64.77% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 64.77% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 64.77% # Class of committed instruction @@ -817,319 +817,319 @@ system.cpu.commit.op_class_0::SimdFloatMisc 2113 0.00% 64.78% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 64.78% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.78% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.78% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 15654647 20.13% 84.91% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 11731971 15.09% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 15654781 20.13% 84.91% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 11732100 15.09% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 77750883 # Class of committed instruction -system.cpu.commit.bw_lim_events 2865710 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 77751509 # Class of committed instruction +system.cpu.commit.bw_lim_events 2937039 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 243007370 # The number of ROB reads -system.cpu.rob.rob_writes 195993770 # The number of ROB writes -system.cpu.timesIdled 1776375 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 322801694 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4575172520 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60309034 # Number of Instructions Simulated -system.cpu.committedOps 77600502 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.911400 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.911400 # CPI: Total CPI of All Threads -system.cpu.ipc 0.126400 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.126400 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 548643015 # number of integer regfile reads -system.cpu.int_regfile_writes 87545924 # number of integer regfile writes -system.cpu.fp_regfile_reads 8332 # number of floating regfile reads -system.cpu.fp_regfile_writes 2902 # number of floating regfile writes -system.cpu.misc_regfile_reads 268108891 # number of misc regfile reads -system.cpu.misc_regfile_writes 1173224 # number of misc regfile writes -system.cpu.toL2Bus.throughput 58876928 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2658786 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2658785 # Transaction distribution +system.cpu.rob.rob_reads 239318561 # The number of ROB reads +system.cpu.rob.rob_writes 197472000 # The number of ROB writes +system.cpu.timesIdled 1764819 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 326125217 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4575456172 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60309513 # Number of Instructions Simulated +system.cpu.committedOps 77601128 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 7.896574 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.896574 # CPI: Total CPI of All Threads +system.cpu.ipc 0.126637 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.126637 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 548833940 # number of integer regfile reads +system.cpu.int_regfile_writes 87707844 # number of integer regfile writes +system.cpu.fp_regfile_reads 8328 # number of floating regfile reads +system.cpu.fp_regfile_writes 2914 # number of floating regfile writes +system.cpu.misc_regfile_reads 264312368 # number of misc regfile reads +system.cpu.misc_regfile_writes 1173237 # number of misc regfile writes +system.cpu.toL2Bus.throughput 58892733 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2658790 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2658789 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 763349 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 763349 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 607456 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 607940 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2966 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 12 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2978 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 246178 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 246178 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1963155 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5795994 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30467 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128822 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7918438 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62783488 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85496634 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 41888 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 215832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 148537842 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 148537842 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 196596 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3128822166 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 11 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2977 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 246105 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 246105 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1961974 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5797376 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30926 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128827 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7919103 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62745984 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85556470 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 42736 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 216536 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 148561726 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 148561726 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 194772 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3129487727 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1475557763 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1474700416 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2549946762 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2550487184 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 19999491 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 20248986 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 74967796 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 74797546 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 981488 # number of replacements -system.cpu.icache.tags.tagsinuse 511.574363 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 10460581 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 982000 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 10.652323 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 6957426250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.574363 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999169 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999169 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 980898 # number of replacements +system.cpu.icache.tags.tagsinuse 511.584882 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 10510158 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 981410 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 10.709243 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 6868426250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.584882 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999189 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999189 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 222 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 155 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 214 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 160 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 12503981 # Number of tag accesses -system.cpu.icache.tags.data_accesses 12503981 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 10460581 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 10460581 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 10460581 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 10460581 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 10460581 # number of overall hits -system.cpu.icache.overall_hits::total 10460581 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1061360 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1061360 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1061360 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1061360 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1061360 # number of overall misses -system.cpu.icache.overall_misses::total 1061360 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14265779687 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14265779687 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14265779687 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14265779687 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14265779687 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14265779687 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11521941 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11521941 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11521941 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11521941 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11521941 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11521941 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092116 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.092116 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.092116 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.092116 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.092116 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.092116 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13441.037619 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13441.037619 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13441.037619 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13441.037619 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13441.037619 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13441.037619 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 7028 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 352 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 19.965909 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.tags.tag_accesses 12553342 # Number of tag accesses +system.cpu.icache.tags.data_accesses 12553342 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 10510158 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 10510158 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 10510158 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 10510158 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 10510158 # number of overall hits +system.cpu.icache.overall_hits::total 10510158 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1061739 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1061739 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1061739 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1061739 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1061739 # number of overall misses +system.cpu.icache.overall_misses::total 1061739 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14266290615 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14266290615 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14266290615 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14266290615 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14266290615 # number of overall miss cycles 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accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.091752 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.091752 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13436.720903 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13436.720903 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13436.720903 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13436.720903 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13436.720903 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13436.720903 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 7331 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 116 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 335 # number of cycles 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blocks. +system.cpu.dcache.tags.avg_refs 33.356848 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 42393250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.993313 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999987 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 301 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 195 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id 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# miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052772 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000048 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000048 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.149679 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.149679 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.149679 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.149679 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13568.722855 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13568.722855 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47172.620888 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 47172.620888 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13685.767024 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13685.767024 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16125.250000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16125.250000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 40494.440116 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 40494.440116 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 40494.440116 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 40494.440116 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 32269 # number of cycles access was blocked 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accesses +system.cpu.dcache.overall_miss_rate::total 0.150865 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13343.931358 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13343.931358 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45954.568802 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 45954.568802 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13660.513599 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13660.513599 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16409.363636 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16409.363636 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 39291.924564 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 39291.924564 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39291.924564 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39291.924564 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 33676 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 25542 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2667 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 316 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.626922 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 80.829114 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed 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11947.345832 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14124.750000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14124.750000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25674.939566 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25674.939566 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25674.939566 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 25674.939566 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 607940 # number of writebacks +system.cpu.dcache.writebacks::total 607940 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 376141 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 376141 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2719425 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2719425 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1345 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1345 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3095566 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3095566 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3095566 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3095566 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 386060 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 386060 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249004 # number of WriteReq MSHR misses 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# number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11232028289 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11232028289 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 145250501 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 145250501 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 158497 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 158497 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16200504652 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16200504652 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16200504652 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16200504652 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182335641750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182335641750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26891357119 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26891357119 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209226998869 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 209226998869 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026614 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026614 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024359 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024359 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047533 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047533 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000044 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025682 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025682 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12869.699951 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12869.699951 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45107.822722 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45107.822722 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11920.435043 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11920.435043 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14408.818182 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14408.818182 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25510.034661 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25510.034661 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25510.034661 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25510.034661 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1435,16 +1435,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1712402234851 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1712402234851 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1712402234851 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1712402234851 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1711484214589 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1711484214589 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1711484214589 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1711484214589 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83034 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 83038 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/system.terminal Binary files differindex 8f4cb76c4..69a162eed 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/system.terminal diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini index b551f2cf3..e53092e6a 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini @@ -12,8 +12,8 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu2 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=256 -boot_loader=/dist/binaries/boot.arm -boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +boot_loader=/home/stever/m5/m5_system_2.0b3/binaries/boot.arm +boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain @@ -30,7 +30,7 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 load_offset=0 machine_type=RealView_PBX @@ -42,7 +42,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=tests/halt.sh +readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -85,7 +85,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/disks/linux-arm-ael.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-arm-ael.img read_only=true [system.clk_domain] @@ -97,6 +97,7 @@ voltage_domain=system.voltage_domain [system.cpu0] type=AtomicSimpleCPU children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer +branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 @@ -126,6 +127,7 @@ simpoint_profile_file=simpoint.bb.gz simpoint_start_insts= simulate_data_stalls=false simulate_inst_stalls=false +socket_id=0 switched_out=false system=system tracer=system.cpu0.tracer @@ -326,6 +328,7 @@ eventq_index=0 [system.cpu1] type=TimingSimpleCPU children=dstage2_mmu dtb isa istage2_mmu itb tracer +branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 @@ -349,6 +352,7 @@ numThreads=1 profile=0 progress_interval=0 simpoint_start_insts= +socket_id=0 switched_out=true system=system tracer=system.cpu1.tracer @@ -543,6 +547,7 @@ smtLSQThreshold=100 smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 +socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=true @@ -1111,9 +1116,9 @@ warn_access=warn pio=system.membus.default [system.physmem] -type=SimpleDRAM +type=DRAMCtrl activation_limit=4 -addr_mapping=RaBaChCo +addr_mapping=RoRaBaChCo banks_per_rank=8 burst_length=8 channels=1 @@ -1124,27 +1129,33 @@ device_rowbuffer_size=1024 devices_per_rank=8 eventq_index=0 in_addr_map=true +max_accesses_per_row=16 mem_sched_policy=frfcfs +min_writes_per_switch=16 null=false -page_policy=open +page_policy=open_adaptive range=0:134217727 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 +tCK=1250 tCL=13750 tRAS=35000 tRCD=13750 tREFI=7800000 -tRFC=300000 +tRFC=260000 tRP=13750 -tRRD=6250 +tRRD=6000 +tRTP=7500 +tRTW=2500 +tWR=15000 tWTR=7500 -tXAW=40000 -write_buffer_size=32 -write_high_thresh_perc=70 -write_low_thresh_perc=0 +tXAW=30000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 port=system.membus.master[6] [system.realview] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout index 21d388ebd..bb9bfcfdd 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2014 12:08:08 -gem5 started Jan 23 2014 19:05:28 -gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full +gem5 compiled Jun 21 2014 11:22:42 +gem5 started Jun 21 2014 21:27:42 +gem5 executing on phenom +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full Global frequency set at 1000000000000 ticks per second - 0: system.cpu0.isa: ISA system set to: 0x5606400 0x5606400 - 0: system.cpu1.isa: ISA system set to: 0x5606400 0x5606400 - 0: system.cpu2.isa: ISA system set to: 0x5606400 0x5606400 + 0: system.cpu0.isa: ISA system set to: 0x61c8fe0 0x61c8fe0 + 0: system.cpu1.isa: ISA system set to: 0x61c8fe0 0x61c8fe0 + 0: system.cpu2.isa: ISA system set to: 0x61c8fe0 0x61c8fe0 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index 60f6414c0..d741bed70 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -1,168 +1,168 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.403852 # Number of seconds simulated -sim_ticks 2403852457500 # Number of ticks simulated -final_tick 2403852457500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.403860 # Number of seconds simulated +sim_ticks 2403859810000 # Number of ticks simulated +final_tick 2403859810000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 165592 # Simulator instruction rate (inst/s) -host_op_rate 212680 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6597855857 # Simulator tick rate (ticks/s) -host_mem_usage 469068 # Number of bytes of host memory used -host_seconds 364.34 # Real time elapsed on the host -sim_insts 60331653 # Number of instructions simulated -sim_ops 77487544 # Number of ops (including micro ops) simulated +host_inst_rate 189252 # Simulator instruction rate (inst/s) +host_op_rate 243065 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7540617560 # Simulator tick rate (ticks/s) +host_mem_usage 419508 # Number of bytes of host memory used +host_seconds 318.79 # Real time elapsed on the host +sim_insts 60331162 # Number of instructions simulated +sim_ops 77486236 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 512456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 7048216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 510792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 7044824 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 63936 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 680960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 576 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 186944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1348288 # Number of bytes read from this memory -system.physmem.bytes_read::total 124660704 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 512456 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 63936 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 186944 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 763336 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3743808 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1298564 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 159248 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2.data 1558004 # Number of bytes written to this memory -system.physmem.bytes_written::total 6759624 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 65024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 679232 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 188416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1352768 # Number of bytes read from this memory +system.physmem.bytes_read::total 124661152 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 510792 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 65024 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 188416 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 764232 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3745216 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1298452 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 159256 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2.data 1558108 # Number of bytes written to this memory +system.physmem.bytes_written::total 6761032 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14352384 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 14219 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 110164 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 14193 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 110111 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 999 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10640 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 9 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 2921 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 21067 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14512407 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 58497 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 324641 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 39812 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2.data 389501 # Number of write requests responded to by this memory -system.physmem.num_writes::total 812451 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47764609 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu1.inst 1016 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10613 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 12 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 2944 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 21137 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14512414 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 58519 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 324613 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 39814 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2.data 389527 # Number of write requests responded to by this memory +system.physmem.num_writes::total 812473 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47764463 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 53 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 213181 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 2932050 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 212488 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 2930630 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 26597 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 283279 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 240 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 77769 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 560886 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51858717 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 213181 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 26597 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 77769 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 317547 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1557420 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 540201 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 66247 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2.data 648128 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2811996 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1557420 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47764609 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 27050 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 282559 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 319 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 78381 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 562748 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51858745 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 212488 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 27050 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 78381 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 317919 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1558001 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 540153 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 66250 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2.data 648169 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2812573 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1558001 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47764463 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 53 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 213181 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3472251 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 212488 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3470783 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 26597 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 349526 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 240 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 77769 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1209014 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54670713 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 13446501 # Number of read requests accepted -system.physmem.writeReqs 446412 # Number of write requests accepted -system.physmem.readBursts 13446501 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 446412 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 860576000 # Total number of bytes read from DRAM +system.physmem.bw_total::cpu1.inst 27050 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 348809 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 319 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 78381 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1210918 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54671318 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 13444811 # Number of read requests accepted +system.physmem.writeReqs 446538 # Number of write requests accepted +system.physmem.readBursts 13444811 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 446538 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 860467840 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 64 # Total number of bytes read from write queue -system.physmem.bytesWritten 2816640 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 109567680 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 2811588 # Total written bytes from the system interface side +system.physmem.bytesWritten 2823232 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 109558976 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 2817972 # Total written bytes from the system interface side system.physmem.servicedByWrQ 1 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 402376 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 2365 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 835689 # Per bank write bursts -system.physmem.perBankRdBursts::1 835334 # Per bank write bursts -system.physmem.perBankRdBursts::2 835514 # Per bank write bursts -system.physmem.perBankRdBursts::3 835992 # Per bank write bursts -system.physmem.perBankRdBursts::4 837083 # Per bank write bursts -system.physmem.perBankRdBursts::5 837766 # Per bank write bursts -system.physmem.perBankRdBursts::6 837910 # Per bank write bursts -system.physmem.perBankRdBursts::7 839140 # Per bank write bursts -system.physmem.perBankRdBursts::8 840643 # Per bank write bursts -system.physmem.perBankRdBursts::9 843328 # Per bank write bursts -system.physmem.perBankRdBursts::10 843395 # Per bank write bursts -system.physmem.perBankRdBursts::11 843892 # Per bank write bursts -system.physmem.perBankRdBursts::12 845429 # Per bank write bursts -system.physmem.perBankRdBursts::13 846004 # Per bank write bursts -system.physmem.perBankRdBursts::14 844795 # Per bank write bursts -system.physmem.perBankRdBursts::15 844586 # Per bank write bursts -system.physmem.perBankWrBursts::0 2674 # Per bank write bursts -system.physmem.perBankWrBursts::1 2534 # Per bank write bursts -system.physmem.perBankWrBursts::2 2538 # Per bank write bursts -system.physmem.perBankWrBursts::3 3024 # Per bank write bursts -system.physmem.perBankWrBursts::4 3410 # Per bank write bursts -system.physmem.perBankWrBursts::5 3131 # Per bank write bursts -system.physmem.perBankWrBursts::6 2493 # Per bank write bursts -system.physmem.perBankWrBursts::7 2267 # Per bank write bursts -system.physmem.perBankWrBursts::8 2164 # Per bank write bursts +system.physmem.mergedWrBursts 402393 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 2368 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 835670 # Per bank write bursts +system.physmem.perBankRdBursts::1 835346 # Per bank write bursts +system.physmem.perBankRdBursts::2 835517 # Per bank write bursts +system.physmem.perBankRdBursts::3 836010 # Per bank write bursts +system.physmem.perBankRdBursts::4 837094 # Per bank write bursts +system.physmem.perBankRdBursts::5 837780 # Per bank write bursts +system.physmem.perBankRdBursts::6 837922 # Per bank write bursts +system.physmem.perBankRdBursts::7 839142 # Per bank write bursts +system.physmem.perBankRdBursts::8 840618 # Per bank write bursts +system.physmem.perBankRdBursts::9 843327 # Per bank write bursts +system.physmem.perBankRdBursts::10 843373 # Per bank write bursts +system.physmem.perBankRdBursts::11 843894 # Per bank write bursts +system.physmem.perBankRdBursts::12 845193 # Per bank write bursts +system.physmem.perBankRdBursts::13 844981 # Per bank write bursts +system.physmem.perBankRdBursts::14 844356 # Per bank write bursts +system.physmem.perBankRdBursts::15 844587 # Per bank write bursts +system.physmem.perBankWrBursts::0 2683 # Per bank write bursts +system.physmem.perBankWrBursts::1 2536 # Per bank write bursts +system.physmem.perBankWrBursts::2 2524 # Per bank write bursts +system.physmem.perBankWrBursts::3 3040 # Per bank write bursts +system.physmem.perBankWrBursts::4 3434 # Per bank write bursts +system.physmem.perBankWrBursts::5 3138 # Per bank write bursts +system.physmem.perBankWrBursts::6 2510 # Per bank write bursts +system.physmem.perBankWrBursts::7 2271 # Per bank write bursts +system.physmem.perBankWrBursts::8 2160 # Per bank write bursts system.physmem.perBankWrBursts::9 2378 # Per bank write bursts -system.physmem.perBankWrBursts::10 2328 # Per bank write bursts +system.physmem.perBankWrBursts::10 2319 # Per bank write bursts system.physmem.perBankWrBursts::11 2803 # Per bank write bursts -system.physmem.perBankWrBursts::12 3718 # Per bank write bursts -system.physmem.perBankWrBursts::13 3446 # Per bank write bursts -system.physmem.perBankWrBursts::14 2595 # Per bank write bursts -system.physmem.perBankWrBursts::15 2507 # Per bank write bursts +system.physmem.perBankWrBursts::12 3771 # Per bank write bursts +system.physmem.perBankWrBursts::13 3447 # Per bank write bursts +system.physmem.perBankWrBursts::14 2601 # Per bank write bursts +system.physmem.perBankWrBursts::15 2498 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2402816386500 # Total gap between requests +system.physmem.totGap 2402823771000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 13410864 # Read request sizes (log2) +system.physmem.readPktSize::3 13409088 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 35637 # Read request sizes (log2) +system.physmem.readPktSize::6 35723 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 429313 # Write request sizes (log2) +system.physmem.writePktSize::2 429341 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 17099 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 877452 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 853858 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 853065 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 937219 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 861122 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 912169 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2402802 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2330624 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3052022 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 86874 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 80661 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 76244 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 73288 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 16615 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 16291 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 16173 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 21 # What read queue length does an incoming req see +system.physmem.writePktSize::6 17197 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 877930 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 852855 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 852810 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 941410 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 861042 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 915654 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2398641 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2321801 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3038639 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 92226 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 84687 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 80541 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 77647 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 16577 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 16214 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 16108 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 28 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -178,10 +178,10 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 100 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 97 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 96 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 95 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 95 # What write queue length does an incoming req see @@ -193,27 +193,27 @@ system.physmem.wrQLenPdf::11 93 # Wh system.physmem.wrQLenPdf::12 92 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 92 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1916 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1920 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 2109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2309 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2421 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2538 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 2461 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 2402 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 2681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2411 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 2396 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 2417 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 2368 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 2356 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 2413 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 2343 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 2346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 2344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 2313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2300 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 2423 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2579 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 2455 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 2431 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 2665 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 2414 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 2438 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 2433 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 2373 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 2390 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 2400 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 2348 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 2337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 2336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 2315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see @@ -242,63 +242,64 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 866032 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 996.952353 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 964.296727 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 145.584191 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 8288 0.96% 0.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 8846 1.02% 1.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6189 0.71% 2.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 800 0.09% 2.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 916 0.11% 2.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 687 0.08% 2.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7828 0.90% 3.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 865990 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 996.883419 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 964.040735 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 145.863432 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 8417 0.97% 0.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 8847 1.02% 1.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6111 0.71% 2.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 842 0.10% 2.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 894 0.10% 2.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 743 0.09% 2.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7672 0.89% 3.87% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 243 0.03% 3.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 832235 96.10% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 866032 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 2414 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 5570.207125 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 258157.496677 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-524287 2413 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::1024-1151 832221 96.10% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 865990 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 2416 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 5564.893626 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 258050.737776 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-524287 2415 99.96% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1.25829e+07-1.31072e+07 1 0.04% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 2414 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 2414 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.231152 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.108696 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.979905 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::2 1 0.04% 0.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::3 2 0.08% 0.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4 1 0.04% 0.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::5 1 0.04% 0.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::7 2 0.08% 0.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::9 1 0.04% 0.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12 1 0.04% 0.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::14 1 0.04% 0.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::15 7 0.29% 0.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 485 20.09% 20.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 15 0.62% 21.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 872 36.12% 57.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 845 35.00% 92.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 52 2.15% 94.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 24 0.99% 95.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 26 1.08% 96.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 34 1.41% 98.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 13 0.54% 98.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 5 0.21% 98.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 6 0.25% 99.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 1 0.04% 99.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 6 0.25% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 7 0.29% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 2 0.08% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 4 0.17% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 2414 # Writes before turning the bus around for reads -system.physmem.totQLat 345783645500 # Total ticks spent queuing -system.physmem.totMemAccLat 597905520500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 67232500000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25715.51 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 2416 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 2416 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.258692 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.106432 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.116221 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::1 1 0.04% 0.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::2 2 0.08% 0.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::3 2 0.08% 0.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4 1 0.04% 0.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::5 1 0.04% 0.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::7 1 0.04% 0.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::9 1 0.04% 0.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::11 2 0.08% 0.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::15 5 0.21% 0.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 486 20.12% 20.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 13 0.54% 21.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 855 35.39% 56.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 862 35.68% 92.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 56 2.32% 94.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 20 0.83% 95.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 20 0.83% 96.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 33 1.37% 97.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 16 0.66% 98.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 6 0.25% 98.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 6 0.25% 98.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 4 0.17% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 7 0.29% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 6 0.25% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 4 0.17% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 4 0.17% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 2 0.08% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 2416 # Writes before turning the bus around for reads +system.physmem.totQLat 346456254750 # Total ticks spent queuing +system.physmem.totMemAccLat 598546442250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 67224050000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25768.77 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44465.51 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 358.00 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 44518.77 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 357.95 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.17 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 45.58 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 1.17 # Average system write bandwidth in MiByte/s @@ -306,18 +307,18 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 2.81 # Data bus utilization in percentage system.physmem.busUtilRead 2.80 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 7.51 # Average read queue length when enqueuing -system.physmem.avgWrQLen 4.43 # Average write queue length when enqueuing -system.physmem.readRowHits 12586631 # Number of row buffer hits during reads -system.physmem.writeRowHits 37847 # Number of row buffer hits during writes +system.physmem.avgRdQLen 8.26 # Average read queue length when enqueuing +system.physmem.avgWrQLen 5.37 # Average write queue length when enqueuing +system.physmem.readRowHits 12585053 # Number of row buffer hits during reads +system.physmem.writeRowHits 37880 # Number of row buffer hits during writes system.physmem.readRowHitRate 93.61 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 85.95 # Row buffer hit rate for writes -system.physmem.avgGap 172952.67 # Average gap between requests +system.physmem.writeRowHitRate 85.81 # Row buffer hit rate for writes +system.physmem.avgGap 172972.67 # Average gap between requests system.physmem.pageHitRate 93.58 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2167477603250 # Time in different power states -system.physmem.memoryStateTime::REF 80269800000 # Time in different power states +system.physmem.memoryStateTime::IDLE 2167576169750 # Time in different power states +system.physmem.memoryStateTime::REF 80270060000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 156101819250 # Time in different power states +system.physmem.memoryStateTime::ACT 156010779000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory @@ -331,322 +332,322 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 8 system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 55667977 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 13781620 # Transaction distribution -system.membus.trans_dist::ReadResp 13781620 # Transaction distribution -system.membus.trans_dist::WriteReq 432153 # Transaction distribution -system.membus.trans_dist::WriteResp 432153 # Transaction distribution -system.membus.trans_dist::Writeback 17099 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2365 # Transaction distribution -system.membus.trans_dist::UpgradeResp 2365 # Transaction distribution -system.membus.trans_dist::ReadExReq 28041 # Transaction distribution -system.membus.trans_dist::ReadExResp 28041 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 731786 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 214 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 951729 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1683729 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 26821728 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 26821728 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 28505457 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 735662 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 428 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 5092356 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 5828446 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 107286912 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 107286912 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 113115358 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 133817603 # Total data (bytes) +system.membus.throughput 55668579 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 13780402 # Transaction distribution +system.membus.trans_dist::ReadResp 13780402 # Transaction distribution +system.membus.trans_dist::WriteReq 432242 # Transaction distribution +system.membus.trans_dist::WriteResp 432242 # Transaction distribution +system.membus.trans_dist::Writeback 17197 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2368 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2368 # Transaction distribution +system.membus.trans_dist::ReadExReq 28083 # Transaction distribution +system.membus.trans_dist::ReadExResp 28083 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 732930 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 220 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 952061 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1685211 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 26818176 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 26818176 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 28503387 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 736825 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 440 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 5104244 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 5841509 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 107272704 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 107272704 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 113114213 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 133819459 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 416874000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 417666500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 199500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 209500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 14576510500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 14570118500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 1596663785 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1595700088 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 33229062000 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 33207877250 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.4 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 63248 # number of replacements -system.l2c.tags.tagsinuse 50398.234461 # Cycle average of tags in use -system.l2c.tags.total_refs 1749256 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 128641 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.597966 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2375562300000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 36845.662788 # Average occupied blocks per requestor +system.l2c.tags.replacements 63255 # number of replacements +system.l2c.tags.tagsinuse 50395.732810 # Cycle average of tags in use +system.l2c.tags.total_refs 1749595 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 128654 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.599227 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2375537274500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 36859.250431 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000018 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000124 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5231.089770 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3832.891832 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.993317 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 496.025776 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 690.296020 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 8.797358 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1694.464698 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 1598.012760 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.562220 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.inst 5225.740605 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3831.207928 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.993318 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 514.351835 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 694.414886 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 10.820575 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1674.526375 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 1584.426715 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.562428 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.079820 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.058485 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.079738 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.058460 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.007569 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.010533 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000134 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.025855 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.024384 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.769016 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65389 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 340 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2635 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6488 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55889 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.997757 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 17683113 # Number of tag accesses -system.l2c.tags.data_accesses 17683113 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 8690 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3137 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 468117 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 177120 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 2623 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1184 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 129717 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 64377 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 18993 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 4195 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 281260 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 131724 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1291137 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 597632 # number of Writeback hits -system.l2c.Writeback_hits::total 597632 # number of Writeback hits +system.l2c.tags.occ_percent::cpu1.inst 0.007848 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.010596 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000165 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.025551 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.024176 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.768978 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65393 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 343 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2636 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6462 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 55911 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.997818 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 17684075 # Number of tag accesses +system.l2c.tags.data_accesses 17684075 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 8753 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 3188 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 465928 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 176871 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 2616 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 1178 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 130375 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 64441 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 18901 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 4190 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 282805 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 131860 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1291106 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 597736 # number of Writeback hits +system.l2c.Writeback_hits::total 597736 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 14 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 4 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu2.data 12 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 30 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu2.data 4 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 4 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 62001 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 18409 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 33201 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 113611 # number of ReadExReq hits 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overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 61167.555826 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -799,52 +800,52 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 58808825 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 1019736 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 1019735 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 432153 # Transaction distribution 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-system.toL2Bus.reqLayer0.occupancy 2176624753 # Layer occupancy (ticks) +system.toL2Bus.throughput 58812389 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 1022771 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 1022770 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 432242 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 432242 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 265826 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 1511 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 3 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1514 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 80908 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 80908 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 834992 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2422460 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 15408 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 52756 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 3325616 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 26696960 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 37444261 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 21472 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 86120 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 64248813 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 141273763 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 102976 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 2181217728 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1870991697 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1881226404 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1845922726 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1849082178 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 10050964 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 10054967 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 31304739 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 31351984 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48758959 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 13773981 # Transaction distribution -system.iobus.trans_dist::ReadResp 13773981 # Transaction distribution -system.iobus.trans_dist::WriteReq 2776 # Transaction distribution -system.iobus.trans_dist::WriteResp 2776 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 11410 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 3028 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 18 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 254 # Packet count per connected master and slave (bytes) +system.iobus.throughput 48758810 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 13772718 # Transaction distribution +system.iobus.trans_dist::ReadResp 13772718 # Transaction distribution +system.iobus.trans_dist::WriteReq 2835 # Transaction distribution +system.iobus.trans_dist::WriteResp 2835 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 11646 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 3040 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 258 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 716788 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 717678 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -860,18 +861,18 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 731786 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 26821728 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::total 26821728 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 27553514 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 15374 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 6056 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 36 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 508 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 732930 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 26818176 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 26818176 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 27551106 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 15610 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 6080 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 516 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 713112 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 714003 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -887,18 +888,18 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 735662 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 107286912 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::total 107286912 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 108022574 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 736825 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 107272704 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::total 107272704 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 108009529 # Cumulative packet size per connected master and slave (bytes) system.iobus.data_through_bus 117209343 # Total data (bytes) -system.iobus.reqLayer0.occupancy 7968000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 8145000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 1514000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 1520000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 18000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 20000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 127000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 129000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -906,7 +907,7 @@ system.iobus.reqLayer5.occupancy 8000 # La system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 358898000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 359342000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) @@ -938,11 +939,11 @@ system.iobus.reqLayer22.occupancy 8000 # La system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 13410864000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 13409088000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 729010000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 730095000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 33767373000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 33780437750 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.4 # Layer utilization (%) system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -967,25 +968,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7995700 # DTB read hits -system.cpu0.dtb.read_misses 6195 # DTB read misses -system.cpu0.dtb.write_hits 6594454 # DTB write hits -system.cpu0.dtb.write_misses 1984 # DTB write misses +system.cpu0.dtb.read_hits 7992228 # DTB read hits +system.cpu0.dtb.read_misses 6211 # DTB read misses +system.cpu0.dtb.write_hits 6585208 # DTB write hits +system.cpu0.dtb.write_misses 1983 # DTB write misses system.cpu0.dtb.flush_tlb 556 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 675 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 676 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5669 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 5702 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 121 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 117 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 209 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 8001895 # DTB read accesses -system.cpu0.dtb.write_accesses 6596438 # DTB write accesses +system.cpu0.dtb.perms_faults 210 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 7998439 # DTB read accesses +system.cpu0.dtb.write_accesses 6587191 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14590154 # DTB hits -system.cpu0.dtb.misses 8179 # DTB misses -system.cpu0.dtb.accesses 14598333 # DTB accesses +system.cpu0.dtb.hits 14577436 # DTB hits +system.cpu0.dtb.misses 8194 # DTB misses +system.cpu0.dtb.accesses 14585630 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1007,468 +1008,468 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 32327896 # ITB inst hits -system.cpu0.itb.inst_misses 3449 # ITB inst misses +system.cpu0.itb.inst_hits 32348466 # ITB inst hits +system.cpu0.itb.inst_misses 3468 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 556 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 675 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 676 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2626 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2648 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 32331345 # ITB inst accesses -system.cpu0.itb.hits 32327896 # DTB hits -system.cpu0.itb.misses 3449 # DTB misses -system.cpu0.itb.accesses 32331345 # DTB accesses -system.cpu0.numCycles 113683212 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 32351934 # ITB inst accesses +system.cpu0.itb.hits 32348466 # DTB hits +system.cpu0.itb.misses 3468 # DTB misses +system.cpu0.itb.accesses 32351934 # DTB accesses +system.cpu0.numCycles 113676157 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 31852389 # Number of instructions committed -system.cpu0.committedOps 42022034 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 37405417 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 4937 # Number of float alu accesses -system.cpu0.num_func_calls 1199046 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4246321 # number of instructions that are conditional controls -system.cpu0.num_int_insts 37405417 # number of integer instructions -system.cpu0.num_fp_insts 4937 # number of float instructions -system.cpu0.num_int_register_reads 193890675 # number of times the integer registers were read -system.cpu0.num_int_register_writes 39514617 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3572 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1366 # number of times the floating registers were written -system.cpu0.num_mem_refs 15257672 # number of memory refs -system.cpu0.num_load_insts 8364380 # Number of load instructions -system.cpu0.num_store_insts 6893292 # Number of store instructions -system.cpu0.num_idle_cycles 110986808.765580 # Number of idle cycles -system.cpu0.num_busy_cycles 2696403.234420 # Number of busy cycles -system.cpu0.not_idle_fraction 0.023719 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.976281 # Percentage of idle cycles -system.cpu0.Branches 5614656 # Number of branches fetched -system.cpu0.op_class::No_OpClass 14792 0.04% 0.04% # Class of executed instruction -system.cpu0.op_class::IntAlu 26773719 63.60% 63.63% # Class of executed instruction -system.cpu0.op_class::IntMult 49650 0.12% 63.75% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 63.75% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 63.75% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 63.75% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 63.75% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 63.75% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 63.75% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 63.75% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 63.75% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 63.75% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 63.75% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 63.75% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 63.75% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 63.75% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 63.75% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 63.75% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 63.75% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 63.75% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 63.75% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 63.75% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 63.75% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 63.75% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 63.75% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 63.75% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 1431 0.00% 63.76% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 63.76% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 63.76% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 63.76% # Class of executed instruction -system.cpu0.op_class::MemRead 8364380 19.87% 83.63% # Class of executed instruction -system.cpu0.op_class::MemWrite 6893292 16.37% 100.00% # Class of executed instruction +system.cpu0.committedInsts 31863567 # Number of instructions committed +system.cpu0.committedOps 42010857 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 37388293 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5018 # Number of float alu accesses +system.cpu0.num_func_calls 1197302 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4248978 # number of instructions that are conditional controls +system.cpu0.num_int_insts 37388293 # number of integer instructions +system.cpu0.num_fp_insts 5018 # number of float instructions +system.cpu0.num_int_register_reads 193803982 # number of times the integer registers were read +system.cpu0.num_int_register_writes 39520708 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3589 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1430 # number of times the floating registers were written +system.cpu0.num_mem_refs 15242780 # number of memory refs +system.cpu0.num_load_insts 8359522 # Number of load instructions +system.cpu0.num_store_insts 6883258 # Number of store instructions +system.cpu0.num_idle_cycles 110978931.176812 # Number of idle cycles +system.cpu0.num_busy_cycles 2697225.823188 # Number of busy cycles +system.cpu0.not_idle_fraction 0.023727 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.976273 # Percentage of idle cycles +system.cpu0.Branches 5616963 # Number of branches fetched +system.cpu0.op_class::No_OpClass 14526 0.03% 0.03% # Class of executed instruction +system.cpu0.op_class::IntAlu 26777156 63.63% 63.66% # Class of executed instruction +system.cpu0.op_class::IntMult 49712 0.12% 63.78% # Class of executed instruction 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-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015992 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.070222 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.009323 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015992 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.070222 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.009323 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11491.722208 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11899.699179 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11771.113748 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11491.722208 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11899.699179 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11771.113748 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11491.722208 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11899.699179 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11771.113748 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 24233 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 24233 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 24233 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 24233 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 24233 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 24233 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 131660 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 286192 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 417852 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 131660 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 286192 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 417852 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 131660 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 286192 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 417852 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1513402000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3408270326 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4921672326 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1513402000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3408270326 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4921672326 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1513402000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3408270326 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4921672326 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016104 # mshr miss rate for ReadReq accesses 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miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11778.506088 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11494.774419 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11909.034236 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11778.506088 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11494.774419 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11909.034236 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11778.506088 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 629833 # number of replacements +system.cpu0.dcache.tags.replacements 629808 # number of replacements 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(read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 92428 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 880124 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1317553 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 345001 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 92428 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 880124 # number of overall misses -system.cpu0.dcache.overall_misses::total 1317553 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 907525000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 3898427279 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 4805952279 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 994225242 # number of WriteReq miss cycles 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(read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 1901750242 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 26837319822 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 28739070064 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7041893 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 1882871 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 4912422 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 13837186 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 6130929 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 1342989 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 2742531 # number of WriteReq accesses(hits+misses) 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accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 1347503 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu2.data 2746857 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 10216447 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 137939 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 34940 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 77235 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 250114 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 137939 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 34940 # number of StoreCondReq accesses(hits+misses) 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-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.025152 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033859 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.055059 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.036954 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027383 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.021352 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.222295 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.078913 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.046768 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.050186 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.048312 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.047719 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000054 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000016 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026190 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.028652 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.114974 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.054776 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026190 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.028652 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.114974 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.054776 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14235.239679 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14413.316175 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 9398.667588 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 34670.987655 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 37626.330752 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 29685.996789 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13127.723624 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13383.243432 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 6098.345729 # average LoadLockedReq miss latency +system.cpu0.dcache.demand_accesses::cpu0.data 13161361 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 3231246 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu2.data 7662056 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 24054663 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13161361 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 3231246 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 7662056 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 24054663 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.025127 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033885 # miss rate for ReadReq accesses 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miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14344.630809 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 9411.746670 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 34403.844157 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 35979.788375 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 28488.347401 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13120.391705 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13425.292177 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 6128.483388 # average LoadLockedReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13000 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 20575.477583 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 30492.657651 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 21812.458447 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 20575.477583 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 30492.657651 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 21812.458447 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 8069 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 3116 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 905 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 48 # number of cycles access was blocked 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LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 57799752 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 44000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 44000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1714080758 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3543058359 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 5257139117 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1714080758 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3543058359 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 5257139117 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27392049000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 28579464500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 55971513500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1440396400 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 13339396963 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 14779793363 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28832445400 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 41918861463 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 70751306863 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033859 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.026666 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014074 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021352 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019443 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008026 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050186 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.043054 # mshr miss rate for LoadLockedReq accesses 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number of writebacks +system.cpu0.dcache.writebacks::total 597736 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 143982 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 143982 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 560780 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 560780 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 407 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 407 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 704762 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 704762 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 704762 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 704762 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 63831 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 131106 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 194937 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 28888 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 53486 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 82374 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1736 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 3351 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 5087 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 3 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 3 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 92719 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 184592 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 277311 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 92719 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 184592 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 277311 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 780623750 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1700229865 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2480853615 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 933509750 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 1853484745 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2786994495 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 19304000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 38850752 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 58154752 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 33000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 33000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1714133500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3553714610 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 5267848110 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1714133500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3553714610 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 5267848110 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27350994000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 28703901500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 56054895500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1444132955 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 13356723550 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 14800856505 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28795126955 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 42060625050 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 70855752005 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033885 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.026674 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014087 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021438 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019472 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008063 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.049685 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.043387 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020339 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000040 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000012 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028695 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.024092 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.011528 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028695 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.024092 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.011528 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12229.539722 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12968.360449 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12726.437849 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32314.793340 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 34653.642916 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33833.424321 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11119.815668 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11593.778574 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11432.033025 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18545.037846 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19222.738986 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18996.397815 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18545.037846 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19222.738986 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18996.397815 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18487.402798 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19251.726023 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18996.174367 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18487.402798 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19251.726023 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18996.174367 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1502,25 +1503,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 2096038 # DTB read hits -system.cpu1.dtb.read_misses 2089 # DTB read misses -system.cpu1.dtb.write_hits 1418402 # DTB write hits -system.cpu1.dtb.write_misses 376 # DTB write misses +system.cpu1.dtb.read_hits 2096820 # DTB read hits +system.cpu1.dtb.read_misses 2107 # DTB read misses +system.cpu1.dtb.write_hits 1423125 # DTB write hits +system.cpu1.dtb.write_misses 370 # DTB write misses system.cpu1.dtb.flush_tlb 554 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 221 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 233 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1770 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1777 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.dtb.prefetch_faults 37 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 79 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 2098127 # DTB read accesses -system.cpu1.dtb.write_accesses 1418778 # DTB write accesses +system.cpu1.dtb.perms_faults 78 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 2098927 # DTB read accesses +system.cpu1.dtb.write_accesses 1423495 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 3514440 # DTB hits -system.cpu1.dtb.misses 2465 # DTB misses -system.cpu1.dtb.accesses 3516905 # DTB accesses +system.cpu1.dtb.hits 3519945 # DTB hits +system.cpu1.dtb.misses 2477 # DTB misses +system.cpu1.dtb.accesses 3522422 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1542,96 +1543,96 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 8190394 # ITB inst hits -system.cpu1.itb.inst_misses 1200 # ITB inst misses +system.cpu1.itb.inst_hits 8175454 # ITB inst hits +system.cpu1.itb.inst_misses 1196 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 554 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 221 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 233 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 949 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 946 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8191594 # ITB inst accesses -system.cpu1.itb.hits 8190394 # DTB hits -system.cpu1.itb.misses 1200 # DTB misses -system.cpu1.itb.accesses 8191594 # DTB accesses -system.cpu1.numCycles 584767176 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 8176650 # ITB inst accesses +system.cpu1.itb.hits 8175454 # DTB hits +system.cpu1.itb.misses 1196 # DTB misses +system.cpu1.itb.accesses 8176650 # DTB accesses +system.cpu1.numCycles 584791217 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7979697 # Number of instructions committed -system.cpu1.committedOps 10128513 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 9101420 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 2019 # Number of float alu accesses -system.cpu1.num_func_calls 304592 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1114093 # number of instructions that are conditional controls -system.cpu1.num_int_insts 9101420 # number of integer instructions -system.cpu1.num_fp_insts 2019 # number of float instructions -system.cpu1.num_int_register_reads 53054873 # number of times the integer registers were read -system.cpu1.num_int_register_writes 9892627 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 1441 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 580 # number of times the floating registers were written -system.cpu1.num_mem_refs 3681879 # number of memory refs -system.cpu1.num_load_insts 2189240 # Number of load instructions -system.cpu1.num_store_insts 1492639 # Number of store instructions -system.cpu1.num_idle_cycles 548440957.661697 # Number of idle cycles -system.cpu1.num_busy_cycles 36326218.338303 # Number of busy cycles -system.cpu1.not_idle_fraction 0.062121 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.937879 # Percentage of idle cycles -system.cpu1.Branches 1446987 # Number of branches fetched -system.cpu1.op_class::No_OpClass 5386 0.05% 0.05% # Class of executed instruction -system.cpu1.op_class::IntAlu 6616988 64.14% 64.19% # Class of executed instruction -system.cpu1.op_class::IntMult 11601 0.11% 64.31% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 298 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::MemRead 2189240 21.22% 85.53% # Class of executed instruction -system.cpu1.op_class::MemWrite 1492639 14.47% 100.00% # Class of executed instruction +system.cpu1.committedInsts 7972563 # Number of instructions committed +system.cpu1.committedOps 10134873 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 9111769 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 2002 # Number of float alu accesses +system.cpu1.num_func_calls 305506 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1114419 # number of instructions that are conditional controls +system.cpu1.num_int_insts 9111769 # number of integer instructions +system.cpu1.num_fp_insts 2002 # number of float instructions +system.cpu1.num_int_register_reads 53111503 # number of times the integer registers were read +system.cpu1.num_int_register_writes 9891567 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 1488 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written +system.cpu1.num_mem_refs 3688880 # number of memory refs +system.cpu1.num_load_insts 2190803 # Number of load instructions +system.cpu1.num_store_insts 1498077 # Number of store instructions +system.cpu1.num_idle_cycles 549443201.253140 # Number of idle cycles +system.cpu1.num_busy_cycles 35348015.746859 # Number of busy cycles +system.cpu1.not_idle_fraction 0.060446 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.939554 # Percentage of idle cycles +system.cpu1.Branches 1447411 # Number of branches fetched +system.cpu1.op_class::No_OpClass 5397 0.05% 0.05% # Class of executed instruction +system.cpu1.op_class::IntAlu 6618001 64.10% 64.15% # Class of executed instruction +system.cpu1.op_class::IntMult 11557 0.11% 64.27% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 298 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::MemRead 2190803 21.22% 85.49% # Class of executed instruction +system.cpu1.op_class::MemWrite 1498077 14.51% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 10316152 # Class of executed instruction +system.cpu1.op_class::total 10324133 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 4788852 # Number of BP lookups -system.cpu2.branchPred.condPredicted 3906949 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 223643 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 3181584 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 2530711 # Number of BTB hits +system.cpu2.branchPred.lookups 4844951 # Number of BP lookups +system.cpu2.branchPred.condPredicted 3958364 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 223288 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 3209464 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 2561917 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 79.542486 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 413887 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 21714 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 79.823827 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 415777 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 21493 # Number of incorrect RAS predictions. system.cpu2.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu2.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu2.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1655,25 +1656,25 @@ system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 10930564 # DTB read hits -system.cpu2.dtb.read_misses 23215 # DTB read misses -system.cpu2.dtb.write_hits 3350483 # DTB write hits -system.cpu2.dtb.write_misses 6482 # DTB write misses +system.cpu2.dtb.read_hits 10946099 # DTB read hits +system.cpu2.dtb.read_misses 23259 # DTB read misses +system.cpu2.dtb.write_hits 3358425 # DTB write hits +system.cpu2.dtb.write_misses 6569 # DTB write misses system.cpu2.dtb.flush_tlb 552 # Number of times complete TLB was flushed system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.dtb.flush_tlb_mva_asid 543 # Number of times TLB was flushed by MVA & ASID +system.cpu2.dtb.flush_tlb_mva_asid 530 # Number of times TLB was flushed by MVA & ASID system.cpu2.dtb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 2337 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 733 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 153 # Number of TLB faults due to prefetch +system.cpu2.dtb.flush_entries 2341 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 761 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 169 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 461 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 10953779 # DTB read accesses -system.cpu2.dtb.write_accesses 3356965 # DTB write accesses +system.cpu2.dtb.perms_faults 490 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 10969358 # DTB read accesses +system.cpu2.dtb.write_accesses 3364994 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 14281047 # DTB hits -system.cpu2.dtb.misses 29697 # DTB misses -system.cpu2.dtb.accesses 14310744 # DTB accesses +system.cpu2.dtb.hits 14304524 # DTB hits +system.cpu2.dtb.misses 29828 # DTB misses +system.cpu2.dtb.accesses 14334352 # DTB accesses system.cpu2.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu2.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu2.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1695,328 +1696,329 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.itb.inst_hits 4054306 # ITB inst hits -system.cpu2.itb.inst_misses 4589 # ITB inst misses +system.cpu2.itb.inst_hits 4066170 # ITB inst hits +system.cpu2.itb.inst_misses 4558 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses system.cpu2.itb.flush_tlb 552 # Number of times complete TLB was flushed system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.itb.flush_tlb_mva_asid 543 # Number of times TLB was flushed by MVA & ASID +system.cpu2.itb.flush_tlb_mva_asid 530 # Number of times TLB was flushed by MVA & ASID system.cpu2.itb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 1707 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_entries 1650 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 958 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 1020 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 4058895 # ITB inst accesses -system.cpu2.itb.hits 4054306 # DTB hits -system.cpu2.itb.misses 4589 # DTB misses -system.cpu2.itb.accesses 4058895 # DTB accesses -system.cpu2.numCycles 88316329 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 4070728 # ITB inst accesses +system.cpu2.itb.hits 4066170 # DTB hits +system.cpu2.itb.misses 4558 # DTB misses +system.cpu2.itb.accesses 4070728 # DTB accesses +system.cpu2.numCycles 88357644 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9351504 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 32524106 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 4788852 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 2944598 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 6861719 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 1761177 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 50498 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.BlockedCycles 19190819 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 265 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 860 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 33145 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 719724 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 402 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 4052907 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 289738 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 2002 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 37419321 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.044533 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.431855 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9387256 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 32765333 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 4844951 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 2977694 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 6914165 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 1793026 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 51157 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.BlockedCycles 18399919 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 356 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 937 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 34522 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 732881 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 499 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 4064781 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 291170 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 1939 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 36763653 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.071353 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.456601 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 30562706 81.68% 81.68% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 385991 1.03% 82.71% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 516133 1.38% 84.09% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 820285 2.19% 86.28% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 630351 1.68% 87.96% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 341631 0.91% 88.88% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1045289 2.79% 91.67% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 230176 0.62% 92.29% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 2886759 7.71% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 29854695 81.21% 81.21% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 388351 1.06% 82.26% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 517738 1.41% 83.67% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 822514 2.24% 85.91% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 639820 1.74% 87.65% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 344469 0.94% 88.59% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1061447 2.89% 91.47% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 231777 0.63% 92.10% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 2902842 7.90% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 37419321 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.054224 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.368268 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 9979534 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 19757337 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 6196813 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 326068 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1158658 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 609699 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 52950 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 36983425 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 178083 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 1158658 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 10528432 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 6814826 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 11435729 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 5959486 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 1521262 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 34891179 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 96 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 325442 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 887620 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.FullRegisterEvents 163 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 37432161 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 161024301 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 148452649 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 3370 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 26548024 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 10884136 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 285664 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 261962 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3325772 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6628163 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3904378 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 525369 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 781342 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 32207136 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 505175 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 34773283 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 55288 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 7195240 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 19128466 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 148705 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 37419321 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 0.929287 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.589860 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 36763653 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.054833 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.370826 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 9873812 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 19124591 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 6319657 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 254865 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1189808 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 613364 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 53448 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 37275302 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 179889 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 1189808 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 10379118 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 2802247 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 11780210 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 6098002 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 4513356 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 35160533 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 386 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 2869122 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 3154793 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 689173 # Number of times rename has blocked due to SQ full +system.cpu2.rename.FullRegisterEvents 383 # Number of times there has been no free registers +system.cpu2.rename.RenamedOperands 37744497 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 162187083 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 149521715 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 3412 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 26544575 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 11199921 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 286052 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 262435 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 2598030 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6687505 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3927813 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 542106 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 758032 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 32441943 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 511673 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 34839204 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 63540 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 7431415 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 19915523 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 154345 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 36763653 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 0.947653 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.617979 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 24716493 66.05% 66.05% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 3990546 10.66% 76.72% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 2313548 6.18% 82.90% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 1974351 5.28% 88.18% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 2779950 7.43% 95.61% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 967650 2.59% 98.19% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 497474 1.33% 99.52% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 144778 0.39% 99.91% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 34531 0.09% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 24294475 66.08% 66.08% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 3786923 10.30% 76.38% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 2217252 6.03% 82.41% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 1918473 5.22% 87.63% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 2844306 7.74% 95.37% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 967223 2.63% 98.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 535277 1.46% 99.46% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 160435 0.44% 99.89% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 39289 0.11% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 37419321 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 36763653 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 19609 1.29% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 1 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 1392955 91.52% 92.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 109452 7.19% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 19487 1.25% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 1 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 1415927 90.74% 91.99% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 124952 8.01% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 8340 0.02% 0.02% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 19803061 56.95% 56.97% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 28127 0.08% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 3 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 3 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 386 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 8595 0.02% 0.02% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 19842102 56.95% 56.98% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 28105 0.08% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 10 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 10 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 382 0.00% 57.06% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 10 0.00% 57.06% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 11414599 32.83% 89.88% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3518761 10.12% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 11432468 32.81% 89.87% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3527522 10.13% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 34773283 # Type of FU issued -system.cpu2.iq.rate 0.393736 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 1522017 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.043770 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 108565265 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 39912731 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 28072202 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 7477 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 4009 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 3345 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 36282976 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 3984 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 206198 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 34839204 # Type of FU issued +system.cpu2.iq.rate 0.394298 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 1560367 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.044788 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 108088247 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 40390587 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 28132113 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 7428 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 3949 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 3288 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 36387010 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 3966 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 216264 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1536367 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 2104 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 9509 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 563915 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1592400 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1668 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 9845 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 582754 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 5287425 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 344896 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 5289504 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 343573 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1158658 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 5187034 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 87972 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 32794480 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 61964 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6628163 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3904378 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 362952 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 29501 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 2651 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 9509 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 107755 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 89629 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 197384 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 33857007 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 11143266 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 916276 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 1189808 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 2192287 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 292580 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 33037931 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 55534 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6687505 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3927813 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 368987 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 60475 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 207427 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 9845 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 107337 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 89487 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 196824 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 33922204 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 11159492 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 917000 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 82169 # number of nop insts executed -system.cpu2.iew.exec_refs 14628489 # number of memory reference insts executed -system.cpu2.iew.exec_branches 3765120 # Number of branches executed -system.cpu2.iew.exec_stores 3485223 # Number of stores executed -system.cpu2.iew.exec_rate 0.383361 # Inst execution rate -system.cpu2.iew.wb_sent 33455826 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 28075547 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 16112995 # num instructions producing a value -system.cpu2.iew.wb_consumers 29113416 # num instructions consuming a value +system.cpu2.iew.exec_nop 84315 # number of nop insts executed +system.cpu2.iew.exec_refs 14652861 # number of memory reference insts executed +system.cpu2.iew.exec_branches 3774133 # Number of branches executed +system.cpu2.iew.exec_stores 3493369 # Number of stores executed +system.cpu2.iew.exec_rate 0.383919 # Inst execution rate +system.cpu2.iew.wb_sent 33519345 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 28135401 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 16326972 # num instructions producing a value +system.cpu2.iew.wb_consumers 29693548 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.317898 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.553456 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.318426 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.549849 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 7147493 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 356470 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 171471 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 36260461 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 0.700277 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.736744 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 7376982 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 357328 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 170683 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 35573653 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 0.713892 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.756913 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 27338017 75.39% 75.39% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4438533 12.24% 87.63% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1258858 3.47% 91.11% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 640995 1.77% 92.87% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 514559 1.42% 94.29% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 318215 0.88% 95.17% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 418287 1.15% 96.32% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 309870 0.85% 97.18% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1023127 2.82% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 26733174 75.15% 75.15% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4358118 12.25% 87.40% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1232607 3.46% 90.86% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 662996 1.86% 92.73% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 505200 1.42% 94.15% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 312825 0.88% 95.03% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 424269 1.19% 96.22% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 302810 0.85% 97.07% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1041654 2.93% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 36260461 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 20554943 # Number of instructions committed -system.cpu2.commit.committedOps 25392373 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 35573653 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 20550287 # Number of instructions committed +system.cpu2.commit.committedOps 25395761 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8432259 # Number of memory references committed -system.cpu2.commit.loads 5091796 # Number of loads committed -system.cpu2.commit.membars 94283 # Number of memory barriers committed -system.cpu2.commit.branches 3240263 # Number of branches committed -system.cpu2.commit.fp_insts 3299 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 22648524 # Number of committed integer instructions. -system.cpu2.commit.function_calls 295510 # Number of function calls committed. +system.cpu2.commit.refs 8440164 # Number of memory references committed +system.cpu2.commit.loads 5095105 # Number of loads committed +system.cpu2.commit.membars 94591 # Number of memory barriers committed +system.cpu2.commit.branches 3237542 # Number of branches committed +system.cpu2.commit.fp_insts 3235 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 22655353 # Number of committed integer instructions. +system.cpu2.commit.function_calls 295831 # Number of function calls committed. system.cpu2.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 16933133 66.69% 66.69% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 26595 0.10% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 386 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 5091796 20.05% 86.84% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 3340463 13.16% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 16928638 66.66% 66.66% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 26577 0.10% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 382 0.00% 66.77% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 66.77% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.77% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.77% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 5095105 20.06% 86.83% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 3345059 13.17% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 25392373 # Class of committed instruction -system.cpu2.commit.bw_lim_events 1023127 # number cycles where commit BW limit reached +system.cpu2.commit.op_class_0::total 25395761 # Class of committed instruction +system.cpu2.commit.bw_lim_events 1041654 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 67255841 # The number of ROB reads -system.cpu2.rob.rob_writes 66282532 # The number of ROB writes -system.cpu2.timesIdled 358696 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 50897008 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 3546076715 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 20499567 # Number of Instructions Simulated -system.cpu2.committedOps 25336997 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 4.308205 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 4.308205 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.232115 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.232115 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 157113831 # number of integer regfile reads -system.cpu2.int_regfile_writes 29893796 # number of integer regfile writes -system.cpu2.fp_regfile_reads 46822 # number of floating regfile reads -system.cpu2.fp_regfile_writes 45178 # number of floating regfile writes -system.cpu2.misc_regfile_reads 67223937 # number of misc regfile reads -system.cpu2.misc_regfile_writes 297064 # number of misc regfile writes +system.cpu2.rob.rob_reads 66778885 # The number of ROB reads +system.cpu2.rob.rob_writes 66779605 # The number of ROB writes +system.cpu2.timesIdled 362907 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 51593991 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 3545947336 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 20495032 # Number of Instructions Simulated +system.cpu2.committedOps 25340506 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 4.311174 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 4.311174 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.231955 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.231955 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 157422880 # number of integer regfile reads +system.cpu2.int_regfile_writes 29963931 # number of integer regfile writes +system.cpu2.fp_regfile_reads 46839 # number of floating regfile reads +system.cpu2.fp_regfile_writes 45210 # number of floating regfile writes +system.cpu2.misc_regfile_reads 66597785 # number of misc regfile reads +system.cpu2.misc_regfile_writes 297300 # number of misc regfile writes system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. @@ -2033,10 +2035,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1535534030000 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1535534030000 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1535534030000 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1535534030000 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1536043103750 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1536043103750 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1536043103750 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1536043103750 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/system.terminal Binary files differindex aaf6d88fc..f40477dbc 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/system.terminal diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini index 789fa7ff8..da5ad247a 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini @@ -12,8 +12,8 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=256 -boot_loader=/dist/binaries/boot.arm -boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +boot_loader=/home/stever/m5/m5_system_2.0b3/binaries/boot.arm +boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain @@ -30,7 +30,7 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 load_offset=0 machine_type=RealView_PBX @@ -42,7 +42,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=tests/halt.sh +readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -85,7 +85,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/disks/linux-arm-ael.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-arm-ael.img read_only=true [system.clk_domain] @@ -172,6 +172,7 @@ smtLSQThreshold=100 smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 +socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false @@ -775,6 +776,7 @@ smtLSQThreshold=100 smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 +socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=true @@ -1343,9 +1345,9 @@ warn_access=warn pio=system.membus.default [system.physmem] -type=SimpleDRAM +type=DRAMCtrl activation_limit=4 -addr_mapping=RaBaChCo +addr_mapping=RoRaBaChCo banks_per_rank=8 burst_length=8 channels=1 @@ -1356,27 +1358,33 @@ device_rowbuffer_size=1024 devices_per_rank=8 eventq_index=0 in_addr_map=true +max_accesses_per_row=16 mem_sched_policy=frfcfs +min_writes_per_switch=16 null=false -page_policy=open +page_policy=open_adaptive range=0:134217727 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 +tCK=1250 tCL=13750 tRAS=35000 tRCD=13750 tREFI=7800000 -tRFC=300000 +tRFC=260000 tRP=13750 -tRRD=6250 +tRRD=6000 +tRTP=7500 +tRTW=2500 +tWR=15000 tWTR=7500 -tXAW=40000 -write_buffer_size=32 -write_high_thresh_perc=70 -write_low_thresh_perc=0 +tXAW=30000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 port=system.membus.master[6] [system.realview] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout index f047a9e04..74b77ce44 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2014 12:08:08 -gem5 started Jan 23 2014 19:10:32 -gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 +gem5 compiled Jun 21 2014 11:22:42 +gem5 started Jun 21 2014 21:27:42 +gem5 executing on phenom +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 Global frequency set at 1000000000000 ticks per second - 0: system.cpu0.isa: ISA system set to: 0x6aaf400 0x6aaf400 - 0: system.cpu1.isa: ISA system set to: 0x6aaf400 0x6aaf400 + 0: system.cpu0.isa: ISA system set to: 0x60c5390 0x60c5390 + 0: system.cpu1.isa: ISA system set to: 0x60c5390 0x60c5390 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index bff238873..4b7f3d43e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -1,154 +1,154 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.550603 # Number of seconds simulated -sim_ticks 2550603285500 # Number of ticks simulated -final_tick 2550603285500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.550237 # Number of seconds simulated +sim_ticks 2550237191000 # Number of ticks simulated +final_tick 2550237191000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 56179 # Simulator instruction rate (inst/s) -host_op_rate 72287 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2375661490 # Simulator tick rate (ticks/s) -host_mem_usage 471120 # Number of bytes of host memory used -host_seconds 1073.64 # Real time elapsed on the host -sim_insts 60315997 # Number of instructions simulated -sim_ops 77609994 # Number of ops (including micro ops) simulated +host_inst_rate 66377 # Simulator instruction rate (inst/s) +host_op_rate 85409 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2806608319 # Simulator tick rate (ticks/s) +host_mem_usage 421988 # Number of bytes of host memory used +host_seconds 908.65 # Real time elapsed on the host +sim_insts 60314055 # Number of instructions simulated +sim_ops 77607027 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 1984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 487168 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5091220 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 768 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 310848 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4002308 # Number of bytes read from this memory -system.physmem.bytes_read::total 131004952 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 487168 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 310848 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 798016 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3785472 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1521388 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1494684 # Number of bytes written to this memory -system.physmem.bytes_written::total 6801544 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 2240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 507520 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5298200 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 704 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 292352 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 3795584 # Number of bytes read from this memory +system.physmem.bytes_read::total 131007192 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 507520 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 292352 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 799872 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3786240 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1521400 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1494672 # Number of bytes written to this memory +system.physmem.bytes_written::total 6802312 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 31 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 7612 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 79585 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 12 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 4857 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 62537 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15293452 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59148 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 380347 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 373671 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813166 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47483091 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 778 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 191001 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1996085 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 301 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 121872 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1569161 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51362340 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 191001 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 121872 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 312873 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1484148 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 596482 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 586012 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2666641 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1484148 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47483091 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 778 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 191001 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2592566 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 301 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 121872 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2155173 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54028981 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15293452 # Number of read requests accepted -system.physmem.writeReqs 813166 # Number of write requests accepted -system.physmem.readBursts 15293452 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 813166 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 977025792 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 1755136 # Total number of bytes read from write queue -system.physmem.bytesWritten 6829888 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 131004952 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6801544 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 27424 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 706426 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4680 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 955870 # Per bank write bursts -system.physmem.perBankRdBursts::1 953353 # Per bank write bursts -system.physmem.perBankRdBursts::2 953267 # Per bank write bursts -system.physmem.perBankRdBursts::3 953402 # Per bank write bursts -system.physmem.perBankRdBursts::4 955744 # Per bank write bursts -system.physmem.perBankRdBursts::5 953745 # Per bank write bursts -system.physmem.perBankRdBursts::6 953482 # Per bank write bursts -system.physmem.perBankRdBursts::7 953247 # Per bank write bursts -system.physmem.perBankRdBursts::8 956258 # Per bank write bursts -system.physmem.perBankRdBursts::9 953771 # Per bank write bursts -system.physmem.perBankRdBursts::10 953551 # Per bank write bursts -system.physmem.perBankRdBursts::11 953111 # Per bank write bursts -system.physmem.perBankRdBursts::12 956206 # Per bank write bursts -system.physmem.perBankRdBursts::13 953857 # Per bank write bursts -system.physmem.perBankRdBursts::14 953612 # Per bank write bursts -system.physmem.perBankRdBursts::15 953552 # Per bank write bursts -system.physmem.perBankWrBursts::0 6609 # Per bank write bursts -system.physmem.perBankWrBursts::1 6381 # Per bank write bursts -system.physmem.perBankWrBursts::2 6537 # Per bank write bursts -system.physmem.perBankWrBursts::3 6560 # Per bank write bursts -system.physmem.perBankWrBursts::4 6488 # Per bank write bursts +system.physmem.num_reads::cpu0.dtb.walker 35 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 7930 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 82820 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 11 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 4568 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 59306 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15293487 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59160 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 380350 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 373668 # Number of write requests responded to by this memory +system.physmem.num_writes::total 813178 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47489907 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 878 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 25 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 199009 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 2077532 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 276 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 114637 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1488326 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51370591 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 199009 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 114637 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 313646 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1484662 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 596572 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 586091 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2667325 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1484662 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47489907 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 878 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 199009 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2674104 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 276 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 114637 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2074417 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54037916 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15293487 # Number of read requests accepted +system.physmem.writeReqs 813178 # Number of write requests accepted +system.physmem.readBursts 15293487 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 813178 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 977052352 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 1730816 # Total number of bytes read from write queue +system.physmem.bytesWritten 6829312 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 131007192 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6802312 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 27044 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 706441 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4687 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 955866 # Per bank write bursts +system.physmem.perBankRdBursts::1 953274 # Per bank write bursts +system.physmem.perBankRdBursts::2 953247 # Per bank write bursts +system.physmem.perBankRdBursts::3 953514 # Per bank write bursts +system.physmem.perBankRdBursts::4 955750 # Per bank write bursts +system.physmem.perBankRdBursts::5 953800 # Per bank write bursts +system.physmem.perBankRdBursts::6 953588 # Per bank write bursts +system.physmem.perBankRdBursts::7 953504 # Per bank write bursts +system.physmem.perBankRdBursts::8 956261 # Per bank write bursts +system.physmem.perBankRdBursts::9 953859 # Per bank write bursts +system.physmem.perBankRdBursts::10 953506 # Per bank write bursts +system.physmem.perBankRdBursts::11 952990 # Per bank write bursts +system.physmem.perBankRdBursts::12 956201 # Per bank write bursts +system.physmem.perBankRdBursts::13 953861 # Per bank write bursts +system.physmem.perBankRdBursts::14 953718 # Per bank write bursts +system.physmem.perBankRdBursts::15 953504 # Per bank write bursts +system.physmem.perBankWrBursts::0 6593 # Per bank write bursts +system.physmem.perBankWrBursts::1 6395 # Per bank write bursts +system.physmem.perBankWrBursts::2 6535 # Per bank write bursts +system.physmem.perBankWrBursts::3 6562 # Per bank write bursts +system.physmem.perBankWrBursts::4 6485 # Per bank write bursts system.physmem.perBankWrBursts::5 6754 # Per bank write bursts -system.physmem.perBankWrBursts::6 6745 # Per bank write bursts -system.physmem.perBankWrBursts::7 6685 # Per bank write bursts -system.physmem.perBankWrBursts::8 7023 # Per bank write bursts -system.physmem.perBankWrBursts::9 6801 # Per bank write bursts -system.physmem.perBankWrBursts::10 6470 # Per bank write bursts -system.physmem.perBankWrBursts::11 6120 # Per bank write bursts -system.physmem.perBankWrBursts::12 7060 # Per bank write bursts -system.physmem.perBankWrBursts::13 6677 # Per bank write bursts -system.physmem.perBankWrBursts::14 6963 # Per bank write bursts -system.physmem.perBankWrBursts::15 6844 # Per bank write bursts +system.physmem.perBankWrBursts::6 6752 # Per bank write bursts +system.physmem.perBankWrBursts::7 6692 # Per bank write bursts +system.physmem.perBankWrBursts::8 7013 # Per bank write bursts +system.physmem.perBankWrBursts::9 6813 # Per bank write bursts +system.physmem.perBankWrBursts::10 6467 # Per bank write bursts +system.physmem.perBankWrBursts::11 6119 # Per bank write bursts +system.physmem.perBankWrBursts::12 7057 # Per bank write bursts +system.physmem.perBankWrBursts::13 6685 # Per bank write bursts +system.physmem.perBankWrBursts::14 6965 # Per bank write bursts +system.physmem.perBankWrBursts::15 6821 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2550602119500 # Total gap between requests +system.physmem.totGap 2550236004000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 38 # Read request sizes (log2) system.physmem.readPktSize::3 15138816 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 154598 # Read request sizes (log2) +system.physmem.readPktSize::6 154633 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 754018 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 59148 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1066844 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1005139 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 964469 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1068011 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 971384 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1033822 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2692544 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2602827 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3401172 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 112530 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 102949 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 95927 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 92392 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 19066 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 18545 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 18331 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 57 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59160 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1068642 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1003556 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 964678 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1068028 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 971433 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1034228 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2693278 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2602966 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3400925 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 112135 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 102170 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 95874 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 92374 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 19109 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 18588 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 18396 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 38 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -161,43 +161,43 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 297 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 298 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 289 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 280 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 272 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 268 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 279 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 278 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 274 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 269 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 267 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 265 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 264 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 263 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3524 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4792 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6078 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6458 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6079 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6047 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6081 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5943 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5910 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6309 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5883 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5894 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5982 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5778 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3279 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3544 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4723 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6033 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6064 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6482 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6060 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6076 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5934 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5931 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6266 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5878 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5998 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5786 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see @@ -225,95 +225,96 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1010962 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 973.187598 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 908.669037 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 201.227455 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22588 2.23% 2.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 20116 1.99% 4.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8785 0.87% 5.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2331 0.23% 5.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2167 0.21% 5.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1761 0.17% 5.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 9115 0.90% 6.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 858 0.08% 6.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 943241 93.30% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1010962 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6071 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2514.580135 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 47785.198367 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-65535 6044 99.56% 99.56% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::65536-131071 1 0.02% 99.57% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::131072-196607 8 0.13% 99.70% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::196608-262143 6 0.10% 99.80% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1011151 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 973.031391 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 908.214038 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 201.586844 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22832 2.26% 2.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 19987 1.98% 4.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8899 0.88% 5.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2276 0.23% 5.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2117 0.21% 5.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1805 0.18% 5.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 9141 0.90% 6.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 764 0.08% 6.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 943330 93.29% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1011151 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6075 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2512.992263 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 47101.457482 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-65535 6047 99.54% 99.54% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::65536-131071 1 0.02% 99.56% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::131072-196607 8 0.13% 99.69% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::196608-262143 7 0.12% 99.80% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::393216-458751 1 0.02% 99.82% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::589824-655359 2 0.03% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::983040-1.04858e+06 1 0.02% 99.87% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1.17965e+06-1.24518e+06 7 0.12% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::983040-1.04858e+06 2 0.03% 99.88% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1.17965e+06-1.24518e+06 6 0.10% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1.37626e+06-1.44179e+06 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6071 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6071 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.578158 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.392553 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.387042 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::1 4 0.07% 0.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::2 4 0.07% 0.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::3 2 0.03% 0.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4 7 0.12% 0.28% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 6075 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6075 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.565103 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.376946 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.337614 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::1 6 0.10% 0.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::2 5 0.08% 0.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::3 2 0.03% 0.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4 4 0.07% 0.28% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::5 2 0.03% 0.31% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::6 2 0.03% 0.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::7 3 0.05% 0.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8 4 0.07% 0.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::9 6 0.10% 0.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::10 2 0.03% 0.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::11 3 0.05% 0.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::13 2 0.03% 0.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::7 2 0.03% 0.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8 4 0.07% 0.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::9 5 0.08% 0.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::10 2 0.03% 0.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::11 3 0.05% 0.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12 3 0.05% 0.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::13 1 0.02% 0.67% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::14 4 0.07% 0.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::15 12 0.20% 0.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 2739 45.12% 46.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 35 0.58% 46.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 1542 25.40% 72.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1308 21.55% 93.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 93 1.53% 95.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 45 0.74% 95.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 49 0.81% 96.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 58 0.96% 97.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 25 0.41% 98.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 17 0.28% 98.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 20 0.33% 98.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 16 0.26% 98.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 13 0.21% 99.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 14 0.23% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 14 0.23% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 16 0.26% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 10 0.16% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6071 # Writes before turning the bus around for reads -system.physmem.totQLat 393355196000 # Total ticks spent queuing -system.physmem.totMemAccLat 679593221000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 76330140000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25766.70 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::15 11 0.18% 0.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 2721 44.79% 45.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 38 0.63% 46.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 1583 26.06% 72.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1297 21.35% 93.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 91 1.50% 95.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 44 0.72% 95.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 54 0.89% 96.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 48 0.79% 97.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 29 0.48% 98.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 18 0.30% 98.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 20 0.33% 98.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 17 0.28% 99.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 13 0.21% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 16 0.26% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 12 0.20% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 10 0.16% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 8 0.13% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6075 # Writes before turning the bus around for reads +system.physmem.totQLat 393209260500 # Total ticks spent queuing +system.physmem.totMemAccLat 679455066750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 76332215000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25756.44 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44516.70 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 383.06 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 44506.44 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 383.12 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.68 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 51.36 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 51.37 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.67 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 3.01 # Data bus utilization in percentage system.physmem.busUtilRead 2.99 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 6.51 # Average read queue length when enqueuing -system.physmem.avgWrQLen 15.34 # Average write queue length when enqueuing -system.physmem.readRowHits 14270645 # Number of row buffer hits during reads -system.physmem.writeRowHits 91138 # Number of row buffer hits during writes +system.physmem.avgRdQLen 6.37 # Average read queue length when enqueuing +system.physmem.avgWrQLen 14.37 # Average write queue length when enqueuing +system.physmem.readRowHits 14270960 # Number of row buffer hits during reads +system.physmem.writeRowHits 91040 # Number of row buffer hits during writes system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 85.38 # Row buffer hit rate for writes -system.physmem.avgGap 158357.40 # Average gap between requests +system.physmem.writeRowHitRate 85.29 # Row buffer hit rate for writes +system.physmem.avgGap 158334.21 # Average gap between requests system.physmem.pageHitRate 93.42 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2202343950500 # Time in different power states -system.physmem.memoryStateTime::REF 85170020000 # Time in different power states +system.physmem.memoryStateTime::IDLE 2202305646000 # Time in different power states +system.physmem.memoryStateTime::REF 85157800000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 263082705750 # Time in different power states +system.physmem.memoryStateTime::ACT 262767276500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory @@ -327,283 +328,289 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54969203 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16346092 # Transaction distribution -system.membus.trans_dist::ReadResp 16346092 # Transaction distribution +system.membus.throughput 54978267 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16346128 # Transaction distribution +system.membus.trans_dist::ReadResp 16346128 # Transaction distribution system.membus.trans_dist::WriteReq 763361 # Transaction distribution system.membus.trans_dist::WriteResp 763361 # Transaction distribution -system.membus.trans_dist::Writeback 59148 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4680 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4680 # Transaction distribution -system.membus.trans_dist::ReadExReq 131444 # Transaction distribution -system.membus.trans_dist::ReadExResp 131444 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2383060 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::Writeback 59160 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4685 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4687 # Transaction distribution +system.membus.trans_dist::ReadExReq 131439 # Transaction distribution +system.membus.trans_dist::ReadExResp 131439 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2383052 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3790 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1885816 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4272670 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1885912 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4272758 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34550302 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390486 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 34550390 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390470 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7580 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16695968 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 19094102 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16698976 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 19097094 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 140204630 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 140204630 # Total data (bytes) +system.membus.tot_pkt_size::total 140207622 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 140207622 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1486938500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1487194000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3616000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3622500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17564463000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17516054500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4735162713 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4714051227 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 37454635709 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 37455331951 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 64370 # number of replacements -system.l2c.tags.tagsinuse 51446.531370 # Cycle average of tags in use -system.l2c.tags.total_refs 1904863 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 129760 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 14.679894 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2513258094500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 36996.902854 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 21.266230 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000371 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4638.850911 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3223.219228 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 10.615555 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3561.358912 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2994.317308 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.564528 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000324 # Average percentage of cache occupancy +system.l2c.tags.replacements 64405 # number of replacements +system.l2c.tags.tagsinuse 51448.142618 # Cycle average of tags in use +system.l2c.tags.total_refs 1904465 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 129797 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 14.672643 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2540066144500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 37002.110374 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 24.124150 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000251 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4932.290143 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3309.962047 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 8.942781 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3265.462064 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2905.250809 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.564607 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000368 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.070783 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.049182 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000162 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.054342 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.045690 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.785012 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 22 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65368 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 21 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 347 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3064 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6835 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55083 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000336 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.997437 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 18932032 # Number of tag accesses -system.l2c.tags.data_accesses 18932032 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 32158 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 6860 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 505744 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 187679 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 31450 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 7231 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 465794 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 199404 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1436320 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 607907 # number of Writeback hits -system.l2c.Writeback_hits::total 607907 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 19 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 15 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 34 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 2 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 5 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 7 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 58462 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 54465 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 112927 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 32158 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 6860 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 505744 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 246141 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 31450 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 7231 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 465794 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 253869 # number of demand (read+write) hits -system.l2c.demand_hits::total 1549247 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 32158 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 6860 # number of overall hits -system.l2c.overall_hits::cpu0.inst 505744 # number of overall hits -system.l2c.overall_hits::cpu0.data 246141 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 31450 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 7231 # number of overall hits -system.l2c.overall_hits::cpu1.inst 465794 # number of overall hits -system.l2c.overall_hits::cpu1.data 253869 # number of overall hits -system.l2c.overall_hits::total 1549247 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 31 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 7502 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6162 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 12 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 4864 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 4544 # number of ReadReq misses -system.l2c.ReadReq_misses::total 23117 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1628 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1276 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2904 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 74336 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 58884 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 133220 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 31 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 7502 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 80498 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 12 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 4864 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 63428 # number of demand (read+write) misses -system.l2c.demand_misses::total 156337 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 31 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 7502 # number of overall misses -system.l2c.overall_misses::cpu0.data 80498 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 12 # number of overall misses -system.l2c.overall_misses::cpu1.inst 4864 # number of overall misses -system.l2c.overall_misses::cpu1.data 63428 # number of overall misses -system.l2c.overall_misses::total 156337 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 2994000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 368000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 537467000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 452401999 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 913750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 350167750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 341997500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1686309999 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 186492 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 326986 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 513478 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 5509515842 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 4330037632 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 9839553474 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 2994000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 368000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 537467000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 5961917841 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 913750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 350167750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 4672035132 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 11525863473 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 2994000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 368000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 537467000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 5961917841 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 913750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 350167750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 4672035132 # number of overall miss cycles -system.l2c.overall_miss_latency::total 11525863473 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 32189 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 6862 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 513246 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 193841 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 31462 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 7231 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 470658 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 203948 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1459437 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 607907 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 607907 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 1647 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1291 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2938 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 5 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 7 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 132798 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 113349 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 246147 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 32189 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 6862 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 513246 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 326639 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 31462 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 7231 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 470658 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 317297 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1705584 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 32189 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 6862 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 513246 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 326639 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 31462 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 7231 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 470658 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 317297 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1705584 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000963 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000291 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.014617 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.031789 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000381 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.010334 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.022280 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.015840 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.988464 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.988381 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.988428 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.559767 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.519493 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.541221 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000963 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000291 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.014617 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.246443 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000381 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.010334 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.199901 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.091662 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000963 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000291 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.014617 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.246443 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000381 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.010334 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.199901 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.091662 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 96580.645161 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 184000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 71643.161824 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 73418.045927 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 76145.833333 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 71991.724918 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 75263.534331 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 72946.749102 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 114.552826 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 256.258621 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 176.817493 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 74116.388318 # average ReadExReq miss latency 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overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 184000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 71643.161824 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 74062.931265 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 76145.833333 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 71991.724918 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 73658.875134 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 73724.476439 # average overall miss latency +system.l2c.tags.occ_percent::cpu0.inst 0.075261 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.050506 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000136 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.049827 # Average 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+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000146 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015261 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.251119 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000355 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009692 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.193285 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.091673 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.001080 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000146 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015261 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.251119 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000355 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009692 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.193285 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.091673 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 89364.285714 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 281000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 58891.705069 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61505.752051 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 70750 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60247.646673 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 64344.497068 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 60973.392226 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10002.566614 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.688361 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 61669.274080 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61089.105156 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 61412.836106 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 84241.935484 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 171750 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59068.588204 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61615.745339 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 63645.833333 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59405.033972 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61214.590057 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 61268.145063 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 84241.935484 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 171750 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59068.588204 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61615.745339 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 63645.833333 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59405.033972 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61214.590057 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 61268.145063 # average overall mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001.737463 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.343879 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 61530.156287 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59331.574060 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 60610.807088 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 89364.285714 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 281000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 58891.705069 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61528.344756 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 70750 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60247.646673 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 59701.172833 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 60664.341591 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 89364.285714 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 281000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 58891.705069 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61528.344756 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 70750 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60247.646673 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 59701.172833 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 60664.341591 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -778,46 +797,46 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 58427348 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2677396 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2677395 # Transaction distribution +system.toL2Bus.throughput 58447524 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2676676 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2676675 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 763361 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 763361 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 607907 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2938 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 7 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2945 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 246147 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 246147 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1969203 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5796633 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 38454 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 149595 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7953885 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 62977408 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 85532246 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 56372 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 254604 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 148820630 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 148820630 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 204356 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4962673723 # Layer occupancy (ticks) +system.toL2Bus.trans_dist::Writeback 608464 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2946 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 18 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2964 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 246266 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 246266 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1967872 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5798454 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 37749 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 149111 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7953186 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 62935104 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 85607366 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 55020 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 253376 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 148850866 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 148850866 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 204184 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4964883974 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4436346984 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4433375902 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4483051170 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4485758372 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 24406904 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 24044394 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 86367392 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 86236537 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48420315 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16322169 # Transaction distribution -system.iobus.trans_dist::ReadResp 16322169 # Transaction distribution +system.iobus.throughput 48427259 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16322165 # Transaction distribution +system.iobus.trans_dist::ReadResp 16322165 # Transaction distribution system.iobus.trans_dist::WriteReq 8177 # Transaction distribution system.iobus.trans_dist::WriteResp 8177 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7940 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7932 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 522 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1030 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -839,12 +858,12 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2383060 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2383052 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 32660692 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 32660684 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15880 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15864 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1044 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2060 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -866,14 +885,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390486 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390470 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 123501014 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 123501014 # Total data (bytes) +system.iobus.tot_pkt_size::total 123500998 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 123500998 # Total data (bytes) system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3975000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 3971000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 522000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -919,19 +938,19 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374883000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374875000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 38146923291 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 38148865049 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) -system.cpu0.branchPred.lookups 7527303 # Number of BP lookups -system.cpu0.branchPred.condPredicted 6005482 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 376664 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 4812068 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 3910560 # Number of BTB hits +system.cpu0.branchPred.lookups 7661485 # Number of BP lookups +system.cpu0.branchPred.condPredicted 6126508 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 381527 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 4905065 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 3983490 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 81.265685 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 724420 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 38989 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 81.211768 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 723596 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 38982 # Number of incorrect RAS predictions. system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -955,25 +974,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 25762472 # DTB read hits -system.cpu0.dtb.read_misses 39475 # DTB read misses -system.cpu0.dtb.write_hits 6143291 # DTB write hits -system.cpu0.dtb.write_misses 10324 # DTB write misses +system.cpu0.dtb.read_hits 25785436 # DTB read hits +system.cpu0.dtb.read_misses 39736 # DTB read misses +system.cpu0.dtb.write_hits 6191742 # DTB write hits +system.cpu0.dtb.write_misses 10170 # DTB write misses system.cpu0.dtb.flush_tlb 514 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 752 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5580 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1376 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 262 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 714 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 5474 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1453 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 252 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 639 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 25801947 # DTB read accesses -system.cpu0.dtb.write_accesses 6153615 # DTB write accesses +system.cpu0.dtb.perms_faults 628 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 25825172 # DTB read accesses +system.cpu0.dtb.write_accesses 6201912 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 31905763 # DTB hits -system.cpu0.dtb.misses 49799 # DTB misses -system.cpu0.dtb.accesses 31955562 # DTB accesses +system.cpu0.dtb.hits 31977178 # DTB hits +system.cpu0.dtb.misses 49906 # DTB misses +system.cpu0.dtb.accesses 32027084 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -995,694 +1014,696 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 5893431 # ITB inst hits -system.cpu0.itb.inst_misses 7431 # ITB inst misses +system.cpu0.itb.inst_hits 5958651 # ITB inst hits +system.cpu0.itb.inst_misses 7224 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 514 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 752 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2617 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 714 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 2573 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1506 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1518 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 5900862 # ITB inst accesses -system.cpu0.itb.hits 5893431 # DTB hits -system.cpu0.itb.misses 7431 # DTB misses -system.cpu0.itb.accesses 5900862 # DTB accesses -system.cpu0.numCycles 242264674 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 5965875 # ITB inst accesses +system.cpu0.itb.hits 5958651 # DTB hits +system.cpu0.itb.misses 7224 # DTB misses +system.cpu0.itb.accesses 5965875 # DTB accesses +system.cpu0.numCycles 242096947 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 15531926 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 45587183 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 7527303 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 4634980 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 10285875 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2434733 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 89107 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 50171859 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 1648 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 2068 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 54478 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 1474048 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 435 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 5891523 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 366856 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 3025 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 79291736 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.723314 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.072188 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 15548527 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 46430150 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 7661485 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 4707086 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 10443980 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2504010 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 87505 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 47991707 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 1669 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 1947 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 50069 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 1492171 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 279 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 5956718 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 371320 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2975 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 77361996 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.753757 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.110815 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 69012854 87.04% 87.04% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 680232 0.86% 87.89% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 874808 1.10% 89.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1172230 1.48% 90.48% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1090891 1.38% 91.85% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 557599 0.70% 92.56% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 1295199 1.63% 94.19% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 379880 0.48% 94.67% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4228043 5.33% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 66925381 86.51% 86.51% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 685980 0.89% 87.40% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 883677 1.14% 88.54% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1195178 1.54% 90.08% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1096516 1.42% 91.50% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 566437 0.73% 92.23% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 1314357 1.70% 93.93% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 386846 0.50% 94.43% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4307624 5.57% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 79291736 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.031071 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.188171 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 16635366 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 51194908 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 9213198 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 653944 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1592125 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 1010665 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 90813 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 54600074 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 300654 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1592125 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 17527482 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 20299787 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 27625200 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 8910460 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 3334547 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 52031373 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 331 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 485563 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 2176301 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 182 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 53736698 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 241285167 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 220106334 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 4864 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 39390817 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 14345881 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 590593 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 539084 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 6947132 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 10055649 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6962422 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1056834 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1358453 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 48348288 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1003135 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 62086915 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 89013 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 9905639 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 24691410 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 254686 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 79291736 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.783019 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.501466 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 77361996 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.031646 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.191783 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 16313273 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 49370536 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 9491475 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 529288 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1655237 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 1021533 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 91523 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 55531280 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 303986 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1655237 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 17162522 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 7654348 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 28580121 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 9244360 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 13063308 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 52889125 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 1160 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 8605902 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 9933616 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 1829408 # Number of times rename has blocked due to SQ full +system.cpu0.rename.FullRegisterEvents 705 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 54696180 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 245103090 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 223663577 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 5274 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 39761499 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 14934681 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 590339 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 538925 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5812671 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 10214201 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 7053988 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1084092 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1355038 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 49147671 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1004891 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 62507144 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 106564 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 10354652 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 26208427 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 256708 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 77361996 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.807983 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.536259 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 56790483 71.62% 71.62% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 7331291 9.25% 80.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3517102 4.44% 85.30% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2900884 3.66% 88.96% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 6182474 7.80% 96.76% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1488398 1.88% 98.64% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 785922 0.99% 99.63% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 230106 0.29% 99.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 65076 0.08% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 55228815 71.39% 71.39% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 6921867 8.95% 80.34% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3371546 4.36% 84.70% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2828196 3.66% 88.35% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 6343832 8.20% 96.55% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1429149 1.85% 98.40% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 903697 1.17% 99.57% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 264810 0.34% 99.91% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 70084 0.09% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 79291736 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 77361996 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 31039 0.70% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 1 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 4198728 94.33% 95.03% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 221343 4.97% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 34065 0.76% 0.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 2 0.00% 0.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 4230863 93.99% 94.75% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 236461 5.25% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 14970 0.02% 0.02% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 29137192 46.93% 46.95% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 47374 0.08% 47.03% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.03% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.03% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.03% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.03% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.03% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.03% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.03% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.03% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.03% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.03% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.03% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.03% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 11 0.00% 47.03% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.03% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.03% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 47.03% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 7 0.00% 47.03% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.03% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.03% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.03% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.03% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.03% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.03% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 1226 0.00% 47.03% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.03% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 10 0.00% 47.03% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.03% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 26440432 42.59% 89.62% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6445693 10.38% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 14977 0.02% 0.02% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 29471794 47.15% 47.17% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 48326 0.08% 47.25% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.25% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.25% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.25% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.25% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.25% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.25% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 10 0.00% 47.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 47.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 7 0.00% 47.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 1252 0.00% 47.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 10 0.00% 47.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.25% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 26467836 42.34% 89.60% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 6502932 10.40% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 62086915 # Type of FU issued -system.cpu0.iq.rate 0.256277 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 4451111 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.071692 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 208044448 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 59266351 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 43285904 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 10871 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 5830 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 4924 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 66517304 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 5752 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 316537 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 62507144 # Type of FU issued +system.cpu0.iq.rate 0.258191 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 4501391 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.072014 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 207022163 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 60516960 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 43741315 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 11807 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 6284 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 5315 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 66987291 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 6267 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 331575 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2144033 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 4052 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 15721 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 849604 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2258680 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3312 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 16640 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 890724 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 17082730 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 349385 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 17025951 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 348422 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1592125 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 15682380 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 239912 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 49471978 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 105539 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 10055649 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6962422 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 704937 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 56286 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 4027 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 15721 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 184221 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 145235 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 329456 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 61023718 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 26110824 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1063197 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1655237 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 6199849 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 752551 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 50264845 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 98291 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 10214201 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 7053988 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 705061 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 147463 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 536075 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 16640 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 186895 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 147787 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 334682 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 61435794 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 26133192 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1071350 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 120555 # number of nop insts executed -system.cpu0.iew.exec_refs 32498156 # number of memory reference insts executed -system.cpu0.iew.exec_branches 5982225 # Number of branches executed -system.cpu0.iew.exec_stores 6387332 # Number of stores executed -system.cpu0.iew.exec_rate 0.251889 # Inst execution rate -system.cpu0.iew.wb_sent 60528797 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 43290828 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 23369621 # num instructions producing a value -system.cpu0.iew.wb_consumers 42956226 # num instructions consuming a value +system.cpu0.iew.exec_nop 112283 # number of nop insts executed +system.cpu0.iew.exec_refs 32576038 # number of memory reference insts executed +system.cpu0.iew.exec_branches 6024055 # Number of branches executed +system.cpu0.iew.exec_stores 6442846 # Number of stores executed +system.cpu0.iew.exec_rate 0.253765 # Inst execution rate +system.cpu0.iew.wb_sent 60932314 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 43746630 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 24175990 # num instructions producing a value +system.cpu0.iew.wb_consumers 44857309 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.178692 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.544033 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.180699 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.538953 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 9786876 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 748449 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 287258 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 77699611 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.504830 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.472024 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 10244306 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 748183 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 291383 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 75706759 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.522606 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.501619 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 63277588 81.44% 81.44% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 7407512 9.53% 90.97% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1967451 2.53% 93.50% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1105852 1.42% 94.93% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 852897 1.10% 96.03% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 576328 0.74% 96.77% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 737114 0.95% 97.72% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 349768 0.45% 98.17% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1425101 1.83% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 61320530 81.00% 81.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7333121 9.69% 90.68% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1910409 2.52% 93.21% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1174950 1.55% 94.76% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 814971 1.08% 95.84% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 569506 0.75% 96.59% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 771340 1.02% 97.61% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 344904 0.46% 98.06% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1467028 1.94% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 77699611 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 30084753 # Number of instructions committed -system.cpu0.commit.committedOps 39225066 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 75706759 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 30422123 # Number of instructions committed +system.cpu0.commit.committedOps 39564795 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 14024434 # Number of memory references committed -system.cpu0.commit.loads 7911616 # Number of loads committed -system.cpu0.commit.membars 209739 # Number of memory barriers committed -system.cpu0.commit.branches 5192960 # Number of branches committed -system.cpu0.commit.fp_insts 4874 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 34907078 # Number of committed integer instructions. -system.cpu0.commit.function_calls 509367 # Number of function calls committed. +system.cpu0.commit.refs 14118785 # Number of memory references committed +system.cpu0.commit.loads 7955521 # Number of loads committed +system.cpu0.commit.membars 210845 # Number of memory barriers committed +system.cpu0.commit.branches 5215430 # Number of branches committed +system.cpu0.commit.fp_insts 5270 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 35234514 # Number of committed integer instructions. +system.cpu0.commit.function_calls 505825 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 25154804 64.13% 64.13% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 44602 0.11% 64.24% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 64.24% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 64.24% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 64.24% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 64.24% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 64.24% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 64.24% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 64.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 64.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 64.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 64.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 64.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 64.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 64.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 64.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 64.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 64.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 64.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 64.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 64.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 64.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 64.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 64.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 64.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 1226 0.00% 64.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 64.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.25% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 7911616 20.17% 84.42% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 6112818 15.58% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 25399613 64.20% 64.20% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 45146 0.11% 64.31% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 64.31% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 64.31% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 64.31% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 64.31% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 64.31% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 64.31% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 64.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 64.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 64.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 64.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 64.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 64.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 64.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 64.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 64.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 64.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 64.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 64.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 64.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 64.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 64.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 64.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 64.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 1251 0.00% 64.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 64.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.31% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 7955521 20.11% 84.42% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 6163264 15.58% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 39225066 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1425101 # number cycles where commit BW limit reached +system.cpu0.commit.op_class_0::total 39564795 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1467028 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 124324951 # The number of ROB reads -system.cpu0.rob.rob_writes 99658992 # The number of ROB writes -system.cpu0.timesIdled 907419 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 162972938 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2247980405 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 30002566 # Number of Instructions Simulated -system.cpu0.committedOps 39142879 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 8.074798 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 8.074798 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.123842 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.123842 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 277224657 # number of integer regfile reads -system.cpu0.int_regfile_writes 43993248 # number of integer regfile writes -system.cpu0.fp_regfile_reads 44815 # number of floating regfile reads -system.cpu0.fp_regfile_writes 42286 # number of floating regfile writes -system.cpu0.misc_regfile_reads 137449038 # number of misc regfile reads -system.cpu0.misc_regfile_writes 580454 # number of misc regfile writes -system.cpu0.icache.tags.replacements 984532 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.571226 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 10502635 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 985044 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 10.662097 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 7040991250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 317.697202 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 193.874025 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.620502 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.378660 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999163 # Average percentage of cache occupancy +system.cpu0.rob.rob_reads 123090455 # The number of ROB reads +system.cpu0.rob.rob_writes 101316686 # The number of ROB writes +system.cpu0.timesIdled 905863 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 164734951 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2248240039 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 30347856 # Number of Instructions Simulated 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blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 163 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 138 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 211 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 162 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 12553911 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 12553911 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 5335132 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 5167503 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 10502635 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5335132 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 5167503 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 10502635 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5335132 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 5167503 # number of overall hits -system.cpu0.icache.overall_hits::total 10502635 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 556266 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 509949 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1066215 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 556266 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 509949 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1066215 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 556266 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 509949 # number of overall misses -system.cpu0.icache.overall_misses::total 1066215 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7659182978 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6870398274 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 14529581252 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 7659182978 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 6870398274 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 14529581252 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 7659182978 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 6870398274 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 14529581252 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 5891398 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 5677452 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 11568850 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 5891398 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 5677452 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 11568850 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 5891398 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 5677452 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 11568850 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.094420 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.089820 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.092163 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.094420 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.089820 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.092163 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.094420 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.089820 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.092163 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13768.921663 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13472.716436 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13627.252714 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13768.921663 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13472.716436 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13627.252714 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13768.921663 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13472.716436 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13627.252714 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 6572 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 144 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 397 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 16.554156 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 144 # average number of cycles each access was blocked +system.cpu0.icache.tags.tag_accesses 12622728 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 12622728 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 5401219 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 5171060 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 10572279 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 5401219 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 5171060 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 10572279 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 5401219 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 5171060 # number of overall hits +system.cpu0.icache.overall_hits::total 10572279 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 555378 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 510680 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1066058 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 555378 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 510680 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1066058 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 555378 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 510680 # number of overall misses +system.cpu0.icache.overall_misses::total 1066058 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7663232618 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6859208809 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 14522441427 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 7663232618 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 6859208809 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 14522441427 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 7663232618 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 6859208809 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 14522441427 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 5956597 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 5681740 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 11638337 # number of ReadReq accesses(hits+misses) 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rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.091599 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.093237 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.089881 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.091599 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13798.228626 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13431.520343 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13622.562212 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13798.228626 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13431.520343 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13622.562212 # average overall miss latency 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accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12152.176982 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11832.828434 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11999.094435 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12152.176982 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11832.828434 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11999.094435 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12152.176982 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11832.828434 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11999.094435 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 643424 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.993257 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 21526419 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 643936 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 33.429439 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 43468250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 254.820066 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 257.173192 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.497695 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.502291 # Average percentage of cache occupancy +system.cpu0.dcache.tags.replacements 644041 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.993361 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 21521749 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 644553 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 33.390193 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 42479250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 255.642215 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 256.351146 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.499301 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.500686 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 190 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 303 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 302 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 101635836 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 101635836 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 7044250 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 6727132 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13771382 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3751595 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 3509581 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 7261176 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 116856 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 126271 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 243127 # number of LoadLockedReq hits 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miss cycles -system.cpu0.dcache.overall_miss_latency::total 160025112228 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7379776 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 7140342 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 14520118 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5372501 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 4851051 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 10223552 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 124253 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 132401 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 256654 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 119518 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 128133 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 247651 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12752277 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 11991393 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 24743670 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12752277 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 11991393 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 24743670 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.045466 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.057870 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.051565 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.301704 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.276532 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.289760 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059532 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.046299 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052705 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000017 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000039 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000028 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.153418 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.146328 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.149982 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.153418 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.146328 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.149982 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16007.580986 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14564.877994 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15211.386729 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 52038.246168 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 47922.572947 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 50174.521862 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14208.327160 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13440.945024 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13860.574333 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 13000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 45859.025543 # average overall miss latency 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StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 127119 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 247644 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12857427 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 11908477 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 24765904 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12857427 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 11908477 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 24765904 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.049124 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.056626 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.052787 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.307201 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.271874 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.290586 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059025 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.046764 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052754 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000075 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000071 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000073 # miss rate for StoreCondReq accesses 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# average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 47188.394190 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14334.401295 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13321.009761 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13874.944313 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 14389 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 14389 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 14389 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 44284.781207 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 36269.518818 # average overall miss latency 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fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 607907 # number of writebacks -system.cpu0.dcache.writebacks::total 607907 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 148329 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 214670 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 362999 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1486511 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1226891 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 2713402 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 703 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 661 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1364 # 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MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7736714362 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 16709674840 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91614967500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90722197000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182337164500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13706653581 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 13072228739 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26778882320 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 105321621081 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103794425739 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 209116046820 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.025366 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027805 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026566 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025015 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023619 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024353 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.053874 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.041306 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047391 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000017 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000039 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000028 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.025218 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.026112 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.025651 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.025218 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.026112 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.025651 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13866.040583 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13267.208633 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13557.819968 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47451.759954 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 44533.839185 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46108.919160 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12477.106812 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11653.137137 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12106.615144 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27901.690583 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24708.543276 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26326.430202 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 27901.690583 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24708.543276 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26326.430202 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 608464 # number of writebacks +system.cpu0.dcache.writebacks::total 608464 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 174205 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 207237 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 381442 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1526591 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1195009 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 2721600 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 704 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 669 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1373 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1700796 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 1402246 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 3103042 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1700796 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 1402246 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 3103042 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 191404 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 194821 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 386225 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 136878 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 112211 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 249089 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6707 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5478 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12185 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 9 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 9 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 18 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 328282 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 307032 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 635314 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 328282 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 307032 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 635314 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2672225710 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2597817092 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5270042802 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6526900100 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 4738022235 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11264922335 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 84662502 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 63153752 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 147816254 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 111499 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 111499 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 222998 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9199125810 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7335839327 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 16534965137 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 9199125810 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7335839327 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 16534965137 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91653477500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90683023500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182336501000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13720132000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 13077337591 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26797469591 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 105373609500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103760361091 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 209133970591 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.025718 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027438 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026558 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025278 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023337 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024365 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.053418 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.041675 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047412 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000075 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000071 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000073 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.025532 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025783 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.025653 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.025532 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025783 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.025653 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13961.180069 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13334.379210 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13645.006931 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47684.069756 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42224.222536 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 45224.487372 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12623.006113 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11528.614823 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12131.001559 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 12388.777778 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 12388.777778 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 12388.777778 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 28022.023169 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23892.751658 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26026.445407 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 28022.023169 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 23892.751658 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26026.445407 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1693,15 +1714,15 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 7300035 # Number of BP lookups -system.cpu1.branchPred.condPredicted 5887077 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 345091 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 4651296 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 3771120 # Number of BTB hits +system.cpu1.branchPred.lookups 7344792 # Number of BP lookups +system.cpu1.branchPred.condPredicted 5924572 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 342317 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 4758265 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 3794052 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 81.076758 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 673548 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 34495 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 79.736038 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 685317 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 35371 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1725,25 +1746,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 25450161 # DTB read hits -system.cpu1.dtb.read_misses 36388 # DTB read misses -system.cpu1.dtb.write_hits 5568332 # DTB write hits -system.cpu1.dtb.write_misses 8538 # DTB write misses +system.cpu1.dtb.read_hits 25350014 # DTB read hits +system.cpu1.dtb.read_misses 36246 # DTB read misses +system.cpu1.dtb.write_hits 5533315 # DTB write hits +system.cpu1.dtb.write_misses 8540 # DTB write misses system.cpu1.dtb.flush_tlb 510 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 687 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 5495 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 2244 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 247 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 725 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 5471 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 1908 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 249 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 710 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 25486549 # DTB read accesses -system.cpu1.dtb.write_accesses 5576870 # DTB write accesses +system.cpu1.dtb.read_accesses 25386260 # DTB read accesses +system.cpu1.dtb.write_accesses 5541855 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 31018493 # DTB hits -system.cpu1.dtb.misses 44926 # DTB misses -system.cpu1.dtb.accesses 31063419 # DTB accesses +system.cpu1.dtb.hits 30883329 # DTB hits +system.cpu1.dtb.misses 44786 # DTB misses +system.cpu1.dtb.accesses 30928115 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1765,125 +1786,126 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 5679651 # ITB inst hits -system.cpu1.itb.inst_misses 6870 # ITB inst misses +system.cpu1.itb.inst_hits 5683844 # ITB inst hits +system.cpu1.itb.inst_misses 6848 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 510 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 687 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2692 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 725 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 2653 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1570 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1514 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 5686521 # ITB inst accesses -system.cpu1.itb.hits 5679651 # DTB hits -system.cpu1.itb.misses 6870 # DTB misses -system.cpu1.itb.accesses 5686521 # DTB accesses -system.cpu1.numCycles 236844574 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 5690692 # ITB inst accesses +system.cpu1.itb.hits 5683844 # DTB hits +system.cpu1.itb.misses 6848 # DTB misses +system.cpu1.itb.accesses 5690692 # DTB accesses +system.cpu1.numCycles 235812118 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 14466322 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 45074741 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 7300035 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 4444668 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 9928510 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 2284755 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 83810 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 49428019 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 1085 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 1865 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 44064 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 1232877 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 132 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 5677454 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 353029 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3058 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 76760101 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.724873 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.076516 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 14488159 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 45028124 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 7344792 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 4479369 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 9950354 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 2325910 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 82893 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 46948697 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 1099 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 1893 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 45519 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 1268155 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 161 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 5681743 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 353393 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2950 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 74402978 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.748631 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.104884 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 66839787 87.08% 87.08% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 628644 0.82% 87.90% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 837705 1.09% 88.99% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1128430 1.47% 90.46% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1025116 1.34% 91.79% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 549692 0.72% 92.51% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1265677 1.65% 94.16% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 371391 0.48% 94.64% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 4113659 5.36% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 64461074 86.64% 86.64% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 633258 0.85% 87.49% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 845202 1.14% 88.62% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1118143 1.50% 90.13% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1030578 1.39% 91.51% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 551741 0.74% 92.25% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1296054 1.74% 94.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 370486 0.50% 94.49% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 4096442 5.51% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 76760101 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.030822 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.190314 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 15575790 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 50164874 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 8875530 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 651724 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1490012 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 958602 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 85804 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 53028773 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 286820 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1490012 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 16419373 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 19259514 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 27698423 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 8639214 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 3251470 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 50560580 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 221 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 607469 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 2007282 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 572 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 52946210 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 233908561 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 213841042 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 5698 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 39345682 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 13600527 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 580708 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 537933 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 6505084 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 9729570 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 6369599 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 877361 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1114434 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 47034811 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 984793 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 60942495 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 91566 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 9279731 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 23349761 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 250555 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 76760101 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.793935 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.504235 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 74402978 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.031147 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.190949 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 15290128 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 48029788 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 9010807 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 535995 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1534066 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 962796 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 84486 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 53087117 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 281620 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1534066 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 16089413 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 6996685 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 28422508 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 8819964 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 12538212 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 50579819 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 715 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 8590875 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 9852379 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 1395671 # Number of times rename has blocked due to SQ full +system.cpu1.rename.FullRegisterEvents 1301 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 52976488 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 233969396 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 213834273 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 5207 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 38971918 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 14004569 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 583497 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 540607 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 5363476 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 9768473 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 6353478 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 903299 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1144541 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 47001226 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 985413 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 60595640 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 98989 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 9593116 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 24473464 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 250944 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 74402978 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.814425 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.533021 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 54532875 71.04% 71.04% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 7326090 9.54% 80.59% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 3469207 4.52% 85.11% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 2884980 3.76% 88.87% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 6118042 7.97% 96.84% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1370862 1.79% 98.62% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 772587 1.01% 99.63% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 222613 0.29% 99.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 62845 0.08% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 52794785 70.96% 70.96% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 6823804 9.17% 80.13% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 3272663 4.40% 84.53% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 2786608 3.75% 88.27% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 6272134 8.43% 96.70% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1319081 1.77% 98.48% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 820611 1.10% 99.58% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 247257 0.33% 99.91% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 66035 0.09% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 76760101 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 74402978 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 29035 0.66% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 5 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 29526 0.66% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 4 0.00% 0.66% # attempts to use FU when none available system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.66% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.66% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.66% # attempts to use FU when none available @@ -1911,182 +1933,182 @@ system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.66% # at system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.66% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.66% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4177111 94.84% 95.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 198082 4.50% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 4196905 94.38% 95.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 220217 4.95% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 13548 0.02% 0.02% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 28887832 47.40% 47.42% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 46127 0.08% 47.50% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 14 0.00% 47.50% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 11 0.00% 47.50% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 887 0.00% 47.50% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 11 0.00% 47.50% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 26105748 42.84% 90.34% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 5888317 9.66% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 13541 0.02% 0.02% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 28679065 47.33% 47.35% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 45344 0.07% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 13 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 9 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 858 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 26009717 42.92% 90.35% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 5847084 9.65% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 60942495 # Type of FU issued -system.cpu1.iq.rate 0.257310 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 4404233 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.072269 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 203173539 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 57307144 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 42269826 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 12116 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 6726 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 5381 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 65326800 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 6380 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 306796 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 60595640 # Type of FU issued +system.cpu1.iq.rate 0.256966 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 4446652 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.073382 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 200172970 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 57588554 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 41991709 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 11520 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 6240 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 4992 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 65022566 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 6185 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 323560 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 1984154 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 3003 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 15089 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 749009 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2067890 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 2468 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 15600 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 783792 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 17027364 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 331342 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 16950409 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 331839 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1490012 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 14823463 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 222107 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 48121220 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 96425 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 9729570 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 6369599 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 709638 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 48371 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 4239 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 15089 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 167591 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 133565 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 301156 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 59912848 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 25789830 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1029647 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 1534066 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 5578937 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 735039 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 48101549 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 89840 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 9768473 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 6353478 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 710230 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 138266 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 531900 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 15600 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 167974 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 132221 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 300195 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 59563474 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 25690610 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1032166 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 101616 # number of nop insts executed -system.cpu1.iew.exec_refs 31626536 # number of memory reference insts executed -system.cpu1.iew.exec_branches 5854246 # Number of branches executed -system.cpu1.iew.exec_stores 5836706 # Number of stores executed -system.cpu1.iew.exec_rate 0.252963 # Inst execution rate -system.cpu1.iew.wb_sent 59450905 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 42275207 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 23556720 # num instructions producing a value -system.cpu1.iew.wb_consumers 42880647 # num instructions consuming a value +system.cpu1.iew.exec_nop 114910 # number of nop insts executed +system.cpu1.iew.exec_refs 31485549 # number of memory reference insts executed +system.cpu1.iew.exec_branches 5840798 # Number of branches executed +system.cpu1.iew.exec_stores 5794939 # Number of stores executed +system.cpu1.iew.exec_rate 0.252589 # Inst execution rate +system.cpu1.iew.wb_sent 59096440 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 41996701 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 23719594 # num instructions producing a value +system.cpu1.iew.wb_consumers 43668575 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.178493 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.549356 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.178094 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.543173 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 9147109 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 734238 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 260548 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 75270089 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.511960 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.483838 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 9469311 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 734469 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 259123 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 72868911 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.524128 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.502288 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 60996835 81.04% 81.04% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 7463530 9.92% 90.95% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1923766 2.56% 93.51% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1066165 1.42% 94.93% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 822611 1.09% 96.02% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 493470 0.66% 96.67% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 696092 0.92% 97.60% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 369554 0.49% 98.09% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1438066 1.91% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 58802570 80.70% 80.70% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 7335717 10.07% 90.76% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1834357 2.52% 93.28% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1110131 1.52% 94.80% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 806352 1.11% 95.91% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 478738 0.66% 96.57% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 708592 0.97% 97.54% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 352493 0.48% 98.02% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1439961 1.98% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 75270089 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 30381625 # Number of instructions committed -system.cpu1.commit.committedOps 38535309 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 72868911 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 30042313 # Number of instructions committed +system.cpu1.commit.committedOps 38192613 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 13366006 # Number of memory references committed -system.cpu1.commit.loads 7745416 # Number of loads committed -system.cpu1.commit.membars 193947 # Number of memory barriers committed -system.cpu1.commit.branches 5114433 # Number of branches committed -system.cpu1.commit.fp_insts 5338 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 34292499 # Number of committed integer instructions. -system.cpu1.commit.function_calls 482077 # Number of function calls committed. +system.cpu1.commit.refs 13270269 # Number of memory references committed +system.cpu1.commit.loads 7700583 # Number of loads committed +system.cpu1.commit.membars 192827 # Number of memory barriers committed +system.cpu1.commit.branches 5091642 # Number of branches committed +system.cpu1.commit.fp_insts 4942 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 33962282 # Number of committed integer instructions. +system.cpu1.commit.function_calls 485556 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 25125071 65.20% 65.20% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 43345 0.11% 65.31% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 65.31% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 65.31% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 65.31% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 65.31% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 65.31% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 65.31% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 65.31% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 65.31% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 65.31% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 65.31% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 65.31% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 65.31% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 65.31% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 65.31% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 65.31% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 65.31% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 65.31% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 65.31% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 65.31% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 65.31% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 65.31% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 65.31% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 65.31% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 887 0.00% 65.31% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 65.31% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.31% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.31% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 7745416 20.10% 85.41% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 5620590 14.59% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 24878693 65.14% 65.14% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 42793 0.11% 65.25% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 65.25% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 65.25% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 65.25% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 65.25% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 65.25% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 65.25% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 65.25% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 65.25% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 65.25% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 65.25% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 65.25% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 65.25% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 65.25% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 65.25% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 65.25% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 65.25% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 65.25% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 65.25% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 65.25% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 65.25% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 65.25% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 65.25% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 65.25% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 858 0.00% 65.25% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 65.25% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.25% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.25% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 7700583 20.16% 85.42% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 5569686 14.58% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 38535309 # Class of committed instruction -system.cpu1.commit.bw_lim_events 1438066 # number cycles where commit BW limit reached +system.cpu1.commit.op_class_0::total 38192613 # Class of committed instruction +system.cpu1.commit.bw_lim_events 1439961 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 120626402 # The number of ROB reads -system.cpu1.rob.rob_writes 96898257 # The number of ROB writes -system.cpu1.timesIdled 866184 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 160084473 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 2317121408 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 30313431 # Number of Instructions Simulated -system.cpu1.committedOps 38467115 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 7.813189 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 7.813189 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.127989 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.127989 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 271901021 # number of integer regfile reads -system.cpu1.int_regfile_writes 43646883 # number of integer regfile writes -system.cpu1.fp_regfile_reads 45279 # number of floating regfile reads -system.cpu1.fp_regfile_writes 42402 # number of floating regfile writes -system.cpu1.misc_regfile_reads 133121444 # number of misc regfile reads -system.cpu1.misc_regfile_writes 593543 # number of misc regfile writes +system.cpu1.rob.rob_reads 118199712 # The number of ROB reads +system.cpu1.rob.rob_writes 96901530 # The number of ROB writes +system.cpu1.timesIdled 866503 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 161409140 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 2317329341 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 29966199 # Number of Instructions Simulated +system.cpu1.committedOps 38116499 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 7.869270 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 7.869270 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.127077 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.127077 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 270334360 # number of integer regfile reads +system.cpu1.int_regfile_writes 43344614 # number of integer regfile writes +system.cpu1.fp_regfile_reads 45048 # number of floating regfile reads +system.cpu1.fp_regfile_writes 42280 # number of floating regfile writes +system.cpu1.misc_regfile_reads 130449609 # number of misc regfile reads +system.cpu1.misc_regfile_writes 594503 # number of misc regfile writes system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. @@ -2103,17 +2125,17 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1734475259291 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1734475259291 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1734475259291 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1734475259291 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1734330533049 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1734330533049 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1734330533049 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1734330533049 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 83062 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 83063 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/system.terminal Binary files differindex 973d0288c..46f8f01b2 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/system.terminal diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini index 04fd84fb1..1ab0a28be 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini @@ -20,13 +20,14 @@ eventq_index=0 init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/dist/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/home/stever/m5/m5_system_2.0b3/binaries/x86_64-vmlinux-2.6.22.9 load_addr_mask=18446744073709551615 +load_offset=0 mem_mode=timing mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -readfile=tests/halt.sh +readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh smbios_table=system.smbios_table symbolfile= work_begin_ckpt_count=0 @@ -161,6 +162,7 @@ smtLSQThreshold=100 smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 +socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false @@ -1535,7 +1537,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/disks/linux-x86.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1558,7 +1560,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/disks/linux-bigswap2.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] @@ -1747,9 +1749,9 @@ system=system pio=system.iobus.master[9] [system.physmem] -type=SimpleDRAM +type=DRAMCtrl activation_limit=4 -addr_mapping=RaBaChCo +addr_mapping=RoRaBaChCo banks_per_rank=8 burst_length=8 channels=1 @@ -1760,27 +1762,33 @@ device_rowbuffer_size=1024 devices_per_rank=8 eventq_index=0 in_addr_map=true +max_accesses_per_row=16 mem_sched_policy=frfcfs +min_writes_per_switch=16 null=false -page_policy=open +page_policy=open_adaptive range=0:134217727 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 +tCK=1250 tCL=13750 tRAS=35000 tRCD=13750 tREFI=7800000 -tRFC=300000 +tRFC=260000 tRP=13750 -tRRD=6250 +tRRD=6000 +tRTP=7500 +tRTW=2500 +tWR=15000 tWTR=7500 -tXAW=40000 -write_buffer_size=32 -write_high_thresh_perc=70 -write_low_thresh_perc=0 +tXAW=30000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 port=system.membus.master[3] [system.smbios_table] diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout index 4c2ae2163..86995b769 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:10:34 -gem5 started Jan 22 2014 22:15:55 -gem5 executing on u200540-lin -command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing +gem5 compiled Jun 21 2014 11:13:07 +gem5 started Jun 21 2014 22:16:40 +gem5 executing on phenom +command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/binaries/x86_64-vmlinux-2.6.22.9 +info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/x86_64-vmlinux-2.6.22.9 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5133933067000 because m5_exit instruction encountered +Exiting @ tick 5137926173000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 4f3c9bdb3..aa05e00b0 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,136 +1,136 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.141960 # Number of seconds simulated -sim_ticks 5141959613000 # Number of ticks simulated -final_tick 5141959613000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.137926 # Number of seconds simulated +sim_ticks 5137926173000 # Number of ticks simulated +final_tick 5137926173000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 152486 # Simulator instruction rate (inst/s) -host_op_rate 301416 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1922658876 # Simulator tick rate (ticks/s) -host_mem_usage 770128 # Number of bytes of host memory used -host_seconds 2674.40 # Real time elapsed on the host -sim_insts 407807707 # Number of instructions simulated -sim_ops 806107146 # Number of ops (including micro ops) simulated +host_inst_rate 165389 # Simulator instruction rate (inst/s) +host_op_rate 326926 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2083966500 # Simulator tick rate (ticks/s) +host_mem_usage 742788 # Number of bytes of host memory used +host_seconds 2465.46 # Real time elapsed on the host +sim_insts 407759509 # Number of instructions simulated +sim_ops 806020953 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::pc.south_bridge.ide 2476992 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3840 # Number of bytes read from this memory +system.physmem.bytes_read::pc.south_bridge.ide 2427584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3776 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1035072 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10749056 # Number of bytes read from this memory -system.physmem.bytes_read::total 14265280 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1035072 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1035072 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9521344 # Number of bytes written to this memory -system.physmem.bytes_written::total 9521344 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 38703 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 60 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu.inst 1035776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10808512 # Number of bytes read from this memory +system.physmem.bytes_read::total 14275968 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1035776 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1035776 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9555328 # Number of bytes written to this memory +system.physmem.bytes_written::total 9555328 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 37931 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 59 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16173 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 167954 # Number of read requests responded to by this memory -system.physmem.num_reads::total 222895 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 148771 # Number of write requests responded to by this memory -system.physmem.num_writes::total 148771 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 481721 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 747 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu.inst 16184 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 168883 # Number of read requests responded to by this memory +system.physmem.num_reads::total 223062 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 149302 # Number of write requests responded to by this memory +system.physmem.num_writes::total 149302 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 472483 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 735 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 201299 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2090459 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2774289 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 201299 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 201299 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1851696 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1851696 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1851696 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 481721 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 747 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 201594 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2103672 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2778547 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 201594 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 201594 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1859764 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1859764 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1859764 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 472483 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 735 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 201299 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2090459 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4625984 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 222895 # Number of read requests accepted -system.physmem.writeReqs 148771 # Number of write requests accepted -system.physmem.readBursts 222895 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 148771 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 14256576 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8704 # Total number of bytes read from write queue -system.physmem.bytesWritten 9520064 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 14265280 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 9521344 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 136 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::cpu.inst 201594 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2103672 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4638310 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 223062 # Number of read requests accepted +system.physmem.writeReqs 149302 # Number of write requests accepted +system.physmem.readBursts 223062 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 149302 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 14267968 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8000 # Total number of bytes read from write queue +system.physmem.bytesWritten 9553728 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 14275968 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 9555328 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 125 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 1680 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 14406 # Per bank write bursts -system.physmem.perBankRdBursts::1 13692 # Per bank write bursts -system.physmem.perBankRdBursts::2 14137 # Per bank write bursts -system.physmem.perBankRdBursts::3 13444 # Per bank write bursts -system.physmem.perBankRdBursts::4 14027 # Per bank write bursts -system.physmem.perBankRdBursts::5 13372 # Per bank write bursts -system.physmem.perBankRdBursts::6 13359 # Per bank write bursts -system.physmem.perBankRdBursts::7 13805 # Per bank write bursts -system.physmem.perBankRdBursts::8 13762 # Per bank write bursts -system.physmem.perBankRdBursts::9 13592 # Per bank write bursts -system.physmem.perBankRdBursts::10 13956 # Per bank write bursts -system.physmem.perBankRdBursts::11 13564 # Per bank write bursts -system.physmem.perBankRdBursts::12 14528 # Per bank write bursts -system.physmem.perBankRdBursts::13 14698 # Per bank write bursts -system.physmem.perBankRdBursts::14 14291 # Per bank write bursts -system.physmem.perBankRdBursts::15 14126 # Per bank write bursts -system.physmem.perBankWrBursts::0 9807 # Per bank write bursts -system.physmem.perBankWrBursts::1 9166 # Per bank write bursts -system.physmem.perBankWrBursts::2 9421 # Per bank write bursts -system.physmem.perBankWrBursts::3 8835 # Per bank write bursts -system.physmem.perBankWrBursts::4 9422 # Per bank write bursts -system.physmem.perBankWrBursts::5 8917 # Per bank write bursts -system.physmem.perBankWrBursts::6 8763 # Per bank write bursts -system.physmem.perBankWrBursts::7 9221 # Per bank write bursts -system.physmem.perBankWrBursts::8 9116 # Per bank write bursts -system.physmem.perBankWrBursts::9 9134 # Per bank write bursts -system.physmem.perBankWrBursts::10 9470 # Per bank write bursts -system.physmem.perBankWrBursts::11 8904 # Per bank write bursts -system.physmem.perBankWrBursts::12 9718 # Per bank write bursts -system.physmem.perBankWrBursts::13 9806 # Per bank write bursts -system.physmem.perBankWrBursts::14 9580 # Per bank write bursts -system.physmem.perBankWrBursts::15 9471 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 1775 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 14642 # Per bank write bursts +system.physmem.perBankRdBursts::1 13963 # Per bank write bursts +system.physmem.perBankRdBursts::2 14587 # Per bank write bursts +system.physmem.perBankRdBursts::3 13341 # Per bank write bursts +system.physmem.perBankRdBursts::4 14143 # Per bank write bursts +system.physmem.perBankRdBursts::5 13526 # Per bank write bursts +system.physmem.perBankRdBursts::6 13007 # Per bank write bursts +system.physmem.perBankRdBursts::7 13123 # Per bank write bursts +system.physmem.perBankRdBursts::8 13660 # Per bank write bursts +system.physmem.perBankRdBursts::9 13743 # Per bank write bursts +system.physmem.perBankRdBursts::10 13657 # Per bank write bursts +system.physmem.perBankRdBursts::11 13667 # Per bank write bursts +system.physmem.perBankRdBursts::12 14668 # Per bank write bursts +system.physmem.perBankRdBursts::13 14755 # Per bank write bursts +system.physmem.perBankRdBursts::14 14289 # Per bank write bursts +system.physmem.perBankRdBursts::15 14166 # Per bank write bursts +system.physmem.perBankWrBursts::0 10056 # Per bank write bursts +system.physmem.perBankWrBursts::1 9321 # Per bank write bursts +system.physmem.perBankWrBursts::2 9829 # Per bank write bursts +system.physmem.perBankWrBursts::3 8830 # Per bank write bursts +system.physmem.perBankWrBursts::4 9558 # Per bank write bursts +system.physmem.perBankWrBursts::5 8986 # Per bank write bursts +system.physmem.perBankWrBursts::6 8593 # Per bank write bursts +system.physmem.perBankWrBursts::7 8747 # Per bank write bursts +system.physmem.perBankWrBursts::8 8969 # Per bank write bursts +system.physmem.perBankWrBursts::9 9193 # Per bank write bursts +system.physmem.perBankWrBursts::10 9160 # Per bank write bursts +system.physmem.perBankWrBursts::11 9087 # Per bank write bursts +system.physmem.perBankWrBursts::12 9894 # Per bank write bursts +system.physmem.perBankWrBursts::13 9881 # Per bank write bursts +system.physmem.perBankWrBursts::14 9649 # Per bank write bursts +system.physmem.perBankWrBursts::15 9524 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 5141959559500 # Total gap between requests +system.physmem.totGap 5137926057000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 222895 # Read request sizes (log2) +system.physmem.readPktSize::6 223062 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 148771 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 173187 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 13769 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5947 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3181 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3035 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3711 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 3299 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 3149 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2487 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1947 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1694 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1507 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1113 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1005 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 833 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 764 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 718 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 557 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 456 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 376 # What read queue length does an incoming req see +system.physmem.writePktSize::6 149302 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 173856 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 14004 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5938 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3116 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2938 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3695 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 3277 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 3105 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2401 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1802 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1616 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1416 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1120 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1019 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 848 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 763 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 690 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 540 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 420 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 347 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 24 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -156,223 +156,225 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1667 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1818 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6657 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6807 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6895 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7018 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7687 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8492 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8899 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9209 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 9322 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 9232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 9176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1873 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1747 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1906 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1843 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1738 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1562 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1321 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1831 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6323 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6727 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6895 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7003 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7385 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8610 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8913 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 9245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 9225 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 9112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 9115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1831 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1783 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1762 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1670 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1529 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1335 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 1057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 845 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 632 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 486 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 857 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 652 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 516 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 372 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 118 # What write queue length does an incoming req see system.physmem.wrQLenPdf::49 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 1 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 74587 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 318.776409 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 185.138812 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 338.199277 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 28275 37.91% 37.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 16828 22.56% 60.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 7503 10.06% 70.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 4244 5.69% 76.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3057 4.10% 80.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2068 2.77% 83.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1382 1.85% 84.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1175 1.58% 86.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10055 13.48% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 74587 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 8285 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 26.884007 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 527.034010 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 8284 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::50 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 75897 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 313.867900 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 181.633012 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 336.529129 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 29529 38.91% 38.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 16915 22.29% 61.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 7566 9.97% 71.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 4259 5.61% 76.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2981 3.93% 80.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2008 2.65% 83.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1459 1.92% 85.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1171 1.54% 86.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 10009 13.19% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 75897 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 8307 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 26.835320 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 526.600201 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 8306 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 8285 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 8285 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.954255 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.428609 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 5.676130 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-17 6158 74.33% 74.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18-19 1338 16.15% 90.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-21 52 0.63% 91.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22-23 77 0.93% 92.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-25 47 0.57% 92.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26-27 55 0.66% 93.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-29 103 1.24% 94.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30-31 89 1.07% 95.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-33 47 0.57% 96.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34-35 58 0.70% 96.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-37 37 0.45% 97.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38-39 45 0.54% 97.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-41 69 0.83% 98.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42-43 27 0.33% 99.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-45 11 0.13% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46-47 16 0.19% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-49 22 0.27% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50-51 4 0.05% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-53 7 0.08% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::54-55 3 0.04% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-57 2 0.02% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::58-59 3 0.04% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-61 5 0.06% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::62-63 4 0.05% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-65 3 0.04% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::66-67 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-81 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-89 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 8285 # Writes before turning the bus around for reads -system.physmem.totQLat 4923822749 # Total ticks spent queuing -system.physmem.totMemAccLat 9100553999 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1113795000 # Total ticks spent in databus transfers -system.physmem.avgQLat 22103.81 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 8307 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 8307 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.970025 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.437156 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 5.734930 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-17 6174 74.32% 74.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18-19 1334 16.06% 90.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-21 66 0.79% 91.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22-23 64 0.77% 91.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-25 51 0.61% 92.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26-27 45 0.54% 93.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-29 113 1.36% 94.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30-31 87 1.05% 95.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-33 56 0.67% 96.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34-35 56 0.67% 96.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-37 34 0.41% 97.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38-39 52 0.63% 97.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-41 60 0.72% 98.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42-43 31 0.37% 98.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-45 10 0.12% 99.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::46-47 10 0.12% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-49 28 0.34% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50-51 7 0.08% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-53 4 0.05% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::54-55 3 0.04% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-57 5 0.06% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::58-59 4 0.05% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-61 2 0.02% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::62-63 3 0.04% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-65 2 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::66-67 1 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-69 2 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-77 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::78-79 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::90-91 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 8307 # Writes before turning the bus around for reads +system.physmem.totQLat 4966355250 # Total ticks spent queuing +system.physmem.totMemAccLat 9146424000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1114685000 # Total ticks spent in databus transfers +system.physmem.avgQLat 22276.94 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 40853.81 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.77 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.85 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.77 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.85 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 41026.94 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.78 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.86 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.78 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.86 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.83 # Average write queue length when enqueuing -system.physmem.readRowHits 186870 # Number of row buffer hits during reads -system.physmem.writeRowHits 110052 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.89 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.97 # Row buffer hit rate for writes -system.physmem.avgGap 13834893.59 # Average gap between requests -system.physmem.pageHitRate 79.92 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 4934274417750 # Time in different power states -system.physmem.memoryStateTime::REF 171701140000 # Time in different power states +system.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.93 # Average write queue length when enqueuing +system.physmem.readRowHits 185691 # Number of row buffer hits during reads +system.physmem.writeRowHits 110625 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.29 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.09 # Row buffer hit rate for writes +system.physmem.avgGap 13798127.79 # Average gap between requests +system.physmem.pageHitRate 79.60 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 4930575819000 # Time in different power states +system.physmem.memoryStateTime::REF 171566460000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 35983950250 # Time in different power states +system.physmem.memoryStateTime::ACT 35783789000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 5095093 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 662466 # Transaction distribution -system.membus.trans_dist::ReadResp 662464 # Transaction distribution -system.membus.trans_dist::WriteReq 13782 # Transaction distribution -system.membus.trans_dist::WriteResp 13782 # Transaction distribution -system.membus.trans_dist::Writeback 148771 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2188 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1699 # Transaction distribution -system.membus.trans_dist::ReadExReq 179320 # Transaction distribution -system.membus.trans_dist::ReadExResp 179319 # Transaction distribution -system.membus.trans_dist::MessageReq 1645 # Transaction distribution -system.membus.trans_dist::MessageResp 1645 # Transaction distribution -system.membus.trans_dist::BadAddressError 2 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3290 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3290 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471084 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775082 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 475021 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 4 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1721191 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 132996 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 132996 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1857477 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6580 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::total 6580 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241828 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550161 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18322944 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 20114933 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5463680 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 5463680 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 25585193 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 25585193 # Total data (bytes) -system.membus.snoop_data_through_bus 613568 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 250592000 # Layer occupancy (ticks) +system.membus.throughput 5117506 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 662560 # Transaction distribution +system.membus.trans_dist::ReadResp 662552 # Transaction distribution +system.membus.trans_dist::WriteReq 13764 # Transaction distribution +system.membus.trans_dist::WriteResp 13764 # Transaction distribution +system.membus.trans_dist::Writeback 149302 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2261 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1794 # Transaction distribution +system.membus.trans_dist::ReadExReq 180173 # Transaction distribution +system.membus.trans_dist::ReadExResp 180170 # Transaction distribution +system.membus.trans_dist::MessageReq 1643 # Transaction distribution +system.membus.trans_dist::MessageResp 1643 # Transaction distribution +system.membus.trans_dist::BadAddressError 8 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3286 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3286 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471036 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775076 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 477605 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 16 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1723733 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 132228 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 132228 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1859247 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6572 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::total 6572 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241801 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550149 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18417024 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 20208974 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5414272 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 5414272 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 25629818 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 25629818 # Total data (bytes) +system.membus.snoop_data_through_bus 663552 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 250523000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 583283000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 583102000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3290000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3286000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 1610033997 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 1620731000 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 3000 # Layer occupancy (ticks) +system.membus.reqLayer4.occupancy 9000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1645000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1643000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 3152758703 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 3164060842 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer4.occupancy 429601748 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 429649499 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47571 # number of replacements -system.iocache.tags.tagsinuse 0.128712 # Cycle average of tags in use +system.iocache.tags.replacements 47575 # number of replacements +system.iocache.tags.tagsinuse 0.116331 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47587 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47591 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 4992977133000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.128712 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.008045 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.008045 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 4992948576000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.116331 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007271 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.007271 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428634 # Number of tag accesses -system.iocache.tags.data_accesses 428634 # Number of data accesses -system.iocache.ReadReq_misses::pc.south_bridge.ide 906 # number of ReadReq misses -system.iocache.ReadReq_misses::total 906 # number of ReadReq misses +system.iocache.tags.tag_accesses 428670 # Number of tag accesses +system.iocache.tags.data_accesses 428670 # Number of data accesses +system.iocache.ReadReq_misses::pc.south_bridge.ide 910 # number of ReadReq misses +system.iocache.ReadReq_misses::total 910 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47626 # number of demand (read+write) misses -system.iocache.demand_misses::total 47626 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47626 # number of overall misses -system.iocache.overall_misses::total 47626 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 147491196 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 147491196 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 11109159898 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 11109159898 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 11256651094 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 11256651094 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 11256651094 # number of overall miss cycles -system.iocache.overall_miss_latency::total 11256651094 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 906 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 906 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47630 # number of demand (read+write) misses +system.iocache.demand_misses::total 47630 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47630 # number of overall misses +system.iocache.overall_misses::total 47630 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 151620185 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 151620185 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 11039278588 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 11039278588 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 11190898773 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 11190898773 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 11190898773 # number of overall miss cycles +system.iocache.overall_miss_latency::total 11190898773 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 910 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 910 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47626 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47626 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47626 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47626 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47630 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47630 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47630 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47630 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -381,40 +383,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 162793.814570 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 162793.814570 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 237781.675899 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 237781.675899 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 236355.165120 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 236355.165120 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 236355.165120 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 236355.165120 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 159859 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 166615.587912 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 166615.587912 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 236285.928682 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 236285.928682 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 234954.834621 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 234954.834621 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 234954.834621 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 234954.834621 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 159238 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 14672 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 14593 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.895515 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.911944 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 906 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 906 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 910 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 910 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 47626 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 47626 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 47626 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 47626 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 100353196 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 100353196 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8677810402 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8677810402 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8778163598 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8778163598 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8778163598 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8778163598 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 47630 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 47630 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 47630 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 47630 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 104274685 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 104274685 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8607905090 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8607905090 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8712179775 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8712179775 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8712179775 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8712179775 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -423,18 +425,18 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 110765.116998 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 110765.116998 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 185740.804837 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 185740.804837 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 184314.525637 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 184314.525637 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 184314.525637 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 184314.525637 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 114587.565934 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 114587.565934 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 184244.543878 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 184244.543878 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 182913.705123 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 182913.705123 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 182913.705123 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 182913.705123 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. @@ -444,22 +446,22 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.throughput 637150 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 225562 # Transaction distribution -system.iobus.trans_dist::ReadResp 225562 # Transaction distribution -system.iobus.trans_dist::WriteReq 57606 # Transaction distribution -system.iobus.trans_dist::WriteResp 57606 # Transaction distribution -system.iobus.trans_dist::MessageReq 1645 # Transaction distribution -system.iobus.trans_dist::MessageResp 1645 # Transaction distribution +system.iobus.throughput 637650 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 225557 # Transaction distribution +system.iobus.trans_dist::ReadResp 225557 # Transaction distribution +system.iobus.trans_dist::WriteReq 57591 # Transaction distribution +system.iobus.trans_dist::WriteResp 57591 # Transaction distribution +system.iobus.trans_dist::MessageReq 1643 # Transaction distribution +system.iobus.trans_dist::MessageResp 1643 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 427356 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 427354 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) @@ -469,21 +471,21 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 471084 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95252 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95252 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3290 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3290 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 569626 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 471036 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95260 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95260 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3286 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3286 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 569582 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 213678 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 213677 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) @@ -493,20 +495,20 @@ system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_3.pio system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 241828 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027792 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027792 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6580 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6580 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 3276200 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 3276200 # Total data (bytes) -system.iobus.reqLayer0.occupancy 3930346 # Layer occupancy (ticks) +system.iobus.tot_pkt_size_system.bridge.master::total 241801 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027824 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027824 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6572 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6572 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 3276197 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 3276197 # Total data (bytes) +system.iobus.reqLayer0.occupancy 3919904 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 8889000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 8851000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -518,7 +520,7 @@ system.iobus.reqLayer7.occupancy 50000 # La system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 213679000 # Layer occupancy (ticks) +system.iobus.reqLayer9.occupancy 213678000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) @@ -536,273 +538,274 @@ system.iobus.reqLayer16.occupancy 9000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 424685346 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 424855274 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 460198000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 460165000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 53671252 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 53596501 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1645000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1643000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 85633263 # Number of BP lookups -system.cpu.branchPred.condPredicted 85633263 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 884686 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 79267379 # Number of BTB lookups -system.cpu.branchPred.BTBHits 77548662 # Number of BTB hits +system.cpu.branchPred.lookups 85854110 # Number of BP lookups +system.cpu.branchPred.condPredicted 85854110 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 890492 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 79431123 # Number of BTB lookups +system.cpu.branchPred.BTBHits 77651636 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.831747 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1440338 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 180105 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.759711 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1460640 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 181048 # Number of incorrect RAS predictions. system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.numCycles 453234333 # number of cpu cycles simulated +system.cpu.numCycles 452853570 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 25483623 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 422835891 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85633263 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 78989000 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 162683938 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4002747 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 108573 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 70983982 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 43526 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 92374 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 193 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8487571 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 384793 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 2466 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 262469836 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.181706 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.411661 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 25683785 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 423946474 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85854110 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 79112276 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 162997927 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4233083 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 105681 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 69250991 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 42777 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 91487 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 266 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8611652 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 409614 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 2534 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 261469410 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.201181 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.413215 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 100201994 38.18% 38.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1531970 0.58% 38.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 71824716 27.36% 66.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 909581 0.35% 66.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1572022 0.60% 67.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2391233 0.91% 67.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1015593 0.39% 68.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1327813 0.51% 68.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 81694914 31.13% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 98890192 37.82% 37.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1558006 0.60% 38.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 71842115 27.48% 65.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 921619 0.35% 66.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1585920 0.61% 66.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2431144 0.93% 67.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1036910 0.40% 68.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1345104 0.51% 68.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 81858400 31.31% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 262469836 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.188938 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.932930 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 29410093 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 68121182 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 158520657 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3344277 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3073627 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 832752013 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 987 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3073627 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 32108860 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 42947155 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 12423337 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 158815296 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 13101561 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 829828808 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 20476 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 6069323 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 5155919 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 991491995 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1800757525 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1107104494 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 110 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 964043985 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27448008 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 454148 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 459927 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 29603104 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 16744391 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 9834089 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1098610 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 922271 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 825029586 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1184674 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 821050392 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 152353 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 19282759 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 29404306 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 129800 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 262469836 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 3.128170 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.399623 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 261469410 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.189585 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.936167 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 29046589 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 66961601 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 159616384 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2548340 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3296496 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 834624632 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 895 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3296496 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 31320829 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 35759496 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 12826241 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 159575235 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 18691113 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 831621243 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 271968 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 7201596 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 103405 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 9490411 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 993545092 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1805477878 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1109904628 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 111 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 963933701 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 29611389 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 457228 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 464601 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 24223020 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 16966534 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 9968316 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1221781 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 988150 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 826572087 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1194475 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 821819105 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 208862 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 20915933 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 32275833 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 139879 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 261469410 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 3.143079 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.407689 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 76068971 28.98% 28.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 15764450 6.01% 34.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 10561557 4.02% 39.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7380977 2.81% 41.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 75732754 28.85% 70.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3744713 1.43% 72.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72297753 27.55% 99.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 770490 0.29% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 148171 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 76437702 29.23% 29.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 14614697 5.59% 34.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 10065724 3.85% 38.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7027094 2.69% 41.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 75658650 28.94% 70.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3979218 1.52% 71.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72575299 27.76% 99.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 879014 0.34% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 232012 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 262469836 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 261469410 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 351121 33.32% 33.32% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 242 0.02% 33.34% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 235 0.02% 33.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 33.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 33.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 33.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.36% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 548827 52.08% 85.44% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 153397 14.56% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 395534 35.48% 35.48% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 246 0.02% 35.50% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 260 0.02% 35.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 35.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 35.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 35.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 35.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.53% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 578947 51.93% 87.46% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 139812 12.54% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 310274 0.04% 0.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 793553745 96.65% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 150127 0.02% 96.71% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 124319 0.02% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 17682976 2.15% 98.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9228951 1.12% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 313841 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 794169455 96.64% 96.67% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 150148 0.02% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 125336 0.02% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 17790783 2.16% 98.87% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9269542 1.13% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 821050392 # Type of FU issued -system.cpu.iq.rate 1.811536 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1053822 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001284 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1905885622 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 845507474 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 817131376 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 174 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 198 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 821819105 # Type of FU issued +system.cpu.iq.rate 1.814757 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1114799 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001357 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1906543911 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 848693742 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 817833447 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 176 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 182 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 50 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 821793858 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 822619981 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 82 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1694774 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 1787791 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2743773 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 18703 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 12097 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1404751 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2974113 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 16000 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 13012 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1545780 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1931902 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 12205 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1935112 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 35450 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3073627 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 31062869 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2159597 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 826214260 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 248339 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 16744391 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 9834089 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 689465 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1620816 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 13300 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 12097 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 498594 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 510068 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1008662 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 819639552 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 17378500 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1410839 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3296496 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 15966541 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 12762115 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 827766562 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 204474 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 16966534 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 9968316 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 698992 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1766485 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 10560079 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 13012 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 503157 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 519909 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1023066 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 820377360 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 17471183 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1441744 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 26423310 # number of memory reference insts executed -system.cpu.iew.exec_branches 83104184 # Number of branches executed -system.cpu.iew.exec_stores 9044810 # Number of stores executed -system.cpu.iew.exec_rate 1.808423 # Inst execution rate -system.cpu.iew.wb_sent 819235043 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 817131426 # cumulative count of insts written-back -system.cpu.iew.wb_producers 638623234 # num instructions producing a value -system.cpu.iew.wb_consumers 1043962608 # num instructions consuming a value +system.cpu.iew.exec_refs 26545601 # number of memory reference insts executed +system.cpu.iew.exec_branches 83164783 # Number of branches executed +system.cpu.iew.exec_stores 9074418 # Number of stores executed +system.cpu.iew.exec_rate 1.811573 # Inst execution rate +system.cpu.iew.wb_sent 819943769 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 817833497 # cumulative count of insts written-back +system.cpu.iew.wb_producers 640559141 # num instructions producing a value +system.cpu.iew.wb_consumers 1047723157 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.802890 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.611730 # average fanout of values written-back +system.cpu.iew.wb_rate 1.805956 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.611382 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 19998130 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1054874 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 894775 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 259396209 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 3.107629 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.863349 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 21640086 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1054596 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 900184 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 258172914 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 3.122020 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.868515 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 87828444 33.86% 33.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11868241 4.58% 38.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3842531 1.48% 39.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 74752258 28.82% 68.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2384729 0.92% 69.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1479281 0.57% 70.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 859408 0.33% 70.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 70845236 27.31% 97.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5536081 2.13% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 87519981 33.90% 33.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11178946 4.33% 38.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3524931 1.37% 39.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74556840 28.88% 68.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2487891 0.96% 69.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1503617 0.58% 70.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 865491 0.34% 70.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 70822706 27.43% 97.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5712511 2.21% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 259396209 # Number of insts commited each cycle -system.cpu.commit.committedInsts 407807707 # Number of instructions committed -system.cpu.commit.committedOps 806107146 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 258172914 # Number of insts commited each cycle +system.cpu.commit.committedInsts 407759509 # Number of instructions committed +system.cpu.commit.committedOps 806020953 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22429955 # Number of memory references committed -system.cpu.commit.loads 14000617 # Number of loads committed -system.cpu.commit.membars 474711 # Number of memory barriers committed -system.cpu.commit.branches 82167469 # Number of branches committed +system.cpu.commit.refs 22414956 # Number of memory references committed +system.cpu.commit.loads 13992420 # Number of loads committed +system.cpu.commit.membars 474659 # Number of memory barriers committed +system.cpu.commit.branches 82156165 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 734952495 # Number of committed integer instructions. -system.cpu.commit.function_calls 1155627 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 174437 0.02% 0.02% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 783236239 97.16% 97.18% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 144862 0.02% 97.20% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 121653 0.02% 97.22% # Class of committed instruction +system.cpu.commit.int_insts 734866809 # Number of committed integer instructions. +system.cpu.commit.function_calls 1155346 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 174342 0.02% 0.02% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 783165220 97.16% 97.19% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 144784 0.02% 97.20% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 121651 0.02% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 97.22% # Class of committed instruction @@ -829,213 +832,213 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.22% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 14000617 1.74% 98.95% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 8429338 1.05% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 13992420 1.74% 98.96% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 8422536 1.04% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 806107146 # Class of committed instruction -system.cpu.commit.bw_lim_events 5536081 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 806020953 # Class of committed instruction +system.cpu.commit.bw_lim_events 5712511 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1079887016 # The number of ROB reads -system.cpu.rob.rob_writes 1655298855 # The number of ROB writes -system.cpu.timesIdled 1259672 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 190764497 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9830690598 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 407807707 # Number of Instructions Simulated -system.cpu.committedOps 806107146 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.111392 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.111392 # CPI: Total CPI of All Threads -system.cpu.ipc 0.899772 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.899772 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1088844162 # number of integer regfile reads -system.cpu.int_regfile_writes 653876789 # number of integer regfile writes +system.cpu.rob.rob_reads 1080043164 # The number of ROB reads +system.cpu.rob.rob_writes 1658634797 # The number of ROB writes +system.cpu.timesIdled 1275471 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 191384160 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9823003775 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 407759509 # Number of Instructions Simulated +system.cpu.committedOps 806020953 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.110590 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.110590 # CPI: Total CPI of All Threads +system.cpu.ipc 0.900422 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.900422 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1089597141 # number of integer regfile reads +system.cpu.int_regfile_writes 654482969 # number of integer regfile writes system.cpu.fp_regfile_reads 50 # number of floating regfile reads -system.cpu.cc_regfile_reads 415644137 # number of cc regfile reads -system.cpu.cc_regfile_writes 321521730 # number of cc regfile writes -system.cpu.misc_regfile_reads 264115519 # number of misc regfile reads -system.cpu.misc_regfile_writes 402672 # number of misc regfile writes -system.cpu.toL2Bus.throughput 53624827 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 3015737 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3015197 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 13782 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 13782 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1584798 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2253 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2253 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 336401 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 289692 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 2 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1908205 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6128379 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 19318 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 159676 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8215578 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61059136 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207801717 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 607680 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5615104 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 275083637 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 275059381 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 677312 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 4044441846 # Layer occupancy (ticks) +system.cpu.cc_regfile_reads 415870022 # number of cc regfile reads +system.cpu.cc_regfile_writes 321677512 # number of cc regfile writes +system.cpu.misc_regfile_reads 264445635 # number of misc regfile reads +system.cpu.misc_regfile_writes 402422 # number of misc regfile writes +system.cpu.toL2Bus.throughput 53724216 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 3026047 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3025482 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 13764 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 13764 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1581183 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2322 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2322 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 334322 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 287613 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 8 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1928223 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6126020 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18717 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 156212 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8229172 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61697728 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207710542 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 574144 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5436928 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 275419342 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 275396046 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 635008 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 4043112921 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 568500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 546000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1434613560 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1449735220 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3141764506 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3140330868 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 14738244 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 14620748 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 107967138 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 106945143 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 953583 # number of replacements -system.cpu.icache.tags.tagsinuse 509.342760 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 7479724 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 954095 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 7.839601 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 147639960250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.342760 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.994810 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.994810 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 963566 # number of replacements +system.cpu.icache.tags.tagsinuse 509.311037 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 7590970 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 964078 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 7.873813 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 147613206250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.311037 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.994748 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.994748 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 225 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 177 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 231 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 180 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 9441724 # Number of tag accesses -system.cpu.icache.tags.data_accesses 9441724 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 7479724 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7479724 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7479724 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7479724 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7479724 # number of overall hits -system.cpu.icache.overall_hits::total 7479724 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1007844 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1007844 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1007844 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1007844 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1007844 # number of overall misses -system.cpu.icache.overall_misses::total 1007844 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14035582232 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14035582232 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14035582232 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14035582232 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14035582232 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14035582232 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8487568 # 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number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14179701612 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14179701612 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 8611650 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8611650 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 8611650 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 8611650 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 8611650 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 8611650 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.118523 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.118523 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.118523 # 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average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12144.301809 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12144.301809 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12144.301809 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12144.301809 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12144.301809 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 56484 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 56484 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 56484 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 56484 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 56484 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 56484 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 964196 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 964196 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 964196 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 964196 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 964196 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 964196 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11690907021 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11690907021 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11690907021 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11690907021 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11690907021 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11690907021 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.111964 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.111964 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.111964 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.111964 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.111964 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.111964 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12125.031654 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12125.031654 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12125.031654 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12125.031654 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12125.031654 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12125.031654 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.tags.replacements 8939 # number of replacements -system.cpu.itb_walker_cache.tags.tagsinuse 6.031288 # Cycle average of tags in use -system.cpu.itb_walker_cache.tags.total_refs 21114 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.tags.sampled_refs 8953 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.tags.avg_refs 2.358316 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.tags.warmup_cycle 5104803925000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.031288 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.376956 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_percent::total 0.376956 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id -system.cpu.itb_walker_cache.tags.tag_accesses 71741 # Number of tag accesses -system.cpu.itb_walker_cache.tags.data_accesses 71741 # Number of data accesses -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 21134 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 21134 # 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Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id +system.cpu.itb_walker_cache.tags.tag_accesses 68718 # Number of tag accesses +system.cpu.itb_walker_cache.tags.data_accesses 68718 # Number of data accesses +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 19738 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 19738 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 21136 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 21136 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 21136 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 21136 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 9823 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 9823 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 9823 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 9823 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 9823 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 9823 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 107949749 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 107949749 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 107949749 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 107949749 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 107949749 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 107949749 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 30957 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 30957 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 19740 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 19740 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 19740 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 19740 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 9746 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 9746 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 9746 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 9746 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 9746 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 9746 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 105945749 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 105945749 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 105945749 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 105945749 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 105945749 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 105945749 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 29484 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 29484 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 30959 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 30959 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 30959 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 30959 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.317311 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.317311 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.317291 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.317291 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.317291 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.317291 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10989.488853 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10989.488853 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10989.488853 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10989.488853 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10989.488853 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10989.488853 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 29486 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 29486 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 29486 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 29486 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.330552 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.330552 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.330530 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.330530 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.330530 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.330530 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10870.690437 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10870.690437 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10870.690437 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10870.690437 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10870.690437 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10870.690437 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1044,85 +1047,85 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 1983 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 1983 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 9823 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 9823 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 9823 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 9823 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 9823 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 9823 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 88296261 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 88296261 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 88296261 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 88296261 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 88296261 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 88296261 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.317311 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.317311 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.317291 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.317291 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.317291 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.317291 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8988.726560 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8988.726560 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8988.726560 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8988.726560 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8988.726560 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8988.726560 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 1636 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 1636 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 9746 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 9746 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 9746 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 9746 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 9746 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 9746 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 86450253 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 86450253 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 86450253 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 86450253 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 86450253 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 86450253 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.330552 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.330552 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.330530 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.330530 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.330530 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.330530 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8870.331726 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8870.331726 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8870.331726 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8870.331726 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8870.331726 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8870.331726 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.tags.replacements 70861 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 12.940736 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 90199 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.sampled_refs 70877 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.272613 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 5101635052500 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 12.940736 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.808796 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_percent::total 0.808796 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 16 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.replacements 70197 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 14.820412 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 92434 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 70211 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.316517 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 5101611575500 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 14.820412 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.926276 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.926276 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dtb_walker_cache.tags.tag_accesses 396218 # Number of tag accesses -system.cpu.dtb_walker_cache.tags.data_accesses 396218 # Number of data accesses -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 90199 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 90199 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 90199 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 90199 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 90199 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 90199 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 71940 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 71940 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 71940 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 71940 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 71940 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 71940 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 878693205 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 878693205 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 878693205 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 878693205 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 878693205 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 878693205 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 162139 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 162139 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 162139 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 162139 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 162139 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 162139 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.443693 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.443693 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.443693 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.443693 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.443693 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.443693 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12214.250834 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12214.250834 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12214.250834 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12214.250834 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12214.250834 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12214.250834 # average overall miss latency +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id +system.cpu.dtb_walker_cache.tags.tag_accesses 398660 # Number of tag accesses +system.cpu.dtb_walker_cache.tags.data_accesses 398660 # Number of data accesses +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 92440 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 92440 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 92440 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 92440 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 92440 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 92440 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 71260 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 71260 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 71260 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 71260 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 71260 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 71260 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 875246716 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 875246716 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 875246716 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 875246716 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 875246716 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 875246716 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 163700 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 163700 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 163700 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 163700 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 163700 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 163700 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.435308 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.435308 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.435308 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.435308 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.435308 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.435308 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12282.440584 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12282.440584 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12282.440584 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12282.440584 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12282.440584 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12282.440584 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1131,153 +1134,153 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 22838 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 22838 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 71940 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 71940 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 71940 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 71940 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 71940 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 71940 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 734698929 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 734698929 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 734698929 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 734698929 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 734698929 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 734698929 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.443693 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.443693 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.443693 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.443693 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.443693 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.443693 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10212.662344 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10212.662344 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10212.662344 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10212.662344 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10212.662344 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10212.662344 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 20047 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 20047 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 71260 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 71260 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 71260 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 71260 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 71260 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 71260 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 732616430 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 732616430 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 732616430 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 732616430 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 732616430 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 732616430 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.435308 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.435308 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.435308 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.435308 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.435308 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.435308 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10280.892927 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10280.892927 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10280.892927 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10280.892927 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10280.892927 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10280.892927 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1658766 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.994288 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 19002910 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1659278 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11.452517 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 1657713 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.996506 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 19009946 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1658225 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.464033 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 39778250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.994288 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999989 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 511.996506 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999993 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999993 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 201 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 295 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 164 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 328 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 87874474 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 87874474 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 10896738 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 10896738 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8103479 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8103479 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 19000217 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 19000217 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 19000217 # number of overall hits -system.cpu.dcache.overall_hits::total 19000217 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2237270 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2237270 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 316309 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 316309 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2553579 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2553579 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2553579 # number of overall misses -system.cpu.dcache.overall_misses::total 2553579 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 32758938054 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 32758938054 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 12034849454 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 12034849454 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 44793787508 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 44793787508 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 44793787508 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 44793787508 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13134008 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13134008 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8419788 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8419788 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21553796 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21553796 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21553796 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21553796 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.170342 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.170342 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037567 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037567 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.118475 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.118475 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.118475 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.118475 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14642.371307 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14642.371307 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38047.761695 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38047.761695 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 17541.571069 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 17541.571069 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 17541.571069 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 17541.571069 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 388234 # number of cycles access was blocked +system.cpu.dcache.tags.tag_accesses 87793833 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 87793833 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 10909808 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 10909808 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8097329 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8097329 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 19007137 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 19007137 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 19007137 # number of overall hits +system.cpu.dcache.overall_hits::total 19007137 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2211100 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2211100 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 315662 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 315662 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2526762 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2526762 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2526762 # number of overall misses +system.cpu.dcache.overall_misses::total 2526762 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 32878750930 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 32878750930 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 12078727781 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 12078727781 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 44957478711 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 44957478711 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 44957478711 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 44957478711 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13120908 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13120908 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8412991 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8412991 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21533899 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21533899 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21533899 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21533899 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.168517 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.168517 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037521 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037521 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.117339 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.117339 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.117339 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.117339 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14869.861576 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14869.861576 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38264.750844 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38264.750844 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 17792.526052 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 17792.526052 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 17792.526052 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 17792.526052 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 428041 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 42159 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 36530 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.208805 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.717520 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1559977 # number of writebacks -system.cpu.dcache.writebacks::total 1559977 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 867558 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 867558 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 24476 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 24476 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 892034 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 892034 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 892034 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 892034 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1369712 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1369712 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 291833 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 291833 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1661545 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1661545 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1661545 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1661545 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17680675970 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 17680675970 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11138475501 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11138475501 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28819151471 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 28819151471 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28819151471 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 28819151471 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97364609500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97364609500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2539074000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2539074000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99903683500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 99903683500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.104287 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.104287 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034660 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034660 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.077088 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.077088 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077088 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.077088 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12908.316471 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12908.316471 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38167.292599 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38167.292599 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17344.791427 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 17344.791427 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17344.791427 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 17344.791427 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1559500 # number of writebacks +system.cpu.dcache.writebacks::total 1559500 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 840350 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 840350 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 25845 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 25845 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 866195 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 866195 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 866195 # 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mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000682 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016788 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026357 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021759 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.825337 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.825337 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.464940 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.464940 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000909 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000682 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016788 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102450 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.069072 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000909 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000682 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016788 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102450 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.069072 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 70131.355932 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 63050 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63692.250479 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64941.993254 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64563.238983 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10640.164927 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10640.164927 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56955.740006 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56955.740006 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 72079.166667 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63201.326063 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66455.955442 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 65453.757057 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10641.745265 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10641.745265 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57113.589053 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57113.589053 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 70131.355932 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 63050 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63692.250479 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58659.135444 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59103.321516 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 72079.166667 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63201.326063 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59100.085878 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59460.405678 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 70131.355932 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 63050 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63692.250479 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58659.135444 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59103.321516 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63201.326063 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59100.085878 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59460.405678 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal index 8b1d3ad58..61d45995b 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal @@ -28,7 +28,7 @@ Built 1 zonelists. Total pages: 30612 Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
Initializing CPU#0
PID hash table entries: 512 (order: 9, 4096 bytes)
-time.c: Detected 2000.008 MHz processor.
+time.c: Detected 1999.999 MHz processor.
Console: colour dummy device 80x25
console handover: boot [earlyser0] -> real [ttyS0]
Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)
@@ -44,7 +44,7 @@ ACPI: Core revision 20070126 ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]
ACPI: Unable to load the System Description Tables
Using local APIC timer interrupts.
-result 7812560
+result 7812524
Detected 7.812 MHz APIC timer.
NET: Registered protocol family 16
PCI: Using configuration type 1
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini index 42bed7716..bf000969d 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini @@ -20,14 +20,14 @@ eventq_index=0 init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/home/stever/m5/m5_system_2.0b3/binaries/x86_64-vmlinux-2.6.22.9 load_addr_mask=18446744073709551615 load_offset=0 mem_mode=atomic mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -readfile=/z/stever/hg/gem5/tests/halt.sh +readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh smbios_table=system.smbios_table symbolfile= work_begin_ckpt_count=0 @@ -1597,7 +1597,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/m5/system/disks/linux-x86.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1620,7 +1620,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr index 246bb0fe6..56f83c534 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr @@ -3,6 +3,7 @@ warn: Reading current count from inactive timer. warn: Sockets disabled, not accepting gdb connections warn: Don't know what interrupt to clear for console. warn: x86 cpuid: unknown family 0xbacc +warn: x86 cpuid: unknown family 0xbacc warn: x86 cpuid: unknown family 0x8086 warn: x86 cpuid: unknown family 0x8086 warn: x86 cpuid: unimplemented function 8 diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout index ad22be7e5..6a57a8844 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 12 2014 12:50:47 -gem5 started May 12 2014 15:35:34 -gem5 executing on zizzer -command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full -re /z/stever/hg/gem5/tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full +gem5 compiled Jun 21 2014 11:13:07 +gem5 started Jun 21 2014 22:18:32 +gem5 executing on phenom +command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full Global frequency set at 1000000000000 ticks per second 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt index 80c9b1902..307acd090 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt @@ -1,156 +1,160 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.133875 # Number of seconds simulated -sim_ticks 5133874673500 # Number of ticks simulated -final_tick 5133874673500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.135764 # Number of seconds simulated +sim_ticks 5135763847500 # Number of ticks simulated +final_tick 5135763847500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 236000 # Simulator instruction rate (inst/s) -host_op_rate 469116 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4968557721 # Simulator tick rate (ticks/s) -host_mem_usage 928744 # Number of bytes of host memory used -host_seconds 1033.27 # Real time elapsed on the host -sim_insts 243852609 # Number of instructions simulated -sim_ops 484724493 # Number of ops (including micro ops) simulated +host_inst_rate 259782 # Simulator instruction rate (inst/s) +host_op_rate 516376 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5470381356 # Simulator tick rate (ticks/s) +host_mem_usage 959692 # Number of bytes of host memory used +host_seconds 938.83 # Real time elapsed on the host +sim_insts 243891279 # Number of instructions simulated +sim_ops 484789360 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::pc.south_bridge.ide 2445440 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 500480 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5911104 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 139776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1689280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 1344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 309696 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2752128 # Number of bytes read from this memory -system.physmem.bytes_read::total 13749568 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 500480 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 139776 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 309696 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 949952 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9083392 # Number of bytes written to this memory -system.physmem.bytes_written::total 9083392 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 38210 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 7820 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 92361 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2184 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 26395 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 21 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 4839 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 43002 # Number of read requests responded to by this memory -system.physmem.num_reads::total 214837 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 141928 # Number of write requests responded to by this memory -system.physmem.num_writes::total 141928 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 476334 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 97486 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1151392 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 27226 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 329046 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 262 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 60324 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 536072 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2678205 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 97486 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 27226 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 60324 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 185036 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1769305 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1769305 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1769305 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 476334 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 97486 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1151392 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 27226 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 329046 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 262 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 60324 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 536072 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4447510 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 96612 # Number of read requests accepted -system.physmem.writeReqs 73475 # Number of write requests accepted -system.physmem.readBursts 96612 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 73475 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 6177024 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6144 # Total number of bytes read from write queue -system.physmem.bytesWritten 4701248 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 6183168 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4702400 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 96 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::pc.south_bridge.ide 2442432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 470912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 6169536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 114240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1582592 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 2240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 379456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2632640 # Number of bytes read from this memory +system.physmem.bytes_read::total 13794368 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 470912 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 114240 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 379456 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 964608 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9131520 # Number of bytes written to this memory +system.physmem.bytes_written::total 9131520 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 38163 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 7358 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 96399 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1785 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 24728 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 35 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 5929 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 41135 # Number of read requests responded to by this memory +system.physmem.num_reads::total 215537 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 142680 # Number of write requests responded to by this memory +system.physmem.num_writes::total 142680 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 475573 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 91693 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1201289 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 12 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 22244 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 308151 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 436 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 73885 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 512609 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2685943 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 91693 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 22244 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 73885 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 187822 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1778026 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1778026 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1778026 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 475573 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 91693 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1201289 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 12 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 22244 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 308151 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 436 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 73885 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 512609 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4463968 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 94056 # Number of read requests accepted +system.physmem.writeReqs 72760 # Number of write requests accepted +system.physmem.readBursts 94056 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 72760 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 6015488 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 4096 # Total number of bytes read from write queue +system.physmem.bytesWritten 4656640 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 6019584 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4656640 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 64 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 831 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 5404 # Per bank write bursts -system.physmem.perBankRdBursts::1 5964 # Per bank write bursts -system.physmem.perBankRdBursts::2 6149 # Per bank write bursts -system.physmem.perBankRdBursts::3 6338 # Per bank write bursts -system.physmem.perBankRdBursts::4 5414 # Per bank write bursts -system.physmem.perBankRdBursts::5 6001 # Per bank write bursts -system.physmem.perBankRdBursts::6 5201 # Per bank write bursts -system.physmem.perBankRdBursts::7 6053 # Per bank write bursts -system.physmem.perBankRdBursts::8 5779 # Per bank write bursts -system.physmem.perBankRdBursts::9 5783 # Per bank write bursts -system.physmem.perBankRdBursts::10 5919 # Per bank write bursts -system.physmem.perBankRdBursts::11 5801 # Per bank write bursts -system.physmem.perBankRdBursts::12 6766 # Per bank write bursts -system.physmem.perBankRdBursts::13 6809 # Per bank write bursts -system.physmem.perBankRdBursts::14 6844 # Per bank write bursts -system.physmem.perBankRdBursts::15 6291 # Per bank write bursts -system.physmem.perBankWrBursts::0 4307 # Per bank write bursts -system.physmem.perBankWrBursts::1 4604 # Per bank write bursts -system.physmem.perBankWrBursts::2 4694 # Per bank write bursts -system.physmem.perBankWrBursts::3 4750 # Per bank write bursts -system.physmem.perBankWrBursts::4 4088 # Per bank write bursts -system.physmem.perBankWrBursts::5 4371 # Per bank write bursts -system.physmem.perBankWrBursts::6 3767 # Per bank write bursts -system.physmem.perBankWrBursts::7 4522 # Per bank write bursts -system.physmem.perBankWrBursts::8 4168 # Per bank write bursts -system.physmem.perBankWrBursts::9 4368 # Per bank write bursts -system.physmem.perBankWrBursts::10 4606 # Per bank write bursts -system.physmem.perBankWrBursts::11 4444 # Per bank write bursts -system.physmem.perBankWrBursts::12 5448 # Per bank write bursts -system.physmem.perBankWrBursts::13 5248 # Per bank write bursts -system.physmem.perBankWrBursts::14 5481 # Per bank write bursts -system.physmem.perBankWrBursts::15 4591 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 766 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 5609 # Per bank write bursts +system.physmem.perBankRdBursts::1 5668 # Per bank write bursts +system.physmem.perBankRdBursts::2 5585 # Per bank write bursts +system.physmem.perBankRdBursts::3 5594 # Per bank write bursts +system.physmem.perBankRdBursts::4 6037 # Per bank write bursts +system.physmem.perBankRdBursts::5 6612 # Per bank write bursts +system.physmem.perBankRdBursts::6 5733 # Per bank write bursts +system.physmem.perBankRdBursts::7 5990 # Per bank write bursts +system.physmem.perBankRdBursts::8 5523 # Per bank write bursts +system.physmem.perBankRdBursts::9 5460 # Per bank write bursts +system.physmem.perBankRdBursts::10 5647 # Per bank write bursts +system.physmem.perBankRdBursts::11 6128 # Per bank write bursts +system.physmem.perBankRdBursts::12 6059 # Per bank write bursts +system.physmem.perBankRdBursts::13 6267 # Per bank write bursts +system.physmem.perBankRdBursts::14 6194 # Per bank write bursts +system.physmem.perBankRdBursts::15 5886 # Per bank write bursts +system.physmem.perBankWrBursts::0 4545 # Per bank write bursts +system.physmem.perBankWrBursts::1 4402 # Per bank write bursts +system.physmem.perBankWrBursts::2 4127 # Per bank write bursts +system.physmem.perBankWrBursts::3 4299 # Per bank write bursts +system.physmem.perBankWrBursts::4 4675 # Per bank write bursts +system.physmem.perBankWrBursts::5 5126 # Per bank write bursts +system.physmem.perBankWrBursts::6 4327 # Per bank write bursts +system.physmem.perBankWrBursts::7 4679 # Per bank write bursts +system.physmem.perBankWrBursts::8 4360 # Per bank write bursts +system.physmem.perBankWrBursts::9 4207 # Per bank write bursts +system.physmem.perBankWrBursts::10 4528 # Per bank write bursts +system.physmem.perBankWrBursts::11 4822 # Per bank write bursts +system.physmem.perBankWrBursts::12 4836 # Per bank write bursts +system.physmem.perBankWrBursts::13 4641 # Per bank write bursts +system.physmem.perBankWrBursts::14 4944 # Per bank write bursts +system.physmem.perBankWrBursts::15 4242 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 5132874544500 # Total gap between requests +system.physmem.numWrRetry 1 # Number of times write queue was full causing retry +system.physmem.totGap 5131947184500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 96612 # Read request sizes (log2) +system.physmem.readPktSize::6 94056 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 73475 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 73469 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4666 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2797 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1617 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1564 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1988 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1759 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1657 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1283 # What read queue length does an incoming req see +system.physmem.writePktSize::6 72760 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 71094 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4372 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2882 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1652 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1622 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1995 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1751 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1697 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1317 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 996 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 876 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 745 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 587 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 557 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 459 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 400 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 371 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 290 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 228 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 192 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 893 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 759 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 598 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 528 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 422 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 379 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 352 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 273 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 218 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 184 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -161,464 +165,474 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 60 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 57 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 57 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 52 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 53 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 991 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1067 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3324 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 3456 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 3620 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1038 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2990 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 3405 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 3645 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 3779 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4073 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4198 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4250 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4441 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4429 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4453 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4398 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4414 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 960 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 921 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 979 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 929 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 852 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 724 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 573 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 466 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 383 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 211 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 35709 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 304.633118 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 178.344584 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 328.042030 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 13828 38.72% 38.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 8395 23.51% 62.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 3582 10.03% 72.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1962 5.49% 77.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1409 3.95% 81.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 988 2.77% 84.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 701 1.96% 86.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 566 1.59% 88.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4278 11.98% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 35709 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4100 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.539756 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 117.618727 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-255 4089 99.73% 99.73% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::256-511 8 0.20% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-767 1 0.02% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2560-2815 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::6656-6911 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4100 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4100 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.916341 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.808533 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 6.372443 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-1 61 1.49% 1.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::2-3 8 0.20% 1.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-5 2 0.05% 1.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::6-7 3 0.07% 1.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-9 1 0.02% 1.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::10-11 1 0.02% 1.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-13 1 0.02% 1.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::14-15 5 0.12% 2.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-17 2769 67.54% 69.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18-19 821 20.02% 89.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-21 36 0.88% 90.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22-23 38 0.93% 91.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-25 31 0.76% 92.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26-27 30 0.73% 92.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-29 54 1.32% 94.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30-31 53 1.29% 95.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-33 24 0.59% 96.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34-35 28 0.68% 96.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-37 12 0.29% 97.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38-39 22 0.54% 97.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-41 34 0.83% 98.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42-43 16 0.39% 98.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-45 10 0.24% 99.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46-47 6 0.15% 99.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-49 8 0.20% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50-51 2 0.05% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-53 4 0.10% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::54-55 5 0.12% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-57 2 0.05% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::58-59 2 0.05% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-61 1 0.02% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::62-63 8 0.20% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::66-67 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::78-79 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4100 # Writes before turning the bus around for reads -system.physmem.totQLat 2438372750 # Total ticks spent queuing -system.physmem.totMemAccLat 4248047750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 482580000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25263.92 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::25 4031 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4380 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4369 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4401 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4387 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4409 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1056 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1028 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1031 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 961 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 898 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 802 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 688 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 557 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 463 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 343 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 3 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 35723 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 298.746690 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 173.799684 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 327.095227 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14318 40.08% 40.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 8282 23.18% 63.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 3507 9.82% 73.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1954 5.47% 78.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1307 3.66% 82.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 922 2.58% 84.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 623 1.74% 86.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 530 1.48% 88.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4280 11.98% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 35723 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 3978 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.627954 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 119.433357 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-255 3969 99.77% 99.77% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::256-511 7 0.18% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2560-2815 1 0.03% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::6656-6911 1 0.03% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 3978 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 3978 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.290598 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.208175 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 6.685696 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-1 45 1.13% 1.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::2-3 5 0.13% 1.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-5 3 0.08% 1.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::6-7 4 0.10% 1.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::10-11 1 0.03% 1.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::14-15 5 0.13% 1.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-17 2627 66.04% 67.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18-19 818 20.56% 88.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-21 28 0.70% 88.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22-23 32 0.80% 89.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-25 32 0.80% 90.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26-27 35 0.88% 91.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-29 65 1.63% 93.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30-31 48 1.21% 94.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-33 35 0.88% 95.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34-35 29 0.73% 95.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-37 29 0.73% 96.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38-39 26 0.65% 97.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-41 31 0.78% 97.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42-43 18 0.45% 98.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-45 10 0.25% 98.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::46-47 17 0.43% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-49 8 0.20% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50-51 6 0.15% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-53 2 0.05% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::54-55 2 0.05% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-57 7 0.18% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::58-59 1 0.03% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-61 3 0.08% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::62-63 4 0.10% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::66-67 2 0.05% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 3978 # Writes before turning the bus around for reads +system.physmem.totQLat 2424873249 # Total ticks spent queuing +system.physmem.totMemAccLat 4187223249 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 469960000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25798.72 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44013.92 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.20 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.92 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.20 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.92 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 44548.72 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.17 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.91 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.17 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.91 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 7.46 # Average write queue length when enqueuing -system.physmem.readRowHits 79177 # Number of row buffer hits during reads -system.physmem.writeRowHits 55086 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.04 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.97 # Row buffer hit rate for writes -system.physmem.avgGap 30177935.67 # Average gap between requests -system.physmem.pageHitRate 78.98 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 4939989054000 # Time in different power states -system.physmem.memoryStateTime::REF 171431260000 # Time in different power states +system.physmem.avgWrQLen 6.97 # Average write queue length when enqueuing +system.physmem.readRowHits 76538 # Number of row buffer hits during reads +system.physmem.writeRowHits 54491 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.43 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.89 # Row buffer hit rate for writes +system.physmem.avgGap 30764118.46 # Average gap between requests +system.physmem.pageHitRate 78.58 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 4942425043001 # Time in different power states +system.physmem.memoryStateTime::REF 171494180000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 22454242000 # Time in different power states +system.physmem.memoryStateTime::ACT 21844559499 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 6437004 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 422289 # Transaction distribution -system.membus.trans_dist::ReadResp 422287 # Transaction distribution -system.membus.trans_dist::WriteReq 6118 # Transaction distribution -system.membus.trans_dist::WriteResp 6118 # Transaction distribution -system.membus.trans_dist::Writeback 73475 # Transaction distribution -system.membus.trans_dist::UpgradeReq 843 # Transaction distribution -system.membus.trans_dist::UpgradeResp 843 # Transaction distribution -system.membus.trans_dist::ReadExReq 76388 # Transaction distribution -system.membus.trans_dist::ReadExResp 76388 # Transaction distribution -system.membus.trans_dist::MessageReq 850 # Transaction distribution -system.membus.trans_dist::MessageResp 850 # Transaction distribution +system.membus.throughput 6452408 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 421921 # Transaction distribution +system.membus.trans_dist::ReadResp 421919 # Transaction distribution +system.membus.trans_dist::WriteReq 5915 # Transaction distribution +system.membus.trans_dist::WriteResp 5915 # Transaction distribution +system.membus.trans_dist::Writeback 72760 # Transaction distribution +system.membus.trans_dist::UpgradeReq 778 # Transaction distribution +system.membus.trans_dist::UpgradeResp 778 # Transaction distribution +system.membus.trans_dist::ReadExReq 75224 # Transaction distribution +system.membus.trans_dist::ReadExResp 75224 # Transaction distribution +system.membus.trans_dist::MessageReq 825 # Transaction distribution +system.membus.trans_dist::MessageResp 825 # Transaction distribution system.membus.trans_dist::BadAddressError 2 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 1700 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 1700 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 308658 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 497514 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 204215 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 1650 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 1650 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 308134 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 497586 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 196326 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 4 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1010391 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 69253 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 69253 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1081344 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 3400 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::total 3400 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 158115 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 995025 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 8047552 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 9200692 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2838016 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 2838016 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 12042108 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 32720690 # Total data (bytes) -system.membus.snoop_data_through_bus 326080 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 162128500 # Layer occupancy (ticks) +system.membus.pkt_count_system.l2c.mem_side::total 1002050 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72232 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72232 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1075932 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 3300 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::total 3300 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 157715 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 995169 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 7734720 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 8887604 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2941504 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 2941504 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 11832408 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 32744958 # Total data (bytes) +system.membus.snoop_data_through_bus 393088 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 161596500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 315102000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 315113000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1700000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1650000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 806327999 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 794070497 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks) +system.membus.reqLayer4.occupancy 2000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 850000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 825000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1598914090 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1569908183 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer4.occupancy 224687998 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 236956000 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 103794 # number of replacements -system.l2c.tags.tagsinuse 64810.608353 # Cycle average of tags in use -system.l2c.tags.total_refs 3657966 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 167984 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 21.775681 # Average number of references to valid blocks. +system.l2c.tags.replacements 104346 # number of replacements +system.l2c.tags.tagsinuse 64811.945905 # Cycle average of tags in use +system.l2c.tags.total_refs 3669840 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 168730 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 21.749778 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 51486.278563 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.125055 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 1295.377972 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4270.696448 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 302.542141 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1483.932036 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 7.824361 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1349.140567 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 4614.691210 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.785618 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 51276.768453 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.121941 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 1221.298902 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4234.138382 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 0.002961 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 249.507225 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 1581.676468 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 7.253356 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1493.843089 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 4747.335130 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.782421 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.019766 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.065166 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.004616 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.022643 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000119 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.020586 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.070415 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.988931 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 64190 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 474 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3206 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 7166 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 53256 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.979462 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 33587388 # Number of tag accesses -system.l2c.tags.data_accesses 33587388 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 20605 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 11266 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 339595 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 520668 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 10906 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 6430 # 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average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 65028.571429 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63366.377635 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 59959.493595 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 59502.614100 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -750,44 +770,44 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 47575 # number of replacements -system.iocache.tags.tagsinuse 0.089403 # Cycle average of tags in use +system.iocache.tags.replacements 47573 # number of replacements +system.iocache.tags.tagsinuse 0.095086 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47591 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47589 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 5000209950509 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.089403 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005588 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.005588 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 5000199085509 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.095086 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005943 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.005943 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428670 # Number of tag accesses -system.iocache.tags.data_accesses 428670 # Number of data accesses -system.iocache.ReadReq_misses::pc.south_bridge.ide 910 # number of ReadReq misses -system.iocache.ReadReq_misses::total 910 # number of ReadReq misses +system.iocache.tags.tag_accesses 428652 # Number of tag accesses +system.iocache.tags.data_accesses 428652 # Number of data accesses +system.iocache.ReadReq_misses::pc.south_bridge.ide 908 # number of ReadReq misses +system.iocache.ReadReq_misses::total 908 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47630 # number of demand (read+write) misses -system.iocache.demand_misses::total 47630 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47630 # number of overall misses -system.iocache.overall_misses::total 47630 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 131527041 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 131527041 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 5824382656 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 5824382656 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 5955909697 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 5955909697 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 5955909697 # number of overall miss cycles -system.iocache.overall_miss_latency::total 5955909697 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 910 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 910 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47628 # number of demand (read+write) misses +system.iocache.demand_misses::total 47628 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47628 # number of overall misses +system.iocache.overall_misses::total 47628 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 130701291 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 130701291 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 6017123258 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 6017123258 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 6147824549 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 6147824549 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 6147824549 # number of overall miss cycles +system.iocache.overall_miss_latency::total 6147824549 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 908 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 908 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47630 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47630 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47630 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47630 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47628 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47628 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47628 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47628 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -796,60 +816,60 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 144535.209890 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 144535.209890 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 124665.724658 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 124665.724658 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 125045.343208 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 125045.343208 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 125045.343208 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 125045.343208 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 88795 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 143944.153084 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 143944.153084 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 128791.165625 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 128791.165625 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 129080.048480 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 129080.048480 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 129080.048480 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 129080.048480 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 86048 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 8200 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7909 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.828659 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.879757 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 733 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 733 # number of ReadReq MSHR misses -system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 24176 # number of WriteReq MSHR misses -system.iocache.WriteReq_mshr_misses::total 24176 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 24909 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 24909 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 24909 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 24909 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 93385041 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 93385041 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 4566242660 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 4566242660 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4659627701 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 4659627701 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4659627701 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 4659627701 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.805495 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.805495 # mshr miss rate for ReadReq accesses -system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 0.517466 # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::total 0.517466 # mshr miss rate for WriteReq accesses -system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.522969 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.522969 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.522969 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.522969 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 127401.147340 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 127401.147340 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 188875.027300 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 188875.027300 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 187066.028383 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 187066.028383 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 187066.028383 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 187066.028383 # average overall mshr miss latency +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 735 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 735 # number of ReadReq MSHR misses +system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 25536 # number of WriteReq MSHR misses +system.iocache.WriteReq_mshr_misses::total 25536 # number of WriteReq MSHR misses +system.iocache.demand_mshr_misses::pc.south_bridge.ide 26271 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 26271 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 26271 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 26271 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 92456791 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 92456791 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 4688241758 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 4688241758 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4780698549 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 4780698549 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4780698549 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 4780698549 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.809471 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.809471 # mshr miss rate for ReadReq accesses +system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 0.546575 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total 0.546575 # mshr miss rate for WriteReq accesses +system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.551587 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.551587 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.551587 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.551587 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 125791.552381 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 125791.552381 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 183593.427240 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 183593.427240 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 181976.268471 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 181976.268471 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 181976.268471 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 181976.268471 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. @@ -859,510 +879,511 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.toL2Bus.throughput 52260442 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 1795853 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 1795321 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 6118 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 6118 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 903975 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 804 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 804 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 176511 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 152342 # Transaction distribution +system.toL2Bus.throughput 52407719 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 1793633 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 1793101 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 5915 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 5915 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 899960 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 730 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 730 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 172146 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 146613 # Transaction distribution system.toL2Bus.trans_dist::BadAddressError 2 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1006951 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3618137 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 34540 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 139444 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 4799072 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 32221504 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 120018356 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 123320 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 517264 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 152880444 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 268161042 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 137520 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 5048228823 # Layer occupancy (ticks) +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 999818 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3602290 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 34349 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 141650 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 4778107 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 31993152 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119401652 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 120808 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 525848 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 152041460 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 269011854 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 141816 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 5025953302 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 945000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 936000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2267749080 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2251918114 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4703679799 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4677619434 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 19140467 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 19272449 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 74891774 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 76057203 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 1277477 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 149797 # Transaction distribution -system.iobus.trans_dist::ReadResp 149797 # Transaction distribution -system.iobus.trans_dist::WriteReq 29441 # Transaction distribution -system.iobus.trans_dist::WriteResp 29441 # Transaction distribution -system.iobus.trans_dist::MessageReq 850 # Transaction distribution -system.iobus.trans_dist::MessageResp 850 # Transaction distribution +system.iobus.throughput 1276582 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 149714 # Transaction distribution +system.iobus.trans_dist::ReadResp 149714 # Transaction distribution +system.iobus.trans_dist::WriteReq 30624 # Transaction distribution +system.iobus.trans_dist::WriteResp 30624 # Transaction distribution +system.iobus.trans_dist::MessageReq 825 # Transaction distribution +system.iobus.trans_dist::MessageResp 825 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 36 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 5466 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 4890 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 558 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 38 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 588 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 30 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 18 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 287110 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 224 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 287208 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 156 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 86 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 13026 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 4 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2064 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 308658 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 49818 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 49818 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 1700 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 1700 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 360176 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 308134 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 52542 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 52542 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 1650 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 1650 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 362326 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 3084 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 2760 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 4 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 279 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 19 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 294 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 15 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 12 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 9 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 143555 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 448 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 143604 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 312 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 43 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 6513 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 2 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4128 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 158115 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 1583592 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 1583592 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3400 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 3400 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 1745107 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 6558405 # Total data (bytes) -system.iobus.reqLayer0.occupancy 2044244 # Layer occupancy (ticks) +system.iobus.tot_pkt_size_system.bridge.master::total 157715 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 1670648 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 1670648 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3300 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 3300 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 1831663 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 6556225 # Total data (bytes) +system.iobus.reqLayer0.occupancy 1987954 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 28000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 4518000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 4046000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer5.occupancy 367000 # Layer occupancy (ticks) +system.iobus.reqLayer5.occupancy 387000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 33000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 27000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 21000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer8.occupancy 18000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 143556000 # Layer occupancy (ticks) +system.iobus.reqLayer9.occupancy 143605000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 178000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 124000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer11.occupancy 86000 # Layer occupancy (ticks) system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 9750000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 9774000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 4000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 220209699 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 232428549 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 1032000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 303393000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 303046000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 30099002 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 31488000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 850000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 825000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu0.numCycles 1160444400 # number of cpu cycles simulated +system.cpu0.numCycles 1167096017 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 72635405 # Number of instructions committed -system.cpu0.committedOps 147758080 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 135731001 # Number of integer alu accesses +system.cpu0.committedInsts 72932334 # Number of instructions committed +system.cpu0.committedOps 148186849 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 136173063 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 1010341 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 14309822 # number of instructions that are conditional controls -system.cpu0.num_int_insts 135731001 # number of integer instructions +system.cpu0.num_func_calls 1014433 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 14332221 # number of instructions that are conditional controls +system.cpu0.num_int_insts 136173063 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 249546871 # number of times the integer registers were read -system.cpu0.num_int_register_writes 116495894 # number of times the integer registers were written +system.cpu0.num_int_register_reads 250637191 # number of times the integer registers were read +system.cpu0.num_int_register_writes 116800630 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 84252648 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 56217158 # number of times the CC registers were written -system.cpu0.num_mem_refs 14168966 # number of memory refs -system.cpu0.num_load_insts 10366088 # Number of load instructions -system.cpu0.num_store_insts 3802878 # Number of store instructions -system.cpu0.num_idle_cycles 1101978015.213226 # Number of idle cycles -system.cpu0.num_busy_cycles 58466384.786774 # Number of busy cycles -system.cpu0.not_idle_fraction 0.050383 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.949617 # Percentage of idle cycles -system.cpu0.Branches 15683494 # Number of branches fetched -system.cpu0.op_class::No_OpClass 100234 0.07% 0.07% # Class of executed instruction -system.cpu0.op_class::IntAlu 133376064 90.27% 90.33% # Class of executed instruction -system.cpu0.op_class::IntMult 62929 0.04% 90.38% # Class of executed instruction -system.cpu0.op_class::IntDiv 50413 0.03% 90.41% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::MemRead 10366088 7.02% 97.43% # Class of executed instruction -system.cpu0.op_class::MemWrite 3802878 2.57% 100.00% # Class of executed instruction +system.cpu0.num_cc_register_reads 84487712 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 56367816 # number of times the CC registers were written +system.cpu0.num_mem_refs 14369378 # number of memory refs +system.cpu0.num_load_insts 10451844 # Number of load instructions +system.cpu0.num_store_insts 3917534 # Number of store instructions +system.cpu0.num_idle_cycles 1108227141.183960 # Number of idle cycles +system.cpu0.num_busy_cycles 58868875.816040 # Number of busy cycles +system.cpu0.not_idle_fraction 0.050440 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.949560 # Percentage of idle cycles +system.cpu0.Branches 15712912 # Number of branches fetched +system.cpu0.op_class::No_OpClass 100385 0.07% 0.07% # Class of executed instruction +system.cpu0.op_class::IntAlu 133601927 90.16% 90.23% # Class of executed instruction +system.cpu0.op_class::IntMult 62763 0.04% 90.27% # Class of executed instruction +system.cpu0.op_class::IntDiv 53014 0.04% 90.30% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::MemRead 10451844 7.05% 97.36% # Class of executed instruction +system.cpu0.op_class::MemWrite 3917534 2.64% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # 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number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 353426 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 499925 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1731523249 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4361398381 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 6092921630 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1731523249 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4361398381 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 6092921630 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1731523249 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4361398381 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 6092921630 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.003815 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.111155 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.003826 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.003815 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.111155 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.003826 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.003815 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.111155 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.003826 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11819.352002 # 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Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 5.035294 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.476186 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.513978 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.009835 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 273.563820 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 233.097338 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 5.338124 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.534304 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.455268 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.010426 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 308 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 210 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 278 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 88185539 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 88185539 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 5216887 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 2373282 # 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miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.135622 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.093511 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14231.485281 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16237.347483 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 10881.588659 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 34858.390247 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30079.869474 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 17222.814847 # average WriteReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 18717.945559 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 17655.422797 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 11868.668449 # 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miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.038599 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.037581 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.036150 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.037575 # miss rate for WriteReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.070756 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.067885 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.133005 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.092236 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.070756 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.067885 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.133005 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.092236 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14287.058948 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 15864.418213 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 10571.977280 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 32826.883677 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30575.551351 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 16393.968289 # average WriteReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 18321.478835 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 17333.894211 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 11491.423730 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 18321.478835 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 17333.894211 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 11491.423730 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 80099 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 11797 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 18060 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.722218 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 4.435161 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 1542066 # number of writebacks -system.cpu0.dcache.writebacks::total 1542066 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 371761 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 371761 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 17373 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 17373 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 389134 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 389134 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 389134 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 389134 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 223619 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 577178 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 800797 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 62158 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 90935 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 153093 # number of WriteReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 285777 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 668113 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 953890 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 285777 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 668113 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 953890 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2734176493 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 8368429033 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 11102605526 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 2032053179 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2876927496 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4908980675 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4766229672 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 11245356529 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 16011586201 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 4766229672 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 11245356529 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 16011586201 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30475246000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33186567000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63661813000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 395642000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 753351500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1148993500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 30870888000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 33939918500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 64810806500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.086110 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.118022 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.060483 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036684 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.031302 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018229 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.066595 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.085705 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.044084 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.066595 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.085705 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.044084 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12226.941776 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14498.870423 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13864.444455 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32691.740066 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 31637.185858 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32065.350310 # average WriteReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 16678.143000 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16831.518813 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16785.568777 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16678.143000 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16831.518813 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16785.568777 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 1546042 # number of writebacks +system.cpu0.dcache.writebacks::total 1546042 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 343252 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 343252 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 17347 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 17347 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 360599 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 360599 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 360599 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 360599 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 225418 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 575479 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 800897 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 62696 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 84608 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 147304 # number of WriteReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 288114 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 660087 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 948201 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 288114 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 660087 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 948201 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2768607746 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 8066658535 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 10835266281 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1923226701 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2756691504 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4679918205 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4691834447 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 10823350039 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 15515184486 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 4691834447 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 10823350039 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 15515184486 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30492689000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33165040000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63657729000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 394150500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 725206000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1119356500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 30886839500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 33890246000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 64777085500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.087511 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.118564 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.060350 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.037581 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.030000 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017533 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.067885 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.086016 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.043751 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.067885 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.086016 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.043751 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12282.105892 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14017.294350 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13528.913557 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30675.429070 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32581.924924 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31770.476056 # average WriteReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 16284.645824 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16396.853807 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16362.759042 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16284.645824 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16396.853807 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16362.759042 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1373,376 +1394,377 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 2606021866 # number of cpu cycles simulated +system.cpu1.numCycles 2604023259 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 34914129 # Number of instructions committed -system.cpu1.committedOps 67869828 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 62995297 # Number of integer alu accesses +system.cpu1.committedInsts 34762499 # Number of instructions committed +system.cpu1.committedOps 67606793 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 62736553 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 438942 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 6428622 # number of instructions that are conditional controls -system.cpu1.num_int_insts 62995297 # number of integer instructions +system.cpu1.num_func_calls 437056 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 6403696 # number of instructions that are conditional controls +system.cpu1.num_int_insts 62736553 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 116271710 # number of times the integer registers were read -system.cpu1.num_int_register_writes 54373007 # number of times the integer registers were written +system.cpu1.num_int_register_reads 115724590 # number of times the integer registers were read +system.cpu1.num_int_register_writes 54164636 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 35773638 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 26686136 # number of times the CC registers were written -system.cpu1.num_mem_refs 4480512 # number of memory refs -system.cpu1.num_load_insts 2784989 # Number of load instructions -system.cpu1.num_store_insts 1695523 # Number of store instructions -system.cpu1.num_idle_cycles 2483027076.334052 # Number of idle cycles -system.cpu1.num_busy_cycles 122994789.665948 # Number of busy cycles -system.cpu1.not_idle_fraction 0.047196 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.952804 # Percentage of idle cycles -system.cpu1.Branches 7029914 # Number of branches fetched -system.cpu1.op_class::No_OpClass 31008 0.05% 0.05% # Class of executed instruction -system.cpu1.op_class::IntAlu 63308003 93.28% 93.32% # Class of executed instruction -system.cpu1.op_class::IntMult 28040 0.04% 93.37% # Class of executed instruction -system.cpu1.op_class::IntDiv 22580 0.03% 93.40% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::MemRead 2784989 4.10% 97.50% # Class of executed instruction -system.cpu1.op_class::MemWrite 1695523 2.50% 100.00% # Class of executed instruction +system.cpu1.num_cc_register_reads 35537675 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 26584960 # number of times the CC registers were written +system.cpu1.num_mem_refs 4433444 # number of memory refs +system.cpu1.num_load_insts 2764122 # Number of load instructions +system.cpu1.num_store_insts 1669322 # Number of store instructions +system.cpu1.num_idle_cycles 2476870816.288117 # Number of idle cycles +system.cpu1.num_busy_cycles 127152442.711883 # Number of busy cycles +system.cpu1.not_idle_fraction 0.048829 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.951171 # Percentage of idle cycles +system.cpu1.Branches 7001569 # Number of branches fetched +system.cpu1.op_class::No_OpClass 28648 0.04% 0.04% # Class of executed instruction +system.cpu1.op_class::IntAlu 63095899 93.33% 93.37% # Class of executed instruction +system.cpu1.op_class::IntMult 28577 0.04% 93.41% # Class of executed instruction +system.cpu1.op_class::IntDiv 20525 0.03% 93.44% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::MemRead 2764122 4.09% 97.53% # Class of executed instruction +system.cpu1.op_class::MemWrite 1669322 2.47% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 67870143 # Class of executed instruction +system.cpu1.op_class::total 67607093 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 28758894 # Number of BP lookups -system.cpu2.branchPred.condPredicted 28758894 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 306803 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 26351534 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 25737629 # Number of BTB hits +system.cpu2.branchPred.lookups 28894520 # Number of BP lookups +system.cpu2.branchPred.condPredicted 28894520 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 314484 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 26386768 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 25807983 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 97.670325 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 530881 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 61512 # Number of incorrect RAS predictions. -system.cpu2.numCycles 154845080 # number of cpu cycles simulated +system.cpu2.branchPred.BTBHitPct 97.806533 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 541788 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 61672 # Number of incorrect RAS predictions. +system.cpu2.numCycles 154118891 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9460785 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 141747704 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 28758894 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 26268510 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 54302787 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 1434244 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 58972 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.BlockedCycles 24471854 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 4161 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 6545 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 20028 # Number of stall cycles due to pending traps -system.cpu2.fetch.IcacheWaitRetryStallCycles 224 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 3117082 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 139514 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 1749 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 89437217 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 3.124405 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 3.409858 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9526926 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 142222809 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 28894520 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 26349771 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 54464711 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 1558370 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 64917 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.BlockedCycles 23183087 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 4981 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 6096 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 25004 # Number of stall cycles due to pending traps +system.cpu2.fetch.IcacheWaitRetryStallCycles 241 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 3179586 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 151181 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 1925 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 88503258 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 3.167922 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 3.413230 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 35270123 39.44% 39.44% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 589507 0.66% 40.09% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 23704151 26.50% 66.60% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 307246 0.34% 66.94% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 603965 0.68% 67.62% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 802586 0.90% 68.51% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 334965 0.37% 68.89% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 517417 0.58% 69.47% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 27307257 30.53% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 34173678 38.61% 38.61% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 596420 0.67% 39.29% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 23721602 26.80% 66.09% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 320974 0.36% 66.45% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 619988 0.70% 67.15% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 815233 0.92% 68.07% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 353145 0.40% 68.47% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 523827 0.59% 69.07% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 27378391 30.93% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 89437217 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.185727 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.915416 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 10926187 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 23367960 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 31523393 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 1298286 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1115198 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 278635226 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 49 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 1115198 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 11921655 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 13834152 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 4411879 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 31656208 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 5292001 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 277656292 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 6764 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 2483668 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 2130930 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 331880087 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 604361998 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 371268132 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 6 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 321920244 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 9959841 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 147988 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 148926 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 11485411 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6218482 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3410117 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 341148 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 274139 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 276004640 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 412430 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 274449569 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 59781 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 7023554 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 10820295 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 55045 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 89437217 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 3.068628 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 2.396853 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 88503258 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.187482 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.922812 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 10770329 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 22316529 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 33210052 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 993418 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1230628 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 279539625 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 15 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 1230628 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 11632631 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 11620518 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 4366536 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 33251587 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 6419117 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 278526444 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 145793 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 2942087 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 39888 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 2722851 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 332982462 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 606515542 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 372413837 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 42 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 321866415 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 11116047 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 145000 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 146469 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 9034946 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6263244 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3375371 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 381006 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 309187 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 276743563 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 411647 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 274777165 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 83308 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 7862427 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 12385425 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 57804 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 88503258 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 3.104712 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 2.400001 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 26098480 29.18% 29.18% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 6131096 6.86% 36.04% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 3936751 4.40% 40.44% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 2730796 3.05% 43.49% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 25025448 27.98% 71.47% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1337810 1.50% 72.97% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 23830586 26.65% 99.61% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 291775 0.33% 99.94% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 54475 0.06% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 25772149 29.12% 29.12% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 5479119 6.19% 35.31% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 3780646 4.27% 39.58% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 2658058 3.00% 42.59% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 25098242 28.36% 70.94% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1415095 1.60% 72.54% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 23897363 27.00% 99.55% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 310729 0.35% 99.90% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 91857 0.10% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 89437217 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 88503258 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 125312 33.75% 33.75% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 120 0.03% 33.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 109 0.03% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 191005 51.44% 85.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 54802 14.76% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 130084 34.74% 34.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 34.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 103 0.03% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 196279 52.42% 87.18% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 48005 12.82% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 76601 0.03% 0.03% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 264560846 96.40% 96.42% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 54414 0.02% 96.44% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 50942 0.02% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 6508971 2.37% 98.83% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3197795 1.17% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 79957 0.03% 0.03% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 264964709 96.43% 96.46% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 54296 0.02% 96.48% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 50937 0.02% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 6495012 2.36% 98.86% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3132254 1.14% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 274449569 # Type of FU issued -system.cpu2.iq.rate 1.772414 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 371348 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001353 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 638809448 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 283444416 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 273102485 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 12 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 274744310 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 6 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 641561 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 274777165 # Type of FU issued +system.cpu2.iq.rate 1.782891 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 374471 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001363 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 638559252 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 285021199 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 273394851 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 45 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 74 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 14 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 275071659 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 20 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 655974 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 993516 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 6753 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 4280 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 500329 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1102337 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 6308 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 4079 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 550460 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 656426 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 10045 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 656385 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 7890 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1115198 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 9119918 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 823405 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 276417070 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 70631 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6218482 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3410117 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 233790 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 637954 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 3900 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 4280 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 173413 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 173644 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 347057 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 273959168 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 6398525 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 490400 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 1230628 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 6003858 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 2680102 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 277155210 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 55656 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6263266 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3375371 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 233323 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 631738 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 1840063 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 4079 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 177700 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 182074 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 359774 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 274266101 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 6377623 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 511064 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed system.cpu2.iew.exec_nop 0 # number of nop insts executed -system.cpu2.iew.exec_refs 9531292 # number of memory reference insts executed -system.cpu2.iew.exec_branches 27864904 # Number of branches executed -system.cpu2.iew.exec_stores 3132767 # Number of stores executed -system.cpu2.iew.exec_rate 1.769247 # Inst execution rate -system.cpu2.iew.wb_sent 273810478 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 273102491 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 212979431 # num instructions producing a value -system.cpu2.iew.wb_consumers 348314367 # num instructions consuming a value +system.cpu2.iew.exec_refs 9440682 # number of memory reference insts executed +system.cpu2.iew.exec_branches 27899539 # Number of branches executed +system.cpu2.iew.exec_stores 3063059 # Number of stores executed +system.cpu2.iew.exec_rate 1.779575 # Inst execution rate +system.cpu2.iew.wb_sent 274107922 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 273394865 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 213810949 # num instructions producing a value +system.cpu2.iew.wb_consumers 349940477 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.763714 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.611457 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.773922 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.610992 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 7316358 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 357385 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 309115 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 88322018 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 3.046767 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.870309 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 8157845 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 353843 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 317282 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 87272630 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 3.082246 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.874009 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 30852434 34.93% 34.93% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4395307 4.98% 39.91% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1238857 1.40% 41.31% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 24650858 27.91% 69.22% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 865215 0.98% 70.20% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 585749 0.66% 70.86% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 347954 0.39% 71.26% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 23291491 26.37% 97.63% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 2094153 2.37% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 30201439 34.61% 34.61% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4017102 4.60% 39.21% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1154677 1.32% 40.53% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 24628965 28.22% 68.75% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 905267 1.04% 69.79% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 589610 0.68% 70.47% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 344278 0.39% 70.86% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 23302755 26.70% 97.56% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 2128537 2.44% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 88322018 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 136303075 # Number of instructions committed -system.cpu2.commit.committedOps 269096585 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 87272630 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 136196446 # Number of instructions committed +system.cpu2.commit.committedOps 268995718 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8134753 # Number of memory references committed -system.cpu2.commit.loads 5224965 # Number of loads committed -system.cpu2.commit.membars 164376 # Number of memory barriers committed -system.cpu2.commit.branches 27532187 # Number of branches committed +system.cpu2.commit.refs 7985840 # Number of memory references committed +system.cpu2.commit.loads 5160929 # Number of loads committed +system.cpu2.commit.membars 163767 # Number of memory barriers committed +system.cpu2.commit.branches 27540439 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 245708361 # Number of committed integer instructions. -system.cpu2.commit.function_calls 429087 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 43848 0.02% 0.02% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 260815603 96.92% 96.94% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 52558 0.02% 96.96% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 49823 0.02% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 5224965 1.94% 98.92% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 2909788 1.08% 100.00% # Class of committed instruction +system.cpu2.commit.int_insts 245590309 # Number of committed integer instructions. +system.cpu2.commit.function_calls 428081 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 46387 0.02% 0.02% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 260861796 96.98% 96.99% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 52266 0.02% 97.01% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 49429 0.02% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 5160929 1.92% 98.95% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 2824911 1.05% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 269096585 # Class of committed instruction -system.cpu2.commit.bw_lim_events 2094153 # number cycles where commit BW limit reached +system.cpu2.commit.op_class_0::total 268995718 # Class of committed instruction +system.cpu2.commit.bw_lim_events 2128537 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 362613065 # The number of ROB reads -system.cpu2.rob.rob_writes 553944877 # The number of ROB writes -system.cpu2.timesIdled 473034 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 65407863 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 4900873955 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 136303075 # Number of Instructions Simulated -system.cpu2.committedOps 269096585 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.136035 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.136035 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.880254 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.880254 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 364552649 # number of integer regfile reads -system.cpu2.int_regfile_writes 218803003 # number of integer regfile writes -system.cpu2.fp_regfile_reads 72918 # number of floating regfile reads -system.cpu2.fp_regfile_writes 72968 # number of floating regfile writes -system.cpu2.cc_regfile_reads 139316304 # number of cc regfile reads -system.cpu2.cc_regfile_writes 107298284 # number of cc regfile writes -system.cpu2.misc_regfile_reads 88761943 # number of misc regfile reads -system.cpu2.misc_regfile_writes 132629 # number of misc regfile writes +system.cpu2.rob.rob_reads 362270810 # The number of ROB reads +system.cpu2.rob.rob_writes 555542201 # The number of ROB writes +system.cpu2.timesIdled 475518 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 65615633 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 4908375985 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 136196446 # Number of Instructions Simulated +system.cpu2.committedOps 268995718 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.131593 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.131593 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.883710 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.883710 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 364616127 # number of integer regfile reads +system.cpu2.int_regfile_writes 219111496 # number of integer regfile writes +system.cpu2.fp_regfile_reads 72926 # number of floating regfile reads +system.cpu2.fp_regfile_writes 72912 # number of floating regfile writes +system.cpu2.cc_regfile_reads 139466740 # number of cc regfile reads +system.cpu2.cc_regfile_writes 107376389 # number of cc regfile writes +system.cpu2.misc_regfile_reads 88828545 # number of misc regfile reads +system.cpu2.misc_regfile_writes 129118 # number of misc regfile writes system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal index 08dac49a9..72fbd3738 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal @@ -44,7 +44,7 @@ ACPI: Core revision 20070126 ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]
ACPI: Unable to load the System Description Tables
Using local APIC timer interrupts.
-result 7812444
+result 7812464
Detected 7.812 MHz APIC timer.
NET: Registered protocol family 16
PCI: Using configuration type 1
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