diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-08-05 04:36:29 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-08-05 04:36:29 -0400 |
| commit | 646994e599bb21459237f1d7001ff4e887f07f33 (patch) | |
| tree | 3e91d7eca0a236a3a31fb932dd57bddb353b5684 /tests/long/fs | |
| parent | 7c904d9d3faff80d724c8ab3e6f1d3815545e2f5 (diff) | |
| download | gem5-646994e599bb21459237f1d7001ff4e887f07f33.tar.xz | |
stats: Reflect current behaviour
Not sure what went wrong in the pushing of the Ruby patches, but
somehow these regressions are not updated.
Diffstat (limited to 'tests/long/fs')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt | 826 |
1 files changed, 413 insertions, 413 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt index 221f5a4a8..5b46ed4d9 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt @@ -4,13 +4,13 @@ sim_seconds 5.305855 # Nu sim_ticks 5305855051000 # Number of ticks simulated final_tick 5305855051000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 136389 # Simulator instruction rate (inst/s) -host_op_rate 261386 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6751430632 # Simulator tick rate (ticks/s) -host_mem_usage 1106140 # Number of bytes of host memory used -host_seconds 785.89 # Real time elapsed on the host -sim_insts 107186053 # Number of instructions simulated -sim_ops 205419480 # Number of ops (including micro ops) simulated +host_inst_rate 191709 # Simulator instruction rate (inst/s) +host_op_rate 367405 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9489836408 # Simulator tick rate (ticks/s) +host_mem_usage 1155664 # Number of bytes of host memory used +host_seconds 559.11 # Real time elapsed on the host +sim_insts 107186064 # Number of instructions simulated +sim_ops 205419446 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.mem_ctrls.bytes_read::ruby.dir_cntrl0 11371136 # Number of bytes read from this memory @@ -88,8 +88,8 @@ system.mem_ctrls.writePktSize::3 0 # Wr system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::6 142679 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 176703 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 67 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::0 176699 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 71 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -135,35 +135,35 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 2059 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 2790 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 8563 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 9122 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 8572 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 2068 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 2801 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 8555 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 9120 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 8578 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::20 9212 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 9228 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 8314 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 9034 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 9060 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 8413 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 8500 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 8357 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 8453 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 8029 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 8097 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 8147 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 9227 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 8319 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 9035 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 9059 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 8416 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 8503 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 8354 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 8443 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 8032 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 8092 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 8140 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::32 7952 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 108 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 106 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::34 85 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::35 89 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::36 75 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 72 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::37 64 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::38 57 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 58 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::39 48 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::40 39 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::41 28 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 37 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 29 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::42 18 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::43 9 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 10 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::44 4 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::45 2 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::46 1 # What write queue length does an incoming req see @@ -184,73 +184,73 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 60336 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 338.676213 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 200.551275 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 343.723517 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 20068 33.26% 33.26% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 14736 24.42% 57.68% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 6373 10.56% 68.25% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 3491 5.79% 74.03% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 2657 4.40% 78.44% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 1861 3.08% 81.52% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 1364 2.26% 83.78% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 1338 2.22% 86.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 8448 14.00% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 60336 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 7897 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 22.382170 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 317.489285 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::0-1023 7891 99.92% 99.92% # Reads before turning the bus around for writes +system.mem_ctrls.bytesPerActivate::samples 60326 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 338.732354 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 200.613193 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 343.695896 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 20059 33.25% 33.25% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 14736 24.43% 57.68% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 6379 10.57% 68.25% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 3472 5.76% 74.01% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 2656 4.40% 78.41% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 1882 3.12% 81.53% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 1369 2.27% 83.80% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 1326 2.20% 86.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 8447 14.00% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 60326 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 7898 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 22.379337 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 317.468114 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::0-1023 7892 99.92% 99.92% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::1024-2047 3 0.04% 99.96% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::2048-3071 1 0.01% 99.97% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::10240-11263 1 0.01% 99.99% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::25600-26623 1 0.01% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 7897 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 7897 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 18.047106 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 17.696875 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 4.065797 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 5800 73.45% 73.45% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::17 9 0.11% 73.56% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 169 2.14% 75.70% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 20 0.25% 75.95% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::20 37 0.47% 76.42% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::21 500 6.33% 82.75% # Writes before turning the bus around for reads +system.mem_ctrls.rdPerTurnAround::total 7898 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 7898 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 18.044821 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 17.697162 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 4.041167 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 5792 73.34% 73.34% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 9 0.11% 73.45% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 176 2.23% 75.68% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 20 0.25% 75.93% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::20 36 0.46% 76.39% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::21 503 6.37% 82.76% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::22 145 1.84% 84.59% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::23 43 0.54% 85.13% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::24 653 8.27% 93.40% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::25 111 1.41% 94.81% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::26 12 0.15% 94.96% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::27 19 0.24% 95.20% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::28 304 3.85% 99.05% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::23 45 0.57% 85.16% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::24 652 8.26% 93.42% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::25 114 1.44% 94.86% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::26 12 0.15% 95.01% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::27 18 0.23% 95.24% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::28 301 3.81% 99.05% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::29 7 0.09% 99.14% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::30 3 0.04% 99.18% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::31 6 0.08% 99.25% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::32 6 0.08% 99.33% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::33 2 0.03% 99.35% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::34 1 0.01% 99.37% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::35 3 0.04% 99.40% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::37 1 0.01% 99.42% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::38 3 0.04% 99.46% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::39 7 0.09% 99.54% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::40 3 0.04% 99.58% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::41 3 0.04% 99.62% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::42 6 0.08% 99.70% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::43 2 0.03% 99.72% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::44 6 0.08% 99.80% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::45 1 0.01% 99.81% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::47 1 0.01% 99.82% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::48 4 0.05% 99.87% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::51 9 0.11% 99.99% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::31 7 0.09% 99.27% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::32 6 0.08% 99.34% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::33 2 0.03% 99.37% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::34 1 0.01% 99.38% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::35 3 0.04% 99.42% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::37 1 0.01% 99.43% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::38 3 0.04% 99.47% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::39 7 0.09% 99.56% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::40 3 0.04% 99.59% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::41 3 0.04% 99.63% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::42 6 0.08% 99.71% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::43 2 0.03% 99.73% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::44 7 0.09% 99.82% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::45 1 0.01% 99.84% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::47 1 0.01% 99.85% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::48 4 0.05% 99.90% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::51 7 0.09% 99.99% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::52 1 0.01% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 7897 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 1934453242 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 5248890742 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.wrPerTurnAround::total 7898 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 1934412994 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 5248850494 # Total ticks spent from burst creation until serviced by the DRAM system.mem_ctrls.totBusLat 883850000 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 10943.33 # Average queueing delay per DRAM burst +system.mem_ctrls.avgQLat 10943.11 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 29693.33 # Average memory access latency per DRAM burst +system.mem_ctrls.avgMemAccLat 29693.11 # Average memory access latency per DRAM burst system.mem_ctrls.avgRdBW 2.13 # Average DRAM read bandwidth in MiByte/s system.mem_ctrls.avgWrBW 1.72 # Average achieved write bandwidth in MiByte/s system.mem_ctrls.avgRdBWSys 2.14 # Average system read bandwidth in MiByte/s @@ -261,71 +261,71 @@ system.mem_ctrls.busUtilRead 0.02 # Da system.mem_ctrls.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing system.mem_ctrls.avgWrQLen 24.42 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 140774 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 118177 # Number of row buffer hits during writes +system.mem_ctrls.readRowHits 140781 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 118180 # Number of row buffer hits during writes system.mem_ctrls.readRowHitRate 79.64 # Row buffer hit rate for reads system.mem_ctrls.writeRowHitRate 82.91 # Row buffer hit rate for writes system.mem_ctrls.avgGap 16562526.08 # Average gap between requests system.mem_ctrls.pageHitRate 81.10 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 229839120 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 125408250 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.actEnergy 229725720 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 125346375 # Energy for precharge commands per rank (pJ) system.mem_ctrls_0.readEnergy 694816200 # Energy for read commands per rank (pJ) system.mem_ctrls_0.writeEnergy 465892560 # Energy for write commands per rank (pJ) system.mem_ctrls_0.refreshEnergy 346552617840 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 149179147425 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 3052653894750 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 3549901616145 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 669.053686 # Core power per rank (mW) -system.mem_ctrls_0.memoryStateTime::IDLE 5078195767000 # Time in different power states +system.mem_ctrls_0.actBackEnergy 149158105020 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 3052672353000 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 3549898856715 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 669.053166 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 5078226654500 # Time in different power states system.mem_ctrls_0.memoryStateTime::REF 177174140000 # Time in different power states system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 50484766750 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 50453879250 # Time in different power states system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls_1.actEnergy 226301040 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 123477750 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.actEnergy 226338840 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 123498375 # Energy for precharge commands per rank (pJ) system.mem_ctrls_1.readEnergy 683982000 # Energy for read commands per rank (pJ) system.mem_ctrls_1.writeEnergy 457624080 # Energy for write commands per rank (pJ) system.mem_ctrls_1.refreshEnergy 346552617840 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 148537848690 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 3053216437500 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 3549798288900 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 669.034212 # Core power per rank (mW) -system.mem_ctrls_1.memoryStateTime::IDLE 5079136661250 # Time in different power states +system.mem_ctrls_1.actBackEnergy 148581064665 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 3053178528750 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 3549803654550 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 669.035223 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 5079073326250 # Time in different power states system.mem_ctrls_1.memoryStateTime::REF 177174140000 # Time in different power states system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 49544125250 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 49607460250 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu0.numCycles 10611710102 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 59039296 # Number of instructions committed -system.cpu0.committedOps 113305650 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 106292214 # Number of integer alu accesses +system.cpu0.committedInsts 59039301 # Number of instructions committed +system.cpu0.committedOps 113305603 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 106292175 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 48 # Number of float alu accesses system.cpu0.num_func_calls 1017385 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 10037497 # number of instructions that are conditional controls -system.cpu0.num_int_insts 106292214 # number of integer instructions +system.cpu0.num_conditional_control_insts 10037487 # number of instructions that are conditional controls +system.cpu0.num_int_insts 106292175 # number of integer instructions system.cpu0.num_fp_insts 48 # number of float instructions -system.cpu0.num_int_register_reads 200616677 # number of times the integer registers were read -system.cpu0.num_int_register_writes 90211380 # number of times the integer registers were written +system.cpu0.num_int_register_reads 200616462 # number of times the integer registers were read +system.cpu0.num_int_register_writes 90211252 # number of times the integer registers were written system.cpu0.num_fp_register_reads 48 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 60966470 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 44030878 # number of times the CC registers were written -system.cpu0.num_mem_refs 12456031 # number of memory refs -system.cpu0.num_load_insts 7518228 # Number of load instructions +system.cpu0.num_cc_register_reads 60966419 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 44030869 # number of times the CC registers were written +system.cpu0.num_mem_refs 12456032 # number of memory refs +system.cpu0.num_load_insts 7518229 # Number of load instructions system.cpu0.num_store_insts 4937803 # Number of store instructions -system.cpu0.num_idle_cycles 10088651138.334099 # Number of idle cycles -system.cpu0.num_busy_cycles 523058963.665901 # Number of busy cycles +system.cpu0.num_idle_cycles 10088651128.334099 # Number of idle cycles +system.cpu0.num_busy_cycles 523058973.665901 # Number of busy cycles system.cpu0.not_idle_fraction 0.049291 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.950709 # Percentage of idle cycles -system.cpu0.Branches 11416966 # Number of branches fetched -system.cpu0.op_class::No_OpClass 131109 0.12% 0.12% # Class of executed instruction -system.cpu0.op_class::IntAlu 100580264 88.77% 88.88% # Class of executed instruction +system.cpu0.Branches 11416956 # Number of branches fetched +system.cpu0.op_class::No_OpClass 131098 0.12% 0.12% # Class of executed instruction +system.cpu0.op_class::IntAlu 100580271 88.77% 88.88% # Class of executed instruction system.cpu0.op_class::IntMult 86269 0.08% 88.96% # Class of executed instruction -system.cpu0.op_class::IntDiv 57079 0.05% 89.01% # Class of executed instruction +system.cpu0.op_class::IntDiv 57035 0.05% 89.01% # Class of executed instruction system.cpu0.op_class::FloatAdd 0 0.00% 89.01% # Class of executed instruction system.cpu0.op_class::FloatCmp 0 0.00% 89.01% # Class of executed instruction system.cpu0.op_class::FloatCvt 16 0.00% 89.01% # Class of executed instruction @@ -352,41 +352,41 @@ system.cpu0.op_class::SimdFloatMisc 0 0.00% 89.01% # Cl system.cpu0.op_class::SimdFloatMult 0 0.00% 89.01% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 89.01% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 89.01% # Class of executed instruction -system.cpu0.op_class::MemRead 7514027 6.63% 95.64% # Class of executed instruction +system.cpu0.op_class::MemRead 7514028 6.63% 95.64% # Class of executed instruction system.cpu0.op_class::MemWrite 4937803 4.36% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 113306567 # Class of executed instruction +system.cpu0.op_class::total 113306520 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu1.numCycles 10608777066 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 48146757 # Number of instructions committed -system.cpu1.committedOps 92113830 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 88441893 # Number of integer alu accesses +system.cpu1.committedInsts 48146763 # Number of instructions committed +system.cpu1.committedOps 92113843 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 88441904 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 48 # Number of float alu accesses system.cpu1.num_func_calls 1752446 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 8219760 # number of instructions that are conditional controls -system.cpu1.num_int_insts 88441893 # number of integer instructions +system.cpu1.num_conditional_control_insts 8219762 # number of instructions that are conditional controls +system.cpu1.num_int_insts 88441904 # number of integer instructions system.cpu1.num_fp_insts 48 # number of float instructions -system.cpu1.num_int_register_reads 171408328 # number of times the integer registers were read -system.cpu1.num_int_register_writes 73196137 # number of times the integer registers were written +system.cpu1.num_int_register_reads 171408346 # number of times the integer registers were read +system.cpu1.num_int_register_writes 73196146 # number of times the integer registers were written system.cpu1.num_fp_register_reads 48 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 50924734 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 32745964 # number of times the CC registers were written -system.cpu1.num_mem_refs 14124901 # number of memory refs -system.cpu1.num_load_insts 9133293 # Number of load instructions +system.cpu1.num_cc_register_reads 50924744 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 32745968 # number of times the CC registers were written +system.cpu1.num_mem_refs 14124903 # number of memory refs +system.cpu1.num_load_insts 9133295 # Number of load instructions system.cpu1.num_store_insts 4991608 # Number of store instructions -system.cpu1.num_idle_cycles 10274072284.207695 # Number of idle cycles -system.cpu1.num_busy_cycles 334704781.792306 # Number of busy cycles +system.cpu1.num_idle_cycles 10274072236.220961 # Number of idle cycles +system.cpu1.num_busy_cycles 334704829.779039 # Number of busy cycles system.cpu1.not_idle_fraction 0.031550 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.968450 # Percentage of idle cycles -system.cpu1.Branches 10581617 # Number of branches fetched +system.cpu1.Branches 10581619 # Number of branches fetched system.cpu1.op_class::No_OpClass 169787 0.18% 0.18% # Class of executed instruction -system.cpu1.op_class::IntAlu 77653530 84.30% 84.49% # Class of executed instruction +system.cpu1.op_class::IntAlu 77653541 84.30% 84.49% # Class of executed instruction system.cpu1.op_class::IntMult 98479 0.11% 84.59% # Class of executed instruction system.cpu1.op_class::IntDiv 71918 0.08% 84.67% # Class of executed instruction system.cpu1.op_class::FloatAdd 0 0.00% 84.67% # Class of executed instruction @@ -415,11 +415,11 @@ system.cpu1.op_class::SimdFloatMisc 0 0.00% 84.67% # Cl system.cpu1.op_class::SimdFloatMult 0 0.00% 84.67% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 84.67% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 84.67% # Class of executed instruction -system.cpu1.op_class::MemRead 9129153 9.91% 94.58% # Class of executed instruction +system.cpu1.op_class::MemRead 9129155 9.91% 94.58% # Class of executed instruction system.cpu1.op_class::MemWrite 4991608 5.42% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 92114491 # Class of executed instruction +system.cpu1.op_class::total 92114504 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.iobus.trans_dist::ReadReq 842290 # Transaction distribution @@ -508,11 +508,11 @@ system.iobus.reqLayer0.occupancy 43500 # La system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 6500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 9032500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 9032000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 154500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 940000 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 939000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer5.occupancy 92000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) @@ -522,7 +522,7 @@ system.iobus.reqLayer7.occupancy 20247500 # La system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer8.occupancy 458718000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 1157500 # Layer occupancy (ticks) +system.iobus.reqLayer9.occupancy 1168984 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 30508000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) @@ -538,17 +538,17 @@ system.iobus.reqLayer16.occupancy 9000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 369412820 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 369423793 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 7528580 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 7540555 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 1593000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 2422900 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1846190500 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1846208467 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 57610000 # Layer occupancy (ticks) +system.iobus.respLayer4.occupancy 57630965 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 32768 # Number of bytes transfered via DMA reads (not PRD). @@ -565,48 +565,48 @@ system.pc.south_bridge.ide.disks1.dma_write_txs 1 system.ruby.clk_domain.clock 500 # Clock period in ticks system.ruby.delayHist::bucket_size 4 # delay histogram for all message system.ruby.delayHist::max_bucket 39 # delay histogram for all message -system.ruby.delayHist::samples 10891010 # delay histogram for all message -system.ruby.delayHist::mean 0.442804 # delay histogram for all message -system.ruby.delayHist::stdev 1.830720 # delay histogram for all message -system.ruby.delayHist | 10288683 94.47% 94.47% | 1238 0.01% 94.48% | 600635 5.51% 100.00% | 152 0.00% 100.00% | 257 0.00% 100.00% | 11 0.00% 100.00% | 34 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message -system.ruby.delayHist::total 10891010 # delay histogram for all message +system.ruby.delayHist::samples 10891037 # delay histogram for all message +system.ruby.delayHist::mean 0.442781 # delay histogram for all message +system.ruby.delayHist::stdev 1.830637 # delay histogram for all message +system.ruby.delayHist | 10288749 94.47% 94.47% | 1200 0.01% 94.48% | 600645 5.52% 100.00% | 149 0.00% 100.00% | 250 0.00% 100.00% | 10 0.00% 100.00% | 34 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message +system.ruby.delayHist::total 10891037 # delay histogram for all message system.ruby.outstanding_req_hist::bucket_size 1 system.ruby.outstanding_req_hist::max_bucket 9 -system.ruby.outstanding_req_hist::samples 152756591 +system.ruby.outstanding_req_hist::samples 152756607 system.ruby.outstanding_req_hist::mean 1.000166 system.ruby.outstanding_req_hist::gmean 1.000115 system.ruby.outstanding_req_hist::stdev 0.012901 -system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 152731162 99.98% 99.98% | 25429 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 152756591 +system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 152731178 99.98% 99.98% | 25429 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 152756607 system.ruby.latency_hist::bucket_size 128 system.ruby.latency_hist::max_bucket 1279 -system.ruby.latency_hist::samples 152756590 +system.ruby.latency_hist::samples 152756606 system.ruby.latency_hist::mean 3.433707 system.ruby.latency_hist::gmean 3.107293 -system.ruby.latency_hist::stdev 5.733578 -system.ruby.latency_hist | 152719525 99.98% 99.98% | 28048 0.02% 99.99% | 2695 0.00% 100.00% | 3637 0.00% 100.00% | 2109 0.00% 100.00% | 523 0.00% 100.00% | 9 0.00% 100.00% | 20 0.00% 100.00% | 17 0.00% 100.00% | 7 0.00% 100.00% -system.ruby.latency_hist::total 152756590 +system.ruby.latency_hist::stdev 5.733417 +system.ruby.latency_hist | 152719535 99.98% 99.98% | 28054 0.02% 99.99% | 2709 0.00% 100.00% | 3616 0.00% 100.00% | 2121 0.00% 100.00% | 519 0.00% 100.00% | 10 0.00% 100.00% | 19 0.00% 100.00% | 16 0.00% 100.00% | 7 0.00% 100.00% +system.ruby.latency_hist::total 152756606 system.ruby.hit_latency_hist::bucket_size 1 system.ruby.hit_latency_hist::max_bucket 9 -system.ruby.hit_latency_hist::samples 150094333 +system.ruby.hit_latency_hist::samples 150094340 system.ruby.hit_latency_hist::mean 3 system.ruby.hit_latency_hist::gmean 3.000000 -system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 150094333 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 150094333 +system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 150094340 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist::total 150094340 system.ruby.miss_latency_hist::bucket_size 128 system.ruby.miss_latency_hist::max_bucket 1279 -system.ruby.miss_latency_hist::samples 2662257 -system.ruby.miss_latency_hist::mean 27.885506 -system.ruby.miss_latency_hist::gmean 22.530762 -system.ruby.miss_latency_hist::stdev 35.745831 -system.ruby.miss_latency_hist | 2625192 98.61% 98.61% | 28048 1.05% 99.66% | 2695 0.10% 99.76% | 3637 0.14% 99.90% | 2109 0.08% 99.98% | 523 0.02% 100.00% | 9 0.00% 100.00% | 20 0.00% 100.00% | 17 0.00% 100.00% | 7 0.00% 100.00% -system.ruby.miss_latency_hist::total 2662257 -system.ruby.l1_cntrl0.L1Dcache.demand_hits 11119260 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 532503 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 11651763 # Number of cache demand accesses -system.ruby.l1_cntrl0.L1Icache.demand_hits 68488995 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Icache.demand_misses 323914 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Icache.demand_accesses 68812909 # Number of cache demand accesses +system.ruby.miss_latency_hist::samples 2662266 +system.ruby.miss_latency_hist::mean 27.885415 +system.ruby.miss_latency_hist::gmean 22.530675 +system.ruby.miss_latency_hist::stdev 35.744325 +system.ruby.miss_latency_hist | 2625195 98.61% 98.61% | 28054 1.05% 99.66% | 2709 0.10% 99.76% | 3616 0.14% 99.90% | 2121 0.08% 99.98% | 519 0.02% 100.00% | 10 0.00% 100.00% | 19 0.00% 100.00% | 16 0.00% 100.00% | 7 0.00% 100.00% +system.ruby.miss_latency_hist::total 2662266 +system.ruby.l1_cntrl0.L1Dcache.demand_hits 11119259 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Dcache.demand_misses 532505 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Dcache.demand_accesses 11651764 # Number of cache demand accesses +system.ruby.l1_cntrl0.L1Icache.demand_hits 68488994 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Icache.demand_misses 323919 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Icache.demand_accesses 68812913 # Number of cache demand accesses system.ruby.l1_cntrl0.prefetcher.miss_observed 0 # number of misses observed system.ruby.l1_cntrl0.prefetcher.allocated_streams 0 # number of streams allocated for prefetching system.ruby.l1_cntrl0.prefetcher.prefetches_requested 0 # number of prefetch requests made @@ -618,11 +618,11 @@ system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed system.ruby.l1_cntrl0.fully_busy_cycles 16 # cycles for which number of transistions == max transitions system.ruby.l1_cntrl1.L1Dcache.demand_hits 12794938 # Number of cache demand hits -system.ruby.l1_cntrl1.L1Dcache.demand_misses 1313574 # Number of cache demand misses -system.ruby.l1_cntrl1.L1Dcache.demand_accesses 14108512 # Number of cache demand accesses -system.ruby.l1_cntrl1.L1Icache.demand_hits 57691140 # Number of cache demand hits +system.ruby.l1_cntrl1.L1Dcache.demand_misses 1313576 # Number of cache demand misses +system.ruby.l1_cntrl1.L1Dcache.demand_accesses 14108514 # Number of cache demand accesses +system.ruby.l1_cntrl1.L1Icache.demand_hits 57691149 # Number of cache demand hits system.ruby.l1_cntrl1.L1Icache.demand_misses 492266 # Number of cache demand misses -system.ruby.l1_cntrl1.L1Icache.demand_accesses 58183406 # Number of cache demand accesses +system.ruby.l1_cntrl1.L1Icache.demand_accesses 58183415 # Number of cache demand accesses system.ruby.l1_cntrl1.prefetcher.miss_observed 0 # number of misses observed system.ruby.l1_cntrl1.prefetcher.allocated_streams 0 # number of streams allocated for prefetching system.ruby.l1_cntrl1.prefetcher.prefetches_requested 0 # number of prefetch requests made @@ -633,62 +633,62 @@ system.ruby.l1_cntrl1.prefetcher.partial_hits 0 system.ruby.l1_cntrl1.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl1.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed system.ruby.l1_cntrl1.fully_busy_cycles 7 # cycles for which number of transistions == max transitions -system.ruby.l2_cntrl0.L2cache.demand_hits 2435460 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_hits 2435469 # Number of cache demand hits system.ruby.l2_cntrl0.L2cache.demand_misses 226797 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 2662257 # Number of cache demand accesses -system.ruby.l2_cntrl0.fully_busy_cycles 5 # cycles for which number of transistions == max transitions +system.ruby.l2_cntrl0.L2cache.demand_accesses 2662266 # Number of cache demand accesses +system.ruby.l2_cntrl0.fully_busy_cycles 4 # cycles for which number of transistions == max transitions system.ruby.memctrl_clk_domain.clock 1500 # Clock period in ticks system.ruby.network.routers0.percent_links_utilized 0.030013 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system.ruby.network.routers0.msg_bytes.Request_Control::2 341280 -system.ruby.network.routers0.msg_bytes.Response_Data::1 63716400 -system.ruby.network.routers0.msg_bytes.Response_Control::1 4081128 -system.ruby.network.routers0.msg_bytes.Response_Control::2 4059640 -system.ruby.network.routers0.msg_bytes.Writeback_Data::0 21491424 +system.ruby.network.routers0.msg_bytes.Response_Data::1 63716904 +system.ruby.network.routers0.msg_bytes.Response_Control::1 4081136 +system.ruby.network.routers0.msg_bytes.Response_Control::2 4059648 +system.ruby.network.routers0.msg_bytes.Writeback_Data::0 21491496 system.ruby.network.routers0.msg_bytes.Writeback_Data::1 12816 system.ruby.network.routers0.msg_bytes.Writeback_Control::0 1363216 system.ruby.network.routers1.percent_links_utilized 0.057139 -system.ruby.network.routers1.msg_count.Control::0 1805840 +system.ruby.network.routers1.msg_count.Control::0 1805842 system.ruby.network.routers1.msg_count.Request_Control::2 40537 -system.ruby.network.routers1.msg_count.Response_Data::1 1830038 -system.ruby.network.routers1.msg_count.Response_Control::1 1255303 -system.ruby.network.routers1.msg_count.Response_Control::2 1254313 -system.ruby.network.routers1.msg_count.Writeback_Data::0 276120 +system.ruby.network.routers1.msg_count.Response_Data::1 1830040 +system.ruby.network.routers1.msg_count.Response_Control::1 1255305 +system.ruby.network.routers1.msg_count.Response_Control::2 1254315 +system.ruby.network.routers1.msg_count.Writeback_Data::0 276121 system.ruby.network.routers1.msg_count.Writeback_Data::1 190 -system.ruby.network.routers1.msg_count.Writeback_Control::0 940436 -system.ruby.network.routers1.msg_bytes.Control::0 14446720 +system.ruby.network.routers1.msg_count.Writeback_Control::0 940437 +system.ruby.network.routers1.msg_bytes.Control::0 14446736 system.ruby.network.routers1.msg_bytes.Request_Control::2 324296 -system.ruby.network.routers1.msg_bytes.Response_Data::1 131762736 -system.ruby.network.routers1.msg_bytes.Response_Control::1 10042424 -system.ruby.network.routers1.msg_bytes.Response_Control::2 10034504 -system.ruby.network.routers1.msg_bytes.Writeback_Data::0 19880640 +system.ruby.network.routers1.msg_bytes.Response_Data::1 131762880 +system.ruby.network.routers1.msg_bytes.Response_Control::1 10042440 +system.ruby.network.routers1.msg_bytes.Response_Control::2 10034520 +system.ruby.network.routers1.msg_bytes.Writeback_Data::0 19880712 system.ruby.network.routers1.msg_bytes.Writeback_Data::1 13680 -system.ruby.network.routers1.msg_bytes.Writeback_Control::0 7523488 +system.ruby.network.routers1.msg_bytes.Writeback_Control::0 7523496 system.ruby.network.routers2.percent_links_utilized 0.091475 -system.ruby.network.routers2.msg_count.Control::0 2839469 +system.ruby.network.routers2.msg_count.Control::0 2839478 system.ruby.network.routers2.msg_count.Request_Control::2 81710 -system.ruby.network.routers2.msg_count.Response_Data::1 2890401 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0 system.ruby.network.routers6.percent_links_utilized 0.030942 -system.ruby.network.routers6.msg_count.Control::0 2839469 +system.ruby.network.routers6.msg_count.Control::0 2839478 system.ruby.network.routers6.msg_count.Request_Control::2 83197 -system.ruby.network.routers6.msg_count.Response_Data::1 2940795 -system.ruby.network.routers6.msg_count.Response_Control::1 1870415 -system.ruby.network.routers6.msg_count.Response_Control::2 1761768 -system.ruby.network.routers6.msg_count.Writeback_Data::0 574612 +system.ruby.network.routers6.msg_count.Response_Data::1 2940804 +system.ruby.network.routers6.msg_count.Response_Control::1 1870418 +system.ruby.network.routers6.msg_count.Response_Control::2 1761771 +system.ruby.network.routers6.msg_count.Writeback_Data::0 574614 system.ruby.network.routers6.msg_count.Writeback_Data::1 368 -system.ruby.network.routers6.msg_count.Writeback_Control::0 1158383 +system.ruby.network.routers6.msg_count.Writeback_Control::0 1158384 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-system.ruby.network.routers6.throttle1.msg_bytes.Response_Data::1 129283920 -system.ruby.network.routers6.throttle1.msg_bytes.Response_Control::1 9904304 -system.ruby.network.routers6.throttle2.link_utilization 0.059642 -system.ruby.network.routers6.throttle2.msg_count.Control::0 2662257 +system.ruby.network.routers6.throttle1.msg_bytes.Response_Data::1 129284064 +system.ruby.network.routers6.throttle1.msg_bytes.Response_Control::1 9904320 +system.ruby.network.routers6.throttle2.link_utilization 0.059643 +system.ruby.network.routers6.throttle2.msg_count.Control::0 2662266 system.ruby.network.routers6.throttle2.msg_count.Response_Data::1 202813 system.ruby.network.routers6.throttle2.msg_count.Response_Control::1 123155 -system.ruby.network.routers6.throttle2.msg_count.Response_Control::2 1761768 -system.ruby.network.routers6.throttle2.msg_count.Writeback_Data::0 574612 +system.ruby.network.routers6.throttle2.msg_count.Response_Control::2 1761771 +system.ruby.network.routers6.throttle2.msg_count.Writeback_Data::0 574614 system.ruby.network.routers6.throttle2.msg_count.Writeback_Data::1 368 -system.ruby.network.routers6.throttle2.msg_count.Writeback_Control::0 1110838 -system.ruby.network.routers6.throttle2.msg_bytes.Control::0 21298056 +system.ruby.network.routers6.throttle2.msg_count.Writeback_Control::0 1110839 +system.ruby.network.routers6.throttle2.msg_bytes.Control::0 21298128 system.ruby.network.routers6.throttle2.msg_bytes.Response_Data::1 14602536 system.ruby.network.routers6.throttle2.msg_bytes.Response_Control::1 985240 -system.ruby.network.routers6.throttle2.msg_bytes.Response_Control::2 14094144 -system.ruby.network.routers6.throttle2.msg_bytes.Writeback_Data::0 41372064 +system.ruby.network.routers6.throttle2.msg_bytes.Response_Control::2 14094168 +system.ruby.network.routers6.throttle2.msg_bytes.Writeback_Data::0 41372208 system.ruby.network.routers6.throttle2.msg_bytes.Writeback_Data::1 26496 -system.ruby.network.routers6.throttle2.msg_bytes.Writeback_Control::0 8886704 +system.ruby.network.routers6.throttle2.msg_bytes.Writeback_Control::0 8886712 system.ruby.network.routers6.throttle3.link_utilization 0.005259 system.ruby.network.routers6.throttle3.msg_count.Control::0 177212 system.ruby.network.routers6.throttle3.msg_count.Response_Data::1 97371 @@ -879,55 +879,55 @@ system.ruby.network.routers6.throttle4.msg_bytes.Writeback_Control::1 3738 system.ruby.network.routers6.throttle5.link_utilization 0 system.ruby.delayVCHist.vnet_0::bucket_size 4 # delay histogram for vnet_0 system.ruby.delayVCHist.vnet_0::max_bucket 39 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::samples 6109475 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::mean 0.754304 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::stdev 2.340275 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0 | 5534056 90.58% 90.58% | 362 0.01% 90.59% | 574616 9.41% 99.99% | 149 0.00% 100.00% | 247 0.00% 100.00% | 11 0.00% 100.00% | 34 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::total 6109475 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::samples 6109490 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::mean 0.754288 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::stdev 2.340197 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0 | 5534078 90.58% 90.58% | 346 0.01% 90.59% | 574634 9.41% 99.99% | 147 0.00% 100.00% | 241 0.00% 100.00% | 10 0.00% 100.00% | 34 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::total 6109490 # delay histogram for vnet_0 system.ruby.delayVCHist.vnet_1::bucket_size 2 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_1::max_bucket 19 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::samples 4698338 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::mean 0.045583 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::stdev 0.599791 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1 | 4670953 99.42% 99.42% | 477 0.01% 99.43% | 336 0.01% 99.43% | 540 0.01% 99.45% | 25880 0.55% 100.00% | 139 0.00% 100.00% | 2 0.00% 100.00% | 1 0.00% 100.00% | 10 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::total 4698338 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::samples 4698350 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::mean 0.045551 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::stdev 0.599594 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1 | 4670978 99.42% 99.42% | 496 0.01% 99.43% | 327 0.01% 99.43% | 527 0.01% 99.45% | 25863 0.55% 100.00% | 148 0.00% 100.00% | 1 0.00% 100.00% | 1 0.00% 100.00% | 9 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::total 4698350 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::samples 83197 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::mean 0.000192 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::stdev 0.019611 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2 | 83189 99.99% 99.99% | 0 0.00% 99.99% | 8 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::mean 0.000144 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::stdev 0.016984 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2 | 83191 99.99% 99.99% | 0 0.00% 99.99% | 6 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::total 83197 # delay histogram for vnet_2 system.ruby.LD.latency_hist::bucket_size 128 system.ruby.LD.latency_hist::max_bucket 1279 -system.ruby.LD.latency_hist::samples 15027912 -system.ruby.LD.latency_hist::mean 4.869020 -system.ruby.LD.latency_hist::gmean 3.591147 -system.ruby.LD.latency_hist::stdev 9.231737 -system.ruby.LD.latency_hist | 15011958 99.89% 99.89% | 13851 0.09% 99.99% | 851 0.01% 99.99% | 792 0.01% 100.00% | 329 0.00% 100.00% | 121 0.00% 100.00% | 2 0.00% 100.00% | 3 0.00% 100.00% | 4 0.00% 100.00% | 1 0.00% 100.00% -system.ruby.LD.latency_hist::total 15027912 +system.ruby.LD.latency_hist::samples 15027915 +system.ruby.LD.latency_hist::mean 4.869031 +system.ruby.LD.latency_hist::gmean 3.591146 +system.ruby.LD.latency_hist::stdev 9.232635 +system.ruby.LD.latency_hist | 15011953 99.89% 99.89% | 13856 0.09% 99.99% | 858 0.01% 99.99% | 788 0.01% 100.00% | 329 0.00% 100.00% | 120 0.00% 100.00% | 2 0.00% 100.00% | 4 0.00% 100.00% | 4 0.00% 100.00% | 1 0.00% 100.00% +system.ruby.LD.latency_hist::total 15027915 system.ruby.LD.hit_latency_hist::bucket_size 1 system.ruby.LD.hit_latency_hist::max_bucket 9 -system.ruby.LD.hit_latency_hist::samples 13637263 +system.ruby.LD.hit_latency_hist::samples 13637262 system.ruby.LD.hit_latency_hist::mean 3 system.ruby.LD.hit_latency_hist::gmean 3.000000 -system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 13637263 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist::total 13637263 +system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 13637262 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist::total 13637262 system.ruby.LD.miss_latency_hist::bucket_size 128 system.ruby.LD.miss_latency_hist::max_bucket 1279 -system.ruby.LD.miss_latency_hist::samples 1390649 -system.ruby.LD.miss_latency_hist::mean 23.197386 -system.ruby.LD.miss_latency_hist::gmean 20.952196 -system.ruby.LD.miss_latency_hist::stdev 23.468925 -system.ruby.LD.miss_latency_hist | 1374695 98.85% 98.85% | 13851 1.00% 99.85% | 851 0.06% 99.91% | 792 0.06% 99.97% | 329 0.02% 99.99% | 121 0.01% 100.00% | 2 0.00% 100.00% | 3 0.00% 100.00% | 4 0.00% 100.00% | 1 0.00% 100.00% -system.ruby.LD.miss_latency_hist::total 1390649 +system.ruby.LD.miss_latency_hist::samples 1390653 +system.ruby.LD.miss_latency_hist::mean 23.197446 +system.ruby.LD.miss_latency_hist::gmean 20.952063 +system.ruby.LD.miss_latency_hist::stdev 23.472645 +system.ruby.LD.miss_latency_hist | 1374691 98.85% 98.85% | 13856 1.00% 99.85% | 858 0.06% 99.91% | 788 0.06% 99.97% | 329 0.02% 99.99% | 120 0.01% 100.00% | 2 0.00% 100.00% | 4 0.00% 100.00% | 4 0.00% 100.00% | 1 0.00% 100.00% +system.ruby.LD.miss_latency_hist::total 1390653 system.ruby.ST.latency_hist::bucket_size 128 system.ruby.ST.latency_hist::max_bucket 1279 system.ruby.ST.latency_hist::samples 9558783 -system.ruby.ST.latency_hist::mean 5.170026 -system.ruby.ST.latency_hist::gmean 3.300098 -system.ruby.ST.latency_hist::stdev 17.579302 -system.ruby.ST.latency_hist | 9544781 99.85% 99.85% | 8164 0.09% 99.94% | 1330 0.01% 99.95% | 2504 0.03% 99.98% | 1628 0.02% 100.00% | 340 0.00% 100.00% | 7 0.00% 100.00% | 12 0.00% 100.00% | 11 0.00% 100.00% | 6 0.00% 100.00% +system.ruby.ST.latency_hist::mean 5.169851 +system.ruby.ST.latency_hist::gmean 3.300097 +system.ruby.ST.latency_hist::stdev 17.574774 +system.ruby.ST.latency_hist | 9544786 99.85% 99.85% | 8165 0.09% 99.94% | 1340 0.01% 99.95% | 2484 0.03% 99.98% | 1636 0.02% 100.00% | 338 0.00% 100.00% | 8 0.00% 100.00% | 10 0.00% 100.00% | 10 0.00% 100.00% | 6 0.00% 100.00% system.ruby.ST.latency_hist::total 9558783 system.ruby.ST.hit_latency_hist::bucket_size 1 system.ruby.ST.hit_latency_hist::max_bucket 9 @@ -939,41 +939,41 @@ system.ruby.ST.hit_latency_hist::total 9207752 system.ruby.ST.miss_latency_hist::bucket_size 128 system.ruby.ST.miss_latency_hist::max_bucket 1279 system.ruby.ST.miss_latency_hist::samples 351031 -system.ruby.ST.miss_latency_hist::mean 62.091086 -system.ruby.ST.miss_latency_hist::gmean 40.236579 -system.ruby.ST.miss_latency_hist::stdev 71.074662 -system.ruby.ST.miss_latency_hist | 337029 96.01% 96.01% | 8164 2.33% 98.34% | 1330 0.38% 98.72% | 2504 0.71% 99.43% | 1628 0.46% 99.89% | 340 0.10% 99.99% | 7 0.00% 99.99% | 12 0.00% 100.00% | 11 0.00% 100.00% | 6 0.00% 100.00% +system.ruby.ST.miss_latency_hist::mean 62.086337 +system.ruby.ST.miss_latency_hist::gmean 40.235982 +system.ruby.ST.miss_latency_hist::stdev 71.047969 +system.ruby.ST.miss_latency_hist | 337034 96.01% 96.01% | 8165 2.33% 98.34% | 1340 0.38% 98.72% | 2484 0.71% 99.43% | 1636 0.47% 99.89% | 338 0.10% 99.99% | 8 0.00% 99.99% | 10 0.00% 100.00% | 10 0.00% 100.00% | 6 0.00% 100.00% system.ruby.ST.miss_latency_hist::total 351031 system.ruby.IFETCH.latency_hist::bucket_size 128 system.ruby.IFETCH.latency_hist::max_bucket 1279 -system.ruby.IFETCH.latency_hist::samples 126996315 -system.ruby.IFETCH.latency_hist::mean 3.119134 +system.ruby.IFETCH.latency_hist::samples 126996328 +system.ruby.IFETCH.latency_hist::mean 3.119146 system.ruby.IFETCH.latency_hist::gmean 3.036572 -system.ruby.IFETCH.latency_hist::stdev 2.233716 -system.ruby.IFETCH.latency_hist | 126989642 99.99% 99.99% | 5673 0.00% 100.00% | 484 0.00% 100.00% | 317 0.00% 100.00% | 137 0.00% 100.00% | 55 0.00% 100.00% | 0 0.00% 100.00% | 5 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.latency_hist::total 126996315 +system.ruby.IFETCH.latency_hist::stdev 2.235323 +system.ruby.IFETCH.latency_hist | 126989653 99.99% 99.99% | 5672 0.00% 100.00% | 481 0.00% 100.00% | 320 0.00% 100.00% | 141 0.00% 100.00% | 54 0.00% 100.00% | 0 0.00% 100.00% | 5 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist::total 126996328 system.ruby.IFETCH.hit_latency_hist::bucket_size 1 system.ruby.IFETCH.hit_latency_hist::max_bucket 9 -system.ruby.IFETCH.hit_latency_hist::samples 126180135 +system.ruby.IFETCH.hit_latency_hist::samples 126180143 system.ruby.IFETCH.hit_latency_hist::mean 3 system.ruby.IFETCH.hit_latency_hist::gmean 3.000000 -system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 126180135 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist::total 126180135 +system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 126180143 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist::total 126180143 system.ruby.IFETCH.miss_latency_hist::bucket_size 128 system.ruby.IFETCH.miss_latency_hist::max_bucket 1279 -system.ruby.IFETCH.miss_latency_hist::samples 816180 -system.ruby.IFETCH.miss_latency_hist::mean 21.537108 -system.ruby.IFETCH.miss_latency_hist::gmean 19.766480 -system.ruby.IFETCH.miss_latency_hist::stdev 20.855244 -system.ruby.IFETCH.miss_latency_hist | 809507 99.18% 99.18% | 5673 0.70% 99.88% | 484 0.06% 99.94% | 317 0.04% 99.98% | 137 0.02% 99.99% | 55 0.01% 100.00% | 0 0.00% 100.00% | 5 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.miss_latency_hist::total 816180 +system.ruby.IFETCH.miss_latency_hist::samples 816185 +system.ruby.IFETCH.miss_latency_hist::mean 21.538739 +system.ruby.IFETCH.miss_latency_hist::gmean 19.766603 +system.ruby.IFETCH.miss_latency_hist::stdev 20.880467 +system.ruby.IFETCH.miss_latency_hist | 809510 99.18% 99.18% | 5672 0.69% 99.88% | 481 0.06% 99.94% | 320 0.04% 99.98% | 141 0.02% 99.99% | 54 0.01% 100.00% | 0 0.00% 100.00% | 5 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist::total 816185 system.ruby.RMW_Read.latency_hist::bucket_size 128 system.ruby.RMW_Read.latency_hist::max_bucket 1279 system.ruby.RMW_Read.latency_hist::samples 494272 -system.ruby.RMW_Read.latency_hist::mean 6.020764 -system.ruby.RMW_Read.latency_hist::gmean 3.952362 -system.ruby.RMW_Read.latency_hist::stdev 10.313773 -system.ruby.RMW_Read.latency_hist | 494092 99.96% 99.96% | 129 0.03% 99.99% | 18 0.00% 99.99% | 18 0.00% 100.00% | 11 0.00% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.RMW_Read.latency_hist::mean 6.021773 +system.ruby.RMW_Read.latency_hist::gmean 3.952377 +system.ruby.RMW_Read.latency_hist::stdev 10.350675 +system.ruby.RMW_Read.latency_hist | 494091 99.96% 99.96% | 129 0.03% 99.99% | 18 0.00% 99.99% | 18 0.00% 100.00% | 12 0.00% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.RMW_Read.latency_hist::total 494272 system.ruby.RMW_Read.hit_latency_hist::bucket_size 1 system.ruby.RMW_Read.hit_latency_hist::max_bucket 9 @@ -985,18 +985,18 @@ system.ruby.RMW_Read.hit_latency_hist::total 428940 system.ruby.RMW_Read.miss_latency_hist::bucket_size 128 system.ruby.RMW_Read.miss_latency_hist::max_bucket 1279 system.ruby.RMW_Read.miss_latency_hist::samples 65332 -system.ruby.RMW_Read.miss_latency_hist::mean 25.853716 -system.ruby.RMW_Read.miss_latency_hist::gmean 24.153784 -system.ruby.RMW_Read.miss_latency_hist::stdev 18.748956 -system.ruby.RMW_Read.miss_latency_hist | 65152 99.72% 99.72% | 129 0.20% 99.92% | 18 0.03% 99.95% | 18 0.03% 99.98% | 11 0.02% 99.99% | 4 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.RMW_Read.miss_latency_hist::mean 25.861354 +system.ruby.RMW_Read.miss_latency_hist::gmean 24.154461 +system.ruby.RMW_Read.miss_latency_hist::stdev 18.894168 +system.ruby.RMW_Read.miss_latency_hist | 65151 99.72% 99.72% | 129 0.20% 99.92% | 18 0.03% 99.95% | 18 0.03% 99.98% | 12 0.02% 99.99% | 4 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.RMW_Read.miss_latency_hist::total 65332 system.ruby.Locked_RMW_Read.latency_hist::bucket_size 128 system.ruby.Locked_RMW_Read.latency_hist::max_bucket 1279 system.ruby.Locked_RMW_Read.latency_hist::samples 339654 -system.ruby.Locked_RMW_Read.latency_hist::mean 5.351331 -system.ruby.Locked_RMW_Read.latency_hist::gmean 3.780101 -system.ruby.Locked_RMW_Read.latency_hist::stdev 8.370233 -system.ruby.Locked_RMW_Read.latency_hist | 339398 99.92% 99.92% | 231 0.07% 99.99% | 12 0.00% 100.00% | 6 0.00% 100.00% | 4 0.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Read.latency_hist::mean 5.350042 +system.ruby.Locked_RMW_Read.latency_hist::gmean 3.780078 +system.ruby.Locked_RMW_Read.latency_hist::stdev 8.318496 +system.ruby.Locked_RMW_Read.latency_hist | 339398 99.92% 99.92% | 232 0.07% 99.99% | 12 0.00% 100.00% | 6 0.00% 100.00% | 3 0.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.Locked_RMW_Read.latency_hist::total 339654 system.ruby.Locked_RMW_Read.hit_latency_hist::bucket_size 1 system.ruby.Locked_RMW_Read.hit_latency_hist::max_bucket 9 @@ -1008,10 +1008,10 @@ system.ruby.Locked_RMW_Read.hit_latency_hist::total 300589 system.ruby.Locked_RMW_Read.miss_latency_hist::bucket_size 128 system.ruby.Locked_RMW_Read.miss_latency_hist::max_bucket 1279 system.ruby.Locked_RMW_Read.miss_latency_hist::samples 39065 -system.ruby.Locked_RMW_Read.miss_latency_hist::mean 23.443850 -system.ruby.Locked_RMW_Read.miss_latency_hist::gmean 22.382210 -system.ruby.Locked_RMW_Read.miss_latency_hist::stdev 15.468459 -system.ruby.Locked_RMW_Read.miss_latency_hist | 38809 99.34% 99.34% | 231 0.59% 99.94% | 12 0.03% 99.97% | 6 0.02% 99.98% | 4 0.01% 99.99% | 3 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Read.miss_latency_hist::mean 23.432638 +system.ruby.Locked_RMW_Read.miss_latency_hist::gmean 22.380989 +system.ruby.Locked_RMW_Read.miss_latency_hist::stdev 15.237176 +system.ruby.Locked_RMW_Read.miss_latency_hist | 38809 99.34% 99.34% | 232 0.59% 99.94% | 12 0.03% 99.97% | 6 0.02% 99.98% | 3 0.01% 99.99% | 3 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.Locked_RMW_Read.miss_latency_hist::total 39065 system.ruby.Locked_RMW_Write.latency_hist::bucket_size 1 system.ruby.Locked_RMW_Write.latency_hist::max_bucket 9 @@ -1065,16 +1065,16 @@ system.ruby.DMA_Controller.BUSY_RD.Data | 809 100.00% 100.00% | system.ruby.DMA_Controller.BUSY_RD.Data::total 809 system.ruby.DMA_Controller.BUSY_WR.Ack | 46736 100.00% 100.00% | 0 0.00% 100.00% system.ruby.DMA_Controller.BUSY_WR.Ack::total 46736 -system.ruby.L1Cache_Controller.Load | 6279317 41.78% 41.78% | 8748595 58.22% 100.00% -system.ruby.L1Cache_Controller.Load::total 15027912 -system.ruby.L1Cache_Controller.Ifetch | 68812914 54.18% 54.18% | 58183407 45.82% 100.00% -system.ruby.L1Cache_Controller.Ifetch::total 126996321 +system.ruby.L1Cache_Controller.Load | 6279318 41.78% 41.78% | 8748597 58.22% 100.00% +system.ruby.L1Cache_Controller.Load::total 15027915 +system.ruby.L1Cache_Controller.Ifetch | 68812918 54.18% 54.18% | 58183416 45.82% 100.00% +system.ruby.L1Cache_Controller.Ifetch::total 126996334 system.ruby.L1Cache_Controller.Store | 5372446 50.06% 50.06% | 5359917 49.94% 100.00% system.ruby.L1Cache_Controller.Store::total 10732363 system.ruby.L1Cache_Controller.Inv | 16157 48.07% 48.07% | 17455 51.93% 100.00% system.ruby.L1Cache_Controller.Inv::total 33612 -system.ruby.L1Cache_Controller.L1_Replacement | 828605 31.79% 31.79% | 1777971 68.21% 100.00% -system.ruby.L1Cache_Controller.L1_Replacement::total 2606576 +system.ruby.L1Cache_Controller.L1_Replacement | 828612 31.79% 31.79% | 1777973 68.21% 100.00% +system.ruby.L1Cache_Controller.L1_Replacement::total 2606585 system.ruby.L1Cache_Controller.Fwd_GETX | 12248 51.07% 51.07% | 11736 48.93% 100.00% system.ruby.L1Cache_Controller.Fwd_GETX::total 23984 system.ruby.L1Cache_Controller.Fwd_GETS | 14251 55.67% 55.67% | 11346 44.33% 100.00% @@ -1083,23 +1083,23 @@ system.ruby.L1Cache_Controller.Fwd_GET_INSTR | 4 100.00% 100.00% system.ruby.L1Cache_Controller.Fwd_GET_INSTR::total 4 system.ruby.L1Cache_Controller.Data | 818 44.46% 44.46% | 1022 55.54% 100.00% system.ruby.L1Cache_Controller.Data::total 1840 -system.ruby.L1Cache_Controller.Data_Exclusive | 252712 19.73% 19.73% | 1028027 80.27% 100.00% -system.ruby.L1Cache_Controller.Data_Exclusive::total 1280739 +system.ruby.L1Cache_Controller.Data_Exclusive | 252714 19.73% 19.73% | 1028028 80.27% 100.00% +system.ruby.L1Cache_Controller.Data_Exclusive::total 1280742 system.ruby.L1Cache_Controller.DataS_fromL1 | 11346 44.32% 44.32% | 14255 55.68% 100.00% system.ruby.L1Cache_Controller.DataS_fromL1::total 25601 -system.ruby.L1Cache_Controller.Data_all_Acks | 579316 43.50% 43.50% | 752306 56.50% 100.00% -system.ruby.L1Cache_Controller.Data_all_Acks::total 1331622 +system.ruby.L1Cache_Controller.Data_all_Acks | 579321 43.50% 43.50% | 752307 56.50% 100.00% +system.ruby.L1Cache_Controller.Data_all_Acks::total 1331628 system.ruby.L1Cache_Controller.Ack | 12225 54.44% 54.44% | 10230 45.56% 100.00% system.ruby.L1Cache_Controller.Ack::total 22455 system.ruby.L1Cache_Controller.Ack_all | 13043 53.69% 53.69% | 11252 46.31% 100.00% system.ruby.L1Cache_Controller.Ack_all::total 24295 -system.ruby.L1Cache_Controller.WB_Ack | 468894 27.82% 27.82% | 1216556 72.18% 100.00% -system.ruby.L1Cache_Controller.WB_Ack::total 1685450 -system.ruby.L1Cache_Controller.NP.Load | 280382 20.44% 20.44% | 1091184 79.56% 100.00% -system.ruby.L1Cache_Controller.NP.Load::total 1371566 -system.ruby.L1Cache_Controller.NP.Ifetch | 323814 39.71% 39.71% | 491732 60.29% 100.00% -system.ruby.L1Cache_Controller.NP.Ifetch::total 815546 -system.ruby.L1Cache_Controller.NP.Store | 225433 53.48% 53.48% | 196079 46.52% 100.00% +system.ruby.L1Cache_Controller.WB_Ack | 468895 27.82% 27.82% | 1216558 72.18% 100.00% +system.ruby.L1Cache_Controller.WB_Ack::total 1685453 +system.ruby.L1Cache_Controller.NP.Load | 280385 20.44% 20.44% | 1091185 79.56% 100.00% +system.ruby.L1Cache_Controller.NP.Load::total 1371570 +system.ruby.L1Cache_Controller.NP.Ifetch | 323819 39.71% 39.71% | 491732 60.29% 100.00% +system.ruby.L1Cache_Controller.NP.Ifetch::total 815551 +system.ruby.L1Cache_Controller.NP.Store | 225432 53.48% 53.48% | 196080 46.52% 100.00% system.ruby.L1Cache_Controller.NP.Store::total 421512 system.ruby.L1Cache_Controller.NP.Inv | 4849 54.09% 54.09% | 4115 45.91% 100.00% system.ruby.L1Cache_Controller.NP.Inv::total 8964 @@ -1111,51 +1111,51 @@ system.ruby.L1Cache_Controller.I.Store | 5739 50.07% 50.07% | system.ruby.L1Cache_Controller.I.Store::total 11461 system.ruby.L1Cache_Controller.I.L1_Replacement | 8993 51.78% 51.78% | 8375 48.22% 100.00% system.ruby.L1Cache_Controller.I.L1_Replacement::total 17368 -system.ruby.L1Cache_Controller.S.Load | 555624 51.88% 51.88% | 515377 48.12% 100.00% +system.ruby.L1Cache_Controller.S.Load | 555622 51.88% 51.88% | 515379 48.12% 100.00% system.ruby.L1Cache_Controller.S.Load::total 1071001 -system.ruby.L1Cache_Controller.S.Ifetch | 68488995 54.28% 54.28% | 57691140 45.72% 100.00% -system.ruby.L1Cache_Controller.S.Ifetch::total 126180135 +system.ruby.L1Cache_Controller.S.Ifetch | 68488994 54.28% 54.28% | 57691149 45.72% 100.00% +system.ruby.L1Cache_Controller.S.Ifetch::total 126180143 system.ruby.L1Cache_Controller.S.Store | 12225 54.44% 54.44% | 10230 45.56% 100.00% system.ruby.L1Cache_Controller.S.Store::total 22455 system.ruby.L1Cache_Controller.S.Inv | 11078 45.79% 45.79% | 13115 54.21% 100.00% system.ruby.L1Cache_Controller.S.Inv::total 24193 -system.ruby.L1Cache_Controller.S.L1_Replacement | 350718 38.81% 38.81% | 553040 61.19% 100.00% -system.ruby.L1Cache_Controller.S.L1_Replacement::total 903758 -system.ruby.L1Cache_Controller.E.Load | 1152084 29.74% 29.74% | 2722150 70.26% 100.00% -system.ruby.L1Cache_Controller.E.Load::total 3874234 -system.ruby.L1Cache_Controller.E.Store | 80726 48.37% 48.37% | 86165 51.63% 100.00% -system.ruby.L1Cache_Controller.E.Store::total 166891 +system.ruby.L1Cache_Controller.S.L1_Replacement | 350724 38.81% 38.81% | 553040 61.19% 100.00% +system.ruby.L1Cache_Controller.S.L1_Replacement::total 903764 +system.ruby.L1Cache_Controller.E.Load | 1152088 29.74% 29.74% | 2722151 70.26% 100.00% +system.ruby.L1Cache_Controller.E.Load::total 3874239 +system.ruby.L1Cache_Controller.E.Store | 80728 48.37% 48.37% | 86165 51.63% 100.00% +system.ruby.L1Cache_Controller.E.Store::total 166893 system.ruby.L1Cache_Controller.E.Inv | 52 59.77% 59.77% | 35 40.23% 100.00% system.ruby.L1Cache_Controller.E.Inv::total 87 -system.ruby.L1Cache_Controller.E.L1_Replacement | 170402 15.34% 15.34% | 940436 84.66% 100.00% -system.ruby.L1Cache_Controller.E.L1_Replacement::total 1110838 +system.ruby.L1Cache_Controller.E.L1_Replacement | 170402 15.34% 15.34% | 940437 84.66% 100.00% +system.ruby.L1Cache_Controller.E.L1_Replacement::total 1110839 system.ruby.L1Cache_Controller.E.Fwd_GETX | 330 72.53% 72.53% | 125 27.47% 100.00% system.ruby.L1Cache_Controller.E.Fwd_GETX::total 455 system.ruby.L1Cache_Controller.E.Fwd_GETS | 996 45.17% 45.17% | 1209 54.83% 100.00% system.ruby.L1Cache_Controller.E.Fwd_GETS::total 2205 -system.ruby.L1Cache_Controller.M.Load | 4282503 49.27% 49.27% | 4409525 50.73% 100.00% -system.ruby.L1Cache_Controller.M.Load::total 8692028 -system.ruby.L1Cache_Controller.M.Store | 5048323 49.93% 49.93% | 5061721 50.07% 100.00% -system.ruby.L1Cache_Controller.M.Store::total 10110044 +system.ruby.L1Cache_Controller.M.Load | 4282499 49.27% 49.27% | 4409523 50.73% 100.00% +system.ruby.L1Cache_Controller.M.Load::total 8692022 +system.ruby.L1Cache_Controller.M.Store | 5048322 49.93% 49.93% | 5061720 50.07% 100.00% +system.ruby.L1Cache_Controller.M.Store::total 10110042 system.ruby.L1Cache_Controller.M.Inv | 178 48.37% 48.37% | 190 51.63% 100.00% system.ruby.L1Cache_Controller.M.Inv::total 368 -system.ruby.L1Cache_Controller.M.L1_Replacement | 298492 51.95% 51.95% | 276120 48.05% 100.00% -system.ruby.L1Cache_Controller.M.L1_Replacement::total 574612 +system.ruby.L1Cache_Controller.M.L1_Replacement | 298493 51.95% 51.95% | 276121 48.05% 100.00% +system.ruby.L1Cache_Controller.M.L1_Replacement::total 574614 system.ruby.L1Cache_Controller.M.Fwd_GETX | 11918 50.65% 50.65% | 11611 49.35% 100.00% system.ruby.L1Cache_Controller.M.Fwd_GETX::total 23529 system.ruby.L1Cache_Controller.M.Fwd_GETS | 13255 56.66% 56.66% | 10137 43.34% 100.00% system.ruby.L1Cache_Controller.M.Fwd_GETS::total 23392 system.ruby.L1Cache_Controller.M.Fwd_GET_INSTR | 4 100.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.M.Fwd_GET_INSTR::total 4 -system.ruby.L1Cache_Controller.IS.Data_Exclusive | 252712 19.73% 19.73% | 1028027 80.27% 100.00% -system.ruby.L1Cache_Controller.IS.Data_Exclusive::total 1280739 +system.ruby.L1Cache_Controller.IS.Data_Exclusive | 252714 19.73% 19.73% | 1028028 80.27% 100.00% +system.ruby.L1Cache_Controller.IS.Data_Exclusive::total 1280742 system.ruby.L1Cache_Controller.IS.DataS_fromL1 | 11346 44.32% 44.32% | 14255 55.68% 100.00% system.ruby.L1Cache_Controller.IS.DataS_fromL1::total 25601 -system.ruby.L1Cache_Controller.IS.Data_all_Acks | 348962 38.75% 38.75% | 551527 61.25% 100.00% -system.ruby.L1Cache_Controller.IS.Data_all_Acks::total 900489 +system.ruby.L1Cache_Controller.IS.Data_all_Acks | 348968 38.75% 38.75% | 551527 61.25% 100.00% +system.ruby.L1Cache_Controller.IS.Data_all_Acks::total 900495 system.ruby.L1Cache_Controller.IM.Data | 818 44.46% 44.46% | 1022 55.54% 100.00% system.ruby.L1Cache_Controller.IM.Data::total 1840 -system.ruby.L1Cache_Controller.IM.Data_all_Acks | 230354 53.43% 53.43% | 200779 46.57% 100.00% +system.ruby.L1Cache_Controller.IM.Data_all_Acks | 230353 53.43% 53.43% | 200780 46.57% 100.00% system.ruby.L1Cache_Controller.IM.Data_all_Acks::total 431133 system.ruby.L1Cache_Controller.SM.Ack | 12225 54.44% 54.44% | 10230 45.56% 100.00% system.ruby.L1Cache_Controller.SM.Ack::total 22455 @@ -1163,13 +1163,13 @@ system.ruby.L1Cache_Controller.SM.Ack_all | 13043 53.69% 53.69% | system.ruby.L1Cache_Controller.SM.Ack_all::total 24295 system.ruby.L1Cache_Controller.M_I.Ifetch | 5 83.33% 83.33% | 1 16.67% 100.00% system.ruby.L1Cache_Controller.M_I.Ifetch::total 6 -system.ruby.L1Cache_Controller.M_I.WB_Ack | 468894 27.82% 27.82% | 1216556 72.18% 100.00% -system.ruby.L1Cache_Controller.M_I.WB_Ack::total 1685450 -system.ruby.L2Cache_Controller.L1_GET_INSTR 816180 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETS 1390821 0.00% 0.00% +system.ruby.L1Cache_Controller.M_I.WB_Ack | 468895 27.82% 27.82% | 1216558 72.18% 100.00% +system.ruby.L1Cache_Controller.M_I.WB_Ack::total 1685453 +system.ruby.L2Cache_Controller.L1_GET_INSTR 816185 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_GETS 1390825 0.00% 0.00% system.ruby.L2Cache_Controller.L1_GETX 432975 0.00% 0.00% system.ruby.L2Cache_Controller.L1_UPGRADE 22455 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTX 1685450 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_PUTX 1685453 0.00% 0.00% system.ruby.L2Cache_Controller.L2_Replacement 95536 0.00% 0.00% system.ruby.L2Cache_Controller.L2_Replacement_clean 15120 0.00% 0.00% system.ruby.L2Cache_Controller.Mem_Data 177212 0.00% 0.00% @@ -1179,20 +1179,20 @@ system.ruby.L2Cache_Controller.WB_Data_clean 2205 0.00% 0.00% system.ruby.L2Cache_Controller.Ack 1487 0.00% 0.00% system.ruby.L2Cache_Controller.Ack_all 7462 0.00% 0.00% system.ruby.L2Cache_Controller.Unblock 25601 0.00% 0.00% -system.ruby.L2Cache_Controller.Exclusive_Unblock 1736167 0.00% 0.00% +system.ruby.L2Cache_Controller.Exclusive_Unblock 1736170 0.00% 0.00% system.ruby.L2Cache_Controller.MEM_Inv 3550 0.00% 0.00% system.ruby.L2Cache_Controller.NP.L1_GET_INSTR 16316 0.00% 0.00% system.ruby.L2Cache_Controller.NP.L1_GETS 33914 0.00% 0.00% system.ruby.L2Cache_Controller.NP.L1_GETX 126982 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_GET_INSTR 799834 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_GETS 84313 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_GET_INSTR 799839 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_GETS 84314 0.00% 0.00% system.ruby.L2Cache_Controller.SS.L1_GETX 1944 0.00% 0.00% system.ruby.L2Cache_Controller.SS.L1_UPGRADE 22455 0.00% 0.00% system.ruby.L2Cache_Controller.SS.L2_Replacement 252 0.00% 0.00% system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 7120 0.00% 0.00% system.ruby.L2Cache_Controller.SS.MEM_Inv 3 0.00% 0.00% system.ruby.L2Cache_Controller.M.L1_GET_INSTR 26 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETS 1246825 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETS 1246828 0.00% 0.00% system.ruby.L2Cache_Controller.M.L1_GETX 280063 0.00% 0.00% system.ruby.L2Cache_Controller.M.L2_Replacement 95163 0.00% 0.00% system.ruby.L2Cache_Controller.M.L2_Replacement_clean 7896 0.00% 0.00% @@ -1200,7 +1200,7 @@ system.ruby.L2Cache_Controller.M.MEM_Inv 1542 0.00% 0.00% system.ruby.L2Cache_Controller.MT.L1_GET_INSTR 4 0.00% 0.00% system.ruby.L2Cache_Controller.MT.L1_GETS 25597 0.00% 0.00% system.ruby.L2Cache_Controller.MT.L1_GETX 23984 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L1_PUTX 1685450 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L1_PUTX 1685453 0.00% 0.00% system.ruby.L2Cache_Controller.MT.L2_Replacement 121 0.00% 0.00% system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 104 0.00% 0.00% system.ruby.L2Cache_Controller.MT.MEM_Inv 230 0.00% 0.00% @@ -1219,15 +1219,15 @@ system.ruby.L2Cache_Controller.S_I.MEM_Inv 3 0.00% 0.00% system.ruby.L2Cache_Controller.ISS.Mem_Data 33914 0.00% 0.00% system.ruby.L2Cache_Controller.IS.Mem_Data 16316 0.00% 0.00% system.ruby.L2Cache_Controller.IM.Mem_Data 126982 0.00% 0.00% -system.ruby.L2Cache_Controller.SS_MB.L1_GETS 122 0.00% 0.00% +system.ruby.L2Cache_Controller.SS_MB.L1_GETS 124 0.00% 0.00% system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock 24399 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.L1_GETS 50 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.L1_GETS 48 0.00% 0.00% system.ruby.L2Cache_Controller.MT_MB.L1_GETX 2 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 1711768 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.WB_Data 23385 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 1711771 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.WB_Data 23386 0.00% 0.00% system.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean 2205 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.Unblock 11 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IB.WB_Data 11 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_SB.Unblock 25590 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.Unblock 10 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IB.WB_Data 10 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_SB.Unblock 25591 0.00% 0.00% ---------- End Simulation Statistics ---------- |