diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-05-30 12:54:18 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-05-30 12:54:18 -0400 |
| commit | 74553c7d3fc5430752c0c08f2b319a99fb7ed632 (patch) | |
| tree | 79b2a309fff0edaf1ef3e9aa62656904c3351650 /tests/long/fs | |
| parent | 3bc4ecdcb4785a976a1c3fd463bf7052b8415d8b (diff) | |
| download | gem5-74553c7d3fc5430752c0c08f2b319a99fb7ed632.tar.xz | |
stats: Update the stats to reflect bus and memory changes
This patch updates the stats to reflect the addition of the bus stats,
and changes to the bus layers. In addition it updates the stats to
match the addition of the static pipeline latency of the memory
conotroller and the addition of a stat tracking the bytes per
activate.
Diffstat (limited to 'tests/long/fs')
13 files changed, 17512 insertions, 13274 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 56627054e..8de825134 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,134 +1,134 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.896442 # Number of seconds simulated -sim_ticks 1896441913500 # Number of ticks simulated -final_tick 1896441913500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.903702 # Number of seconds simulated +sim_ticks 1903702212500 # Number of ticks simulated +final_tick 1903702212500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 132187 # Simulator instruction rate (inst/s) -host_op_rate 132187 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4418345683 # Simulator tick rate (ticks/s) -host_mem_usage 311512 # Number of bytes of host memory used -host_seconds 429.22 # Real time elapsed on the host -sim_insts 56737124 # Number of instructions simulated -sim_ops 56737124 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 937984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24915648 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2650688 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 39872 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 337088 # Number of bytes read from this memory -system.physmem.bytes_read::total 28881280 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 937984 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 39872 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 977856 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7850944 # Number of bytes written to this memory -system.physmem.bytes_written::total 7850944 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 14656 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 389307 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41417 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 623 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 5267 # Number of read requests responded to by this memory -system.physmem.num_reads::total 451270 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 122671 # Number of write requests responded to by this memory -system.physmem.num_writes::total 122671 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 494602 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 13138102 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1397716 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 21025 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 177748 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15229193 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 494602 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 21025 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 515627 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4139828 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4139828 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4139828 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 494602 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 13138102 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1397716 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 21025 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 177748 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19369021 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 451270 # Total number of read requests seen -system.physmem.writeReqs 122671 # Total number of write requests seen -system.physmem.cpureqs 578881 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 28881280 # Total number of bytes read from memory -system.physmem.bytesWritten 7850944 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28881280 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7850944 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 67 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4936 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28286 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 28331 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 28232 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 28037 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 28769 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 28511 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 28476 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 28312 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 28256 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 28154 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 28207 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 27864 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 27902 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 28010 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 27813 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 28043 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7715 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7756 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7743 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7541 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 8184 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7906 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7897 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7828 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7761 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7702 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7706 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7342 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7423 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7442 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7221 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7504 # Track writes on a per bank basis +host_inst_rate 94355 # Simulator instruction rate (inst/s) +host_op_rate 94355 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3162860632 # Simulator tick rate (ticks/s) +host_mem_usage 314400 # Number of bytes of host memory used +host_seconds 601.89 # Real time elapsed on the host +sim_insts 56791782 # Number of instructions simulated +sim_ops 56791782 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 898816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24768192 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2649600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 78528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 430592 # Number of bytes read from this memory +system.physmem.bytes_read::total 28825728 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 898816 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 78528 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 977344 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7790720 # Number of bytes written to this memory +system.physmem.bytes_written::total 7790720 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 14044 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 387003 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41400 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1227 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 6728 # Number of read requests responded to by this memory +system.physmem.num_reads::total 450402 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 121730 # Number of write requests responded to by this memory +system.physmem.num_writes::total 121730 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 472141 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 13010539 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1391814 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 41250 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 226187 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15141931 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 472141 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 41250 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 513391 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4092405 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4092405 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4092405 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 472141 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 13010539 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1391814 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 41250 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 226187 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19234336 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 450402 # Total number of read requests seen +system.physmem.writeReqs 121730 # Total number of write requests seen +system.physmem.cpureqs 577215 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28825728 # Total number of bytes read from memory +system.physmem.bytesWritten 7790720 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28825728 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7790720 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 61 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 5081 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 28459 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 28431 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 28031 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 27727 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 27674 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 28209 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 27366 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 27524 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 27697 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 28104 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 28295 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 28543 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 28907 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 28800 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 27954 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 28620 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 8184 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7919 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7522 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 7235 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7118 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7644 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 6911 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 6897 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7004 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7408 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7664 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7923 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 8310 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 8279 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7633 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 8079 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 4 # Number of times wr buffer was full causing retry -system.physmem.totGap 1896440622000 # Total gap between requests +system.physmem.numWrRetry 2 # Number of times wr buffer was full causing retry +system.physmem.totGap 1903701167000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 451270 # Categorize read packet sizes +system.physmem.readPktSize::6 450402 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 122671 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 320077 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 59739 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 33398 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 7716 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3200 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2984 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2709 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2710 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2673 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2618 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1536 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1465 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1405 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1359 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1357 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1405 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1629 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1501 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 921 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 776 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 16 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 121730 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 323323 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 65789 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 29264 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6597 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3337 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3029 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1570 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1545 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1498 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1465 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1430 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1420 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1390 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 2037 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 2367 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 2248 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1203 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 459 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 229 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 114 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see @@ -138,224 +138,395 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3224 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3863 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4392 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4442 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4963 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5320 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5328 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5330 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5330 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1471 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 942 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 892 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 371 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4 # What write queue length does an incoming req see -system.physmem.totQLat 7836942250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 15642141000 # Sum of mem lat for all requests -system.physmem.totBusLat 2256015000 # Total cycles spent in databus access -system.physmem.totBankLat 5549183750 # Total cycles spent in bank access -system.physmem.avgQLat 17368.99 # Average queueing delay per request -system.physmem.avgBankLat 12298.64 # Average bank access latency per request +system.physmem.wrQLenPdf::0 3688 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3914 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4977 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5279 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5284 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5285 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5290 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1605 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1379 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 316 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 3 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 40212 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 910.430717 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 224.153261 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 2362.806871 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 14303 35.57% 35.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 6082 15.12% 50.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 3751 9.33% 60.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 2511 6.24% 66.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 1745 4.34% 70.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 1426 3.55% 74.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 1071 2.66% 76.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 838 2.08% 78.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 669 1.66% 80.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 518 1.29% 81.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 558 1.39% 83.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 522 1.30% 84.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 270 0.67% 85.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 231 0.57% 85.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 190 0.47% 86.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 283 0.70% 86.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 119 0.30% 87.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 115 0.29% 87.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 106 0.26% 87.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 202 0.50% 88.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 170 0.42% 88.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 105 0.26% 88.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 478 1.19% 90.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 629 1.56% 91.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 105 0.26% 92.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 36 0.09% 92.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 35 0.09% 92.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 97 0.24% 92.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 29 0.07% 92.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 7 0.02% 92.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 13 0.03% 92.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 52 0.13% 92.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 26 0.06% 92.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 1 0.00% 92.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2243 6 0.01% 92.76% # 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Bytes accessed per row activation +system.physmem.bytesPerActivate::17536-17539 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 40212 # Bytes accessed per row activation +system.physmem.totQLat 6402871500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13861687750 # Sum of mem lat for all requests +system.physmem.totBusLat 2251705000 # Total cycles spent in databus access +system.physmem.totBankLat 5207111250 # Total cycles spent in bank access +system.physmem.avgQLat 14217.83 # Average queueing delay per request +system.physmem.avgBankLat 11562.60 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 34667.64 # Average memory access latency -system.physmem.avgRdBW 15.23 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 4.14 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 15.23 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 4.14 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 30780.43 # Average memory access latency +system.physmem.avgRdBW 15.14 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 4.09 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 15.14 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 4.09 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 10.84 # Average write queue length over time -system.physmem.readRowHits 423356 # Number of row buffer hits during reads -system.physmem.writeRowHits 94009 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.83 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 76.64 # Row buffer hit rate for writes -system.physmem.avgGap 3304243.16 # Average gap between requests -system.l2c.replacements 344349 # number of replacements -system.l2c.tagsinuse 65273.956353 # Cycle average of tags in use -system.l2c.total_refs 2577923 # Total number of references to valid blocks. -system.l2c.sampled_refs 409542 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.294649 # Average number of references to valid blocks. -system.l2c.warmup_cycle 5466319751 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 53748.349121 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 5295.726441 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 5975.264441 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 194.705269 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 59.911080 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.820135 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.080806 # 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mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.005427 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.006036 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.133237 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.940601 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.795359 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.892390 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.914343 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.949219 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.931953 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.428583 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.186907 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.401253 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.016172 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.305361 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005427 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.063410 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.165793 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.016172 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.305361 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005427 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.063410 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.165793 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 73909.060520 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 50443.521644 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 77712.510187 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 72273.242630 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 51731.979750 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10071.008172 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10008.064545 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10052.386869 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10047.803922 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10005.115226 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10025.849735 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 68696.865849 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 97466.194672 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 70212.348628 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 73909.060520 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 55816.241053 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 77712.510187 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 95828.745615 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 57164.832242 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 73909.060520 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 55816.241053 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 77712.510187 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 95828.745615 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 57164.832242 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -493,39 +664,39 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 41694 # number of replacements -system.iocache.tagsinuse 0.474409 # Cycle average of tags in use +system.iocache.replacements 41695 # number of replacements +system.iocache.tagsinuse 0.492474 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 41710 # Sample count of references to valid blocks. +system.iocache.sampled_refs 41711 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1705455708000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 0.474409 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.029651 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.029651 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses -system.iocache.ReadReq_misses::total 174 # number of ReadReq misses +system.iocache.warmup_cycle 1710349466000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 0.492474 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.030780 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.030780 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses +system.iocache.ReadReq_misses::total 175 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses -system.iocache.demand_misses::total 41726 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses -system.iocache.overall_misses::total 41726 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21041998 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21041998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 10633425431 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10633425431 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 10654467429 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10654467429 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 10654467429 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10654467429 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 41727 # number of demand (read+write) misses +system.iocache.demand_misses::total 41727 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 41727 # number of overall misses +system.iocache.overall_misses::total 41727 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 21568883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21568883 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 10518241771 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10518241771 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 10539810654 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10539810654 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 10539810654 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10539810654 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41727 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41727 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41727 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses @@ -534,40 +705,40 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120931.022989 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 120931.022989 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 255906.464936 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 255906.464936 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 255343.608997 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 255343.608997 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 255343.608997 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 255343.608997 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 285994 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 123250.760000 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 123250.760000 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 253134.428451 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 253134.428451 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 252589.705802 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 252589.705802 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 252589.705802 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 252589.705802 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 276539 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27316 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27281 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.469835 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.136689 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 175 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 175 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41726 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41726 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41726 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41726 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11993249 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 11993249 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8471449424 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8471449424 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 8483442673 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8483442673 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 8483442673 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8483442673 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 41727 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41727 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41727 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41727 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12468133 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12468133 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8356835276 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8356835276 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 8369303409 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8369303409 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 8369303409 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8369303409 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -576,14 +747,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68926.718391 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 68926.718391 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 203875.852522 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 203875.852522 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203313.106289 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 203313.106289 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203313.106289 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 203313.106289 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 71246.474286 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 71246.474286 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 201117.522045 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 201117.522045 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 200572.852326 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 200572.852326 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 200572.852326 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 200572.852326 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -597,35 +768,35 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 12584062 # Number of BP lookups -system.cpu0.branchPred.condPredicted 10588139 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 341886 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 8301483 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 5323497 # Number of BTB hits +system.cpu0.branchPred.lookups 12372167 # Number of BP lookups +system.cpu0.branchPred.condPredicted 10430268 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 327512 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 8051050 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 5251093 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 64.127060 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 804999 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 33376 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 65.222462 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 787082 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 28165 # Number of incorrect RAS predictions. system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 8950032 # DTB read hits -system.cpu0.dtb.read_misses 34820 # DTB read misses -system.cpu0.dtb.read_acv 539 # DTB read access violations -system.cpu0.dtb.read_accesses 674081 # DTB read accesses -system.cpu0.dtb.write_hits 5877992 # DTB write hits -system.cpu0.dtb.write_misses 8366 # DTB write misses -system.cpu0.dtb.write_acv 348 # DTB write access violations -system.cpu0.dtb.write_accesses 235610 # DTB write accesses -system.cpu0.dtb.data_hits 14828024 # DTB hits -system.cpu0.dtb.data_misses 43186 # DTB misses -system.cpu0.dtb.data_acv 887 # DTB access violations -system.cpu0.dtb.data_accesses 909691 # DTB accesses -system.cpu0.itb.fetch_hits 1040487 # ITB hits -system.cpu0.itb.fetch_misses 31672 # ITB misses -system.cpu0.itb.fetch_acv 1020 # ITB acv -system.cpu0.itb.fetch_accesses 1072159 # ITB accesses +system.cpu0.dtb.read_hits 8811099 # DTB read hits +system.cpu0.dtb.read_misses 30390 # DTB read misses +system.cpu0.dtb.read_acv 555 # DTB read access violations +system.cpu0.dtb.read_accesses 626499 # DTB read accesses +system.cpu0.dtb.write_hits 5759352 # DTB write hits +system.cpu0.dtb.write_misses 7345 # DTB write misses +system.cpu0.dtb.write_acv 331 # DTB write access violations +system.cpu0.dtb.write_accesses 208988 # DTB write accesses +system.cpu0.dtb.data_hits 14570451 # DTB hits +system.cpu0.dtb.data_misses 37735 # DTB misses +system.cpu0.dtb.data_acv 886 # DTB access violations +system.cpu0.dtb.data_accesses 835487 # DTB accesses +system.cpu0.itb.fetch_hits 988720 # ITB hits +system.cpu0.itb.fetch_misses 28459 # ITB misses +system.cpu0.itb.fetch_acv 940 # ITB acv +system.cpu0.itb.fetch_accesses 1017179 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -638,269 +809,269 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 103751291 # number of cpu cycles simulated +system.cpu0.numCycles 113576100 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 25592047 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 64430414 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 12584062 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 6128496 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 12114182 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1732019 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 37108557 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 31932 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 208707 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 355709 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 408 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 7808396 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 232068 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 76528583 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.841913 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.179850 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 24795587 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 63494847 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 12372167 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 6038175 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 11937811 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1694344 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 37245698 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 31806 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 195246 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 359396 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 148 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 7671411 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 221670 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 75653727 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.839282 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.177028 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 64414401 84.17% 84.17% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 777905 1.02% 85.19% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1574114 2.06% 87.24% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 716339 0.94% 88.18% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2604704 3.40% 91.58% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 529326 0.69% 92.28% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 586322 0.77% 93.04% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 831890 1.09% 94.13% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4493582 5.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 63715916 84.22% 84.22% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 763032 1.01% 85.23% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1559362 2.06% 87.29% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 696709 0.92% 88.21% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2577784 3.41% 91.62% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 516509 0.68% 92.30% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 573501 0.76% 93.06% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 819035 1.08% 94.14% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4431879 5.86% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 76528583 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.121291 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.621008 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 26850978 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 36641611 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 11018000 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 937421 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1080572 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 523116 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 36832 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 63252649 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 110299 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1080572 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 27872767 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 14726920 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 18377517 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 10342666 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 4128139 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 59880890 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 6989 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 638699 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1446922 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 40104744 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 72926681 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 72541237 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 385444 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 35232895 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 4871841 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1468873 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 214348 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 11259122 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9368607 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6150188 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1144221 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 763596 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 53152910 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1825418 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 51980474 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 87912 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 5962808 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 3052808 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1237037 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 76528583 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.679230 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.328773 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 75653727 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.108933 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.559051 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 26076145 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 36746783 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 10850479 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 927296 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1053023 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 507905 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 35356 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 62314637 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 105308 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1053023 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 27090322 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 15013520 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 18214120 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 10165522 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 4117218 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 58954969 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 7221 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 636497 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1465868 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 39489312 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 71817747 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 71438623 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 379124 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 34689683 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 4799621 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1442009 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 210125 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 11209509 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 9215492 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6028586 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1140138 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 729797 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 52283270 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1794569 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 51124724 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 87475 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 5854476 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 3047065 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1215266 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 75653727 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.675773 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.327184 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 53422858 69.81% 69.81% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 10519380 13.75% 83.55% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 4737419 6.19% 89.74% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3110993 4.07% 93.81% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2482363 3.24% 97.05% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1230781 1.61% 98.66% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 656198 0.86% 99.52% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 315996 0.41% 99.93% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 52595 0.07% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 52928215 69.96% 69.96% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 10364815 13.70% 83.66% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 4648030 6.14% 89.81% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 3048990 4.03% 93.84% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2439160 3.22% 97.06% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1210231 1.60% 98.66% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 645067 0.85% 99.51% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 315070 0.42% 99.93% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 54149 0.07% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 76528583 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 75653727 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 81649 11.89% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 319979 46.59% 58.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 285231 41.53% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 82277 12.13% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 315255 46.46% 58.59% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 280962 41.41% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 3782 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 35814992 68.90% 68.91% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 57898 0.11% 69.02% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.02% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 15714 0.03% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9315059 17.92% 86.97% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5946213 11.44% 98.41% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 824933 1.59% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 3785 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 35245093 68.94% 68.95% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 56186 0.11% 69.06% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.06% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 15594 0.03% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9165347 17.93% 87.02% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5826893 11.40% 98.42% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 809947 1.58% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 51980474 # Type of FU issued -system.cpu0.iq.rate 0.501010 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 686859 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.013214 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 180712322 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 60686814 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 50945996 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 551979 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 267326 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 260492 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 52374713 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 288838 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 545458 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 51124724 # Type of FU issued +system.cpu0.iq.rate 0.450136 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 678494 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.013271 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 178124739 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 59681238 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 50082929 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 544404 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 263662 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 256861 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 51514533 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 284900 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 542155 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1121947 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2762 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13266 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 454260 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1111126 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3856 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 12844 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 447697 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18544 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 124618 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18437 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 153340 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1080572 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 10513662 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 794213 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 58228726 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 618999 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9368607 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6150188 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1608738 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 580049 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 5099 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13266 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 168319 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 356582 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 524901 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 51585627 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9008604 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 394846 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1053023 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 10729289 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 792549 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 57283617 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 622169 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 9215492 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6028586 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1581349 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 577410 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 6280 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 12844 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 162347 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 348099 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 510446 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 50735914 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 8864635 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 388809 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3250398 # number of nop insts executed -system.cpu0.iew.exec_refs 14908735 # number of memory reference insts executed -system.cpu0.iew.exec_branches 8218209 # Number of branches executed -system.cpu0.iew.exec_stores 5900131 # Number of stores executed -system.cpu0.iew.exec_rate 0.497205 # Inst execution rate -system.cpu0.iew.wb_sent 51301062 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 51206488 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 25493361 # num instructions producing a value -system.cpu0.iew.wb_consumers 34352042 # num instructions consuming a value +system.cpu0.iew.exec_nop 3205778 # number of nop insts executed +system.cpu0.iew.exec_refs 14644864 # number of memory reference insts executed +system.cpu0.iew.exec_branches 8078425 # Number of branches executed +system.cpu0.iew.exec_stores 5780229 # Number of stores executed +system.cpu0.iew.exec_rate 0.446713 # Inst execution rate +system.cpu0.iew.wb_sent 50428595 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 50339790 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 25084021 # num instructions producing a value +system.cpu0.iew.wb_consumers 33790368 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.493550 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.742121 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.443225 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.742342 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6443785 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 588381 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 491234 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 75448011 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.685042 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.601476 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6311482 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 579303 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 475138 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 74600704 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.681919 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.596319 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 56013876 74.24% 74.24% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 8117892 10.76% 85.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 4422865 5.86% 90.86% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2392310 3.17% 94.03% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1343441 1.78% 95.81% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 564278 0.75% 96.56% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 477580 0.63% 97.20% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 442296 0.59% 97.78% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1673473 2.22% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 55419889 74.29% 74.29% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 8033545 10.77% 85.06% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 4371447 5.86% 90.92% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2356278 3.16% 94.08% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1324268 1.78% 95.85% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 555518 0.74% 96.60% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 469565 0.63% 97.22% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 427219 0.57% 97.80% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1642975 2.20% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 75448011 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 51685042 # Number of instructions committed -system.cpu0.commit.committedOps 51685042 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 74600704 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 50871658 # Number of instructions committed +system.cpu0.commit.committedOps 50871658 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13942588 # Number of memory references committed -system.cpu0.commit.loads 8246660 # Number of loads committed -system.cpu0.commit.membars 199926 # Number of memory barriers committed -system.cpu0.commit.branches 7810095 # Number of branches committed -system.cpu0.commit.fp_insts 258326 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 47876421 # Number of committed integer instructions. -system.cpu0.commit.function_calls 664533 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1673473 # number cycles where commit BW limit reached +system.cpu0.commit.refs 13685255 # Number of memory references committed +system.cpu0.commit.loads 8104366 # Number of loads committed +system.cpu0.commit.membars 196950 # Number of memory barriers committed +system.cpu0.commit.branches 7686240 # Number of branches committed +system.cpu0.commit.fp_insts 254806 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 47114322 # Number of committed integer instructions. +system.cpu0.commit.function_calls 650737 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1642975 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 131700376 # The number of ROB reads -system.cpu0.rob.rob_writes 117338865 # The number of ROB writes -system.cpu0.timesIdled 1069961 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 27222708 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3689125904 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 48725185 # Number of Instructions Simulated -system.cpu0.committedOps 48725185 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 48725185 # Number of Instructions Simulated -system.cpu0.cpi 2.129315 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.129315 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.469634 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.469634 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 67898060 # number of integer regfile reads -system.cpu0.int_regfile_writes 37063784 # number of integer regfile writes -system.cpu0.fp_regfile_reads 127956 # number of floating regfile reads -system.cpu0.fp_regfile_writes 129360 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1719000 # number of misc regfile reads -system.cpu0.misc_regfile_writes 824833 # number of misc regfile writes +system.cpu0.rob.rob_reads 129943858 # The number of ROB reads +system.cpu0.rob.rob_writes 115419344 # The number of ROB writes +system.cpu0.timesIdled 1091777 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 37922373 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3693821721 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 47948786 # Number of Instructions Simulated +system.cpu0.committedOps 47948786 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 47948786 # Number of Instructions Simulated +system.cpu0.cpi 2.368696 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.368696 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.422173 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.422173 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 66777793 # number of integer regfile reads +system.cpu0.int_regfile_writes 36448823 # number of integer regfile writes +system.cpu0.fp_regfile_reads 126128 # number of floating regfile reads +system.cpu0.fp_regfile_writes 127569 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1693303 # number of misc regfile reads +system.cpu0.misc_regfile_writes 810480 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -932,245 +1103,375 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 889638 # number of replacements -system.cpu0.icache.tagsinuse 510.303457 # Cycle average of tags in use -system.cpu0.icache.total_refs 6872883 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 890147 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 7.721065 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 20517812000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 510.303457 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.996686 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.996686 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 6872883 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 6872883 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 6872883 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 6872883 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 6872883 # number of overall hits -system.cpu0.icache.overall_hits::total 6872883 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 935512 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 935512 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 935512 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 935512 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 935512 # number of overall misses -system.cpu0.icache.overall_misses::total 935512 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13284271991 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 13284271991 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 13284271991 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 13284271991 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 13284271991 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 13284271991 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 7808395 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 7808395 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 7808395 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 7808395 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 7808395 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 7808395 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.119808 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.119808 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.119808 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.119808 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.119808 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.119808 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14200.001701 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14200.001701 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14200.001701 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14200.001701 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14200.001701 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14200.001701 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 5547 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 2537 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 162 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 3 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 34.240741 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 845.666667 # average number of cycles each access was blocked +system.toL2Bus.throughput 111431458 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2199741 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2199647 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 13135 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 13135 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 819443 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 10566 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 6236 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 16802 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 343057 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 301508 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 77 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 1737096 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 3343563 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 452207 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 314296 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count 5847162 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 55584064 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 129094452 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 14469760 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 11514982 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size 210663258 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 210652954 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 1479360 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4959879460 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 3910967404 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 5778463419 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 1017961113 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 540290711 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.throughput 1437243 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 7369 # Transaction distribution +system.iobus.trans_dist::ReadResp 7369 # Transaction distribution +system.iobus.trans_dist::WriteReq 54687 # Transaction distribution +system.iobus.trans_dist::WriteResp 54687 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 12062 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 40658 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.cchip.pio 12062 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 124112 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 48248 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 74458 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.cchip.pio 48248 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 2736082 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 2736082 # Total data (bytes) +system.iobus.reqLayer0.occupancy 11417000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) +system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 13505000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer24.occupancy 2450000 # Layer occupancy (ticks) +system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) +system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) +system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer29.occupancy 378279654 # Layer occupancy (ticks) +system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 27523000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer1.occupancy 42014000 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu0.icache.replacements 867916 # number of replacements +system.cpu0.icache.tagsinuse 509.785268 # Cycle average of tags in use +system.cpu0.icache.total_refs 6758563 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 868427 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 7.782534 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 25769681000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 509.785268 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.995674 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.995674 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 6758564 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 6758564 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 6758564 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 6758564 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 6758564 # number of overall hits +system.cpu0.icache.overall_hits::total 6758564 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 912847 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 912847 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 912847 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 912847 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 912847 # number of overall misses +system.cpu0.icache.overall_misses::total 912847 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13149310993 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 13149310993 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 13149310993 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 13149310993 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 13149310993 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 13149310993 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 7671411 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 7671411 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 7671411 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 7671411 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 7671411 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 7671411 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.118993 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.118993 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.118993 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.118993 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.118993 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.118993 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14404.726086 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14404.726086 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14404.726086 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14404.726086 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14404.726086 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14404.726086 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 3418 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 152 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 22.486842 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 45203 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 45203 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 45203 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 45203 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 45203 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 45203 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 890309 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 890309 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 890309 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 890309 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 890309 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 890309 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10926647992 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 10926647992 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10926647992 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 10926647992 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10926647992 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 10926647992 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.114019 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.114019 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.114019 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.114019 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.114019 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.114019 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12272.871545 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12272.871545 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12272.871545 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12272.871545 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12272.871545 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12272.871545 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 44252 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 44252 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 44252 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 44252 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 44252 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 44252 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 868595 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 868595 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 868595 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 868595 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 868595 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 868595 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10814937089 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 10814937089 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10814937089 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 10814937089 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10814937089 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 10814937089 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.113225 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.113225 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.113225 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.113225 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.113225 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.113225 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12451.069934 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12451.069934 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12451.069934 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12451.069934 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12451.069934 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12451.069934 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1284134 # number of replacements -system.cpu0.dcache.tagsinuse 505.722211 # Cycle average of tags in use -system.cpu0.dcache.total_refs 10611019 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1284646 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 8.259878 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 22124000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 505.722211 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.987739 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.987739 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6528989 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6528989 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3717707 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3717707 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 164546 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 164546 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 188999 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 188999 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10246696 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10246696 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10246696 # number of overall hits -system.cpu0.dcache.overall_hits::total 10246696 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1596925 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1596925 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1771522 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1771522 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20418 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 20418 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2763 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 2763 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3368447 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3368447 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3368447 # number of overall misses -system.cpu0.dcache.overall_misses::total 3368447 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 34533208000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 34533208000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 68837486976 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 68837486976 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 293802000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 293802000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 20678500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 20678500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 103370694976 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 103370694976 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 103370694976 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 103370694976 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8125914 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8125914 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5489229 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5489229 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 184964 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 184964 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 191762 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 191762 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13615143 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 13615143 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13615143 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 13615143 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.196523 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.196523 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.322727 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.322727 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.110389 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.110389 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.014408 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.014408 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.247404 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.247404 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.247404 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.247404 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 21624.815192 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 21624.815192 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38857.822243 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 38857.822243 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14389.362327 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14389.362327 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7484.075280 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7484.075280 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 30687.938678 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 30687.938678 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 30687.938678 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 30687.938678 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 2260715 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 560 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 49054 # number of cycles access was blocked +system.cpu0.dcache.replacements 1271376 # number of replacements +system.cpu0.dcache.tagsinuse 505.686526 # Cycle average of tags in use +system.cpu0.dcache.total_refs 10390956 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1271888 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 8.169710 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 25830000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 505.686526 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.987669 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.987669 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6393137 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6393137 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3639350 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3639350 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 161427 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 161427 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 185616 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 185616 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10032487 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10032487 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10032487 # number of overall hits +system.cpu0.dcache.overall_hits::total 10032487 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1573505 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1573505 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1738147 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1738147 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20045 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 20045 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 3020 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 3020 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3311652 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3311652 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3311652 # number of overall misses +system.cpu0.dcache.overall_misses::total 3311652 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 39654304500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 39654304500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 77521243901 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 77521243901 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 292960500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 292960500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 22204000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 22204000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 117175548401 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 117175548401 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 117175548401 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 117175548401 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7966642 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7966642 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5377497 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5377497 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 181472 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 181472 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 188636 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 188636 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 13344139 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 13344139 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13344139 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 13344139 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.197512 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.197512 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.323226 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.323226 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.110458 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.110458 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.016010 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.016010 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.248173 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.248173 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.248173 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.248173 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25201.257384 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 25201.257384 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44599.935392 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 44599.935392 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14615.140933 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14615.140933 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7352.317881 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7352.317881 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35382.808460 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 35382.808460 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35382.808460 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 35382.808460 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 2842539 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 840 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 51698 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 46.086252 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 80 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 54.983539 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 120 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 757117 # number of writebacks -system.cpu0.dcache.writebacks::total 757117 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 591865 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 591865 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1494302 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1494302 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4660 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4660 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 2086167 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 2086167 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 2086167 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 2086167 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1005060 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1005060 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 277220 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 277220 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15758 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15758 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2763 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 2763 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1282280 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1282280 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1282280 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1282280 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 21590310000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 21590310000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10033221203 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10033221203 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 180646500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 180646500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 15152500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 15152500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 31623531203 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 31623531203 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 31623531203 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 31623531203 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465155500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465155500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2167706499 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2167706499 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3632861999 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3632861999 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.123686 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.123686 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050503 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050503 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.085195 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.085195 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.014408 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.014408 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.094180 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.094180 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.094180 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.094180 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 21481.613038 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 21481.613038 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36192.270410 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36192.270410 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11463.796167 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11463.796167 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5484.075280 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5484.075280 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24661.954646 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24661.954646 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24661.954646 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24661.954646 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 746874 # number of writebacks +system.cpu0.dcache.writebacks::total 746874 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 575080 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 575080 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1465992 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1465992 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4461 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4461 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 2041072 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 2041072 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 2041072 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 2041072 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 998425 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 998425 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 272155 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 272155 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15584 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15584 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 3020 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 3020 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1270580 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1270580 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1270580 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1270580 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 26454916051 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 26454916051 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11388682739 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11388682739 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 172348003 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 172348003 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 16164000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 16164000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 37843598790 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 37843598790 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 37843598790 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 37843598790 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1459347502 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1459347502 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2156087498 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2156087498 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3615435000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3615435000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.125326 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.125326 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050610 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050610 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.085876 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.085876 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.016010 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.016010 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.095216 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.095216 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.095216 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.095216 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26496.648272 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26496.648272 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41846.310885 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41846.310885 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11059.291774 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11059.291774 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5352.317881 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5352.317881 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29784.506910 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29784.506910 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29784.506910 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29784.506910 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1178,35 +1479,35 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 2374472 # Number of BP lookups -system.cpu1.branchPred.condPredicted 1973565 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 63683 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 1357670 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 789569 # Number of BTB hits +system.cpu1.branchPred.lookups 2604526 # Number of BP lookups +system.cpu1.branchPred.condPredicted 2153409 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 75247 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 1513707 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 876072 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 58.156179 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 159848 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 6979 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 57.875930 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 179167 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 7740 # Number of incorrect RAS predictions. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1755569 # DTB read hits -system.cpu1.dtb.read_misses 9259 # DTB read misses -system.cpu1.dtb.read_acv 6 # DTB read access violations -system.cpu1.dtb.read_accesses 277737 # DTB read accesses -system.cpu1.dtb.write_hits 1124169 # DTB write hits -system.cpu1.dtb.write_misses 1775 # DTB write misses -system.cpu1.dtb.write_acv 38 # DTB write access violations -system.cpu1.dtb.write_accesses 104346 # DTB write accesses -system.cpu1.dtb.data_hits 2879738 # DTB hits -system.cpu1.dtb.data_misses 11034 # DTB misses -system.cpu1.dtb.data_acv 44 # DTB access violations -system.cpu1.dtb.data_accesses 382083 # DTB accesses -system.cpu1.itb.fetch_hits 378886 # ITB hits -system.cpu1.itb.fetch_misses 5643 # ITB misses -system.cpu1.itb.fetch_acv 144 # ITB acv -system.cpu1.itb.fetch_accesses 384529 # ITB accesses +system.cpu1.dtb.read_hits 1932131 # DTB read hits +system.cpu1.dtb.read_misses 10237 # DTB read misses +system.cpu1.dtb.read_acv 25 # DTB read access violations +system.cpu1.dtb.read_accesses 320506 # DTB read accesses +system.cpu1.dtb.write_hits 1251341 # DTB write hits +system.cpu1.dtb.write_misses 1962 # DTB write misses +system.cpu1.dtb.write_acv 65 # DTB write access violations +system.cpu1.dtb.write_accesses 130037 # DTB write accesses +system.cpu1.dtb.data_hits 3183472 # DTB hits +system.cpu1.dtb.data_misses 12199 # DTB misses +system.cpu1.dtb.data_acv 90 # DTB access violations +system.cpu1.dtb.data_accesses 450543 # DTB accesses +system.cpu1.itb.fetch_hits 430844 # ITB hits +system.cpu1.itb.fetch_misses 6753 # ITB misses +system.cpu1.itb.fetch_acv 212 # ITB acv +system.cpu1.itb.fetch_accesses 437597 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1219,512 +1520,508 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 14403389 # number of cpu cycles simulated +system.cpu1.numCycles 15794943 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 5507969 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 11118541 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 2374472 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 949417 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 1985955 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 349018 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 5777579 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 25749 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 54503 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 55745 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 7 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1323443 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 42238 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 13629786 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.815753 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.191288 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 6044274 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 12313553 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 2604526 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 1055239 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 2204838 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 395965 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 6209579 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 26246 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 62195 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 53260 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 20 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 1481011 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 50405 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 14852690 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.829045 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.204427 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 11643831 85.43% 85.43% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 125140 0.92% 86.35% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 217081 1.59% 87.94% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 155934 1.14% 89.08% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 266080 1.95% 91.04% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 106134 0.78% 91.82% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 117650 0.86% 92.68% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 192941 1.42% 94.09% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 804995 5.91% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 12647852 85.16% 85.16% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 141564 0.95% 86.11% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 235652 1.59% 87.70% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 175889 1.18% 88.88% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 303768 2.05% 90.92% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 119285 0.80% 91.73% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 129403 0.87% 92.60% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 209113 1.41% 94.01% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 890164 5.99% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 13629786 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.164855 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.771939 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 5440584 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 6013692 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 1859543 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 99467 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 216499 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 99353 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 5852 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 10916304 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 17556 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 216499 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 5632614 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 346968 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 5076489 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 1765081 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 592133 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 10097386 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 38 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 55596 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 134498 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 6632848 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 12019300 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 11877082 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 142218 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 5717715 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 915133 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 422143 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 38586 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 1845577 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 1850340 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1191384 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 164933 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 85198 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 8855097 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 461396 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 8635428 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 27588 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1251794 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 621930 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 331901 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 13629786 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.633570 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.306468 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 14852690 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.164896 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.779588 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 5971093 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 6462269 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 2062064 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 112088 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 245175 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 113398 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 7205 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 12081319 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 21458 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 245175 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 6179272 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 425366 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 5395094 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 1962879 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 644902 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 11197795 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 87 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 57093 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 157527 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 7361429 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 13363056 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 13213666 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 149390 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 6300177 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1061252 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 451071 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 42573 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 1993362 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 2041709 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1326014 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 180090 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 100258 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 9822573 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 491625 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 9565946 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 29815 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1410113 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 705464 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 352077 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 14852690 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.644055 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.318534 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 9807862 71.96% 71.96% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 1774840 13.02% 84.98% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 743934 5.46% 90.44% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 492954 3.62% 94.06% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 425816 3.12% 97.18% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 193635 1.42% 98.60% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 119802 0.88% 99.48% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 63937 0.47% 99.95% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 7006 0.05% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 10648951 71.70% 71.70% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 1930050 12.99% 84.69% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 818337 5.51% 90.20% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 551122 3.71% 93.91% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 476075 3.21% 97.12% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 213789 1.44% 98.56% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 136394 0.92% 99.48% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 69529 0.47% 99.94% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 8443 0.06% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 13629786 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 14852690 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 2819 1.60% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 95112 53.88% 55.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 78586 44.52% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 3207 1.63% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 106178 53.97% 55.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 87357 44.40% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3518 0.04% 0.04% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 5368636 62.17% 62.21% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 14579 0.17% 62.38% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.38% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 10813 0.13% 62.50% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.50% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.50% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.50% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1759 0.02% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 1836056 21.26% 83.79% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1146030 13.27% 97.06% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 254037 2.94% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3526 0.04% 0.04% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 5966011 62.37% 62.40% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 16243 0.17% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 10971 0.11% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1763 0.02% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 2021702 21.13% 83.84% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1274955 13.33% 97.17% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 270775 2.83% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 8635428 # Type of FU issued -system.cpu1.iq.rate 0.599541 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 176517 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.020441 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 30899211 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 10469267 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 8392820 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 205536 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 100351 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 97198 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 8701253 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 107174 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 85247 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 9565946 # Type of FU issued +system.cpu1.iq.rate 0.605633 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 196742 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.020567 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 33995446 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 11620704 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 9288457 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 215693 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 105258 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 101999 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 9646700 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 112462 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 92569 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 244767 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 715 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 1400 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 111607 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 282729 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 1535 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 1711 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 123624 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 264 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 8613 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 323 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 14236 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 216499 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 208020 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 39541 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 9780313 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 131211 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 1850340 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1191384 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 418145 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 33976 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 1692 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 1400 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 28557 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 89287 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 117844 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 8559872 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 1771461 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 75556 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 245175 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 256542 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 43339 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 10829040 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 147658 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 2041709 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1326014 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 444647 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 36382 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 1620 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 1711 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 33953 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 99696 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 133649 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 9473535 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 1949759 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 92411 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 463820 # number of nop insts executed -system.cpu1.iew.exec_refs 2903123 # number of memory reference insts executed -system.cpu1.iew.exec_branches 1270722 # Number of branches executed -system.cpu1.iew.exec_stores 1131662 # Number of stores executed -system.cpu1.iew.exec_rate 0.594296 # Inst execution rate -system.cpu1.iew.wb_sent 8515413 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 8490018 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 3998147 # num instructions producing a value -system.cpu1.iew.wb_consumers 5641896 # num instructions consuming a value +system.cpu1.iew.exec_nop 514842 # number of nop insts executed +system.cpu1.iew.exec_refs 3209162 # number of memory reference insts executed +system.cpu1.iew.exec_branches 1413585 # Number of branches executed +system.cpu1.iew.exec_stores 1259403 # Number of stores executed +system.cpu1.iew.exec_rate 0.599783 # Inst execution rate +system.cpu1.iew.wb_sent 9417236 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 9390456 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 4401006 # num instructions producing a value +system.cpu1.iew.wb_consumers 6190652 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.589446 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.708653 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.594523 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.710912 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 1285480 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 129495 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 111745 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 13413287 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.628190 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.573982 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 1449457 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 139548 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 125475 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 14607515 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.636458 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.578813 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 10261662 76.50% 76.50% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1478959 11.03% 87.53% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 542849 4.05% 91.58% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 333012 2.48% 94.06% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 234215 1.75% 95.81% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 91771 0.68% 96.49% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 99946 0.75% 97.24% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 99972 0.75% 97.98% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 270901 2.02% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 11126487 76.17% 76.17% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 1625013 11.12% 87.29% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 604004 4.13% 91.43% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 371910 2.55% 93.98% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 263907 1.81% 95.78% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 102565 0.70% 96.48% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 109537 0.75% 97.23% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 110097 0.75% 97.99% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 293995 2.01% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 13413287 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 8426096 # Number of instructions committed -system.cpu1.commit.committedOps 8426096 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 14607515 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 9297065 # Number of instructions committed +system.cpu1.commit.committedOps 9297065 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 2685350 # Number of memory references committed -system.cpu1.commit.loads 1605573 # Number of loads committed -system.cpu1.commit.membars 41432 # Number of memory barriers committed -system.cpu1.commit.branches 1197085 # Number of branches committed -system.cpu1.commit.fp_insts 95994 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 7795496 # Number of committed integer instructions. -system.cpu1.commit.function_calls 132738 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 270901 # number cycles where commit BW limit reached +system.cpu1.commit.refs 2961370 # Number of memory references committed +system.cpu1.commit.loads 1758980 # Number of loads committed +system.cpu1.commit.membars 44792 # Number of memory barriers committed +system.cpu1.commit.branches 1328076 # Number of branches committed +system.cpu1.commit.fp_insts 100787 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 8610735 # Number of committed integer instructions. +system.cpu1.commit.function_calls 147103 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 293995 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 22771832 # The number of ROB reads -system.cpu1.rob.rob_writes 19637981 # The number of ROB writes -system.cpu1.timesIdled 118769 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 773603 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3777797828 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 8011939 # Number of Instructions Simulated -system.cpu1.committedOps 8011939 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 8011939 # Number of Instructions Simulated -system.cpu1.cpi 1.797741 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.797741 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.556254 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.556254 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 11010177 # number of integer regfile reads -system.cpu1.int_regfile_writes 6039470 # number of integer regfile writes -system.cpu1.fp_regfile_reads 53089 # number of floating regfile reads -system.cpu1.fp_regfile_writes 52904 # number of floating regfile writes -system.cpu1.misc_regfile_reads 494875 # number of misc regfile reads -system.cpu1.misc_regfile_writes 202385 # number of misc regfile writes -system.cpu1.icache.replacements 202443 # number of replacements -system.cpu1.icache.tagsinuse 470.727745 # Cycle average of tags in use -system.cpu1.icache.total_refs 1113774 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 202955 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 5.487788 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1886714019000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 470.727745 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.919390 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.919390 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 1113774 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1113774 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 1113774 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1113774 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 1113774 # number of overall hits -system.cpu1.icache.overall_hits::total 1113774 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 209669 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 209669 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 209669 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 209669 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 209669 # number of overall misses -system.cpu1.icache.overall_misses::total 209669 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 2812457500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 2812457500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 2812457500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 2812457500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 2812457500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 2812457500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 1323443 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1323443 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1323443 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1323443 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1323443 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1323443 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.158427 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.158427 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.158427 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.158427 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.158427 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.158427 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13413.797462 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13413.797462 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13413.797462 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13413.797462 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13413.797462 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13413.797462 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 72 # number of cycles access was blocked +system.cpu1.rob.rob_reads 24970897 # The number of ROB reads +system.cpu1.rob.rob_writes 21736671 # The number of ROB writes +system.cpu1.timesIdled 134601 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 942253 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3790981004 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 8842996 # Number of Instructions Simulated +system.cpu1.committedOps 8842996 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 8842996 # Number of Instructions Simulated +system.cpu1.cpi 1.786153 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.786153 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.559862 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.559862 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 12205153 # number of integer regfile reads +system.cpu1.int_regfile_writes 6674473 # number of integer regfile writes +system.cpu1.fp_regfile_reads 55471 # number of floating regfile reads +system.cpu1.fp_regfile_writes 55305 # number of floating regfile writes +system.cpu1.misc_regfile_reads 527113 # number of misc regfile reads +system.cpu1.misc_regfile_writes 218222 # number of misc regfile writes +system.cpu1.icache.replacements 225540 # number of replacements +system.cpu1.icache.tagsinuse 470.721925 # Cycle average of tags in use +system.cpu1.icache.total_refs 1246547 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 226052 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 5.514426 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1877726350000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 470.721925 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.919379 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.919379 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 1246547 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1246547 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1246547 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 1246547 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 1246547 # number of overall hits +system.cpu1.icache.overall_hits::total 1246547 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 234464 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 234464 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 234464 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 234464 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 234464 # number of overall misses +system.cpu1.icache.overall_misses::total 234464 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3166624000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 3166624000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 3166624000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 3166624000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 3166624000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 3166624000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 1481011 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1481011 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 1481011 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 1481011 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 1481011 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 1481011 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.158313 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.158313 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.158313 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.158313 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.158313 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.158313 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13505.800464 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13505.800464 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13505.800464 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13505.800464 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13505.800464 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13505.800464 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 237 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 9 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 27 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 8 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 8.777778 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 6654 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 6654 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 6654 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 6654 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 6654 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 6654 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 203015 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 203015 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 203015 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 203015 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 203015 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 203015 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2347033500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 2347033500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2347033500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 2347033500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2347033500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 2347033500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.153399 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.153399 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.153399 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.153399 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.153399 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.153399 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11560.887127 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11560.887127 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11560.887127 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11560.887127 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11560.887127 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11560.887127 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 8347 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 8347 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 8347 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 8347 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 8347 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 8347 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 226117 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 226117 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 226117 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 226117 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 226117 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 226117 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2628094387 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 2628094387 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2628094387 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 2628094387 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2628094387 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 2628094387 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.152677 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.152677 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.152677 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.152677 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.152677 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.152677 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11622.719154 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11622.719154 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11622.719154 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11622.719154 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11622.719154 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11622.719154 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 95898 # number of replacements -system.cpu1.dcache.tagsinuse 491.044785 # Cycle average of tags in use -system.cpu1.dcache.total_refs 2359205 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 96213 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 24.520647 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 39003208000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 491.044785 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.959072 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.959072 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 1444297 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1444297 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 860369 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 860369 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 29709 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 29709 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 28445 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 28445 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 2304666 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 2304666 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 2304666 # number of overall hits -system.cpu1.dcache.overall_hits::total 2304666 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 191100 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 191100 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 182257 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 182257 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 4958 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 4958 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 3002 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 3002 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 373357 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 373357 # 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Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 43858959000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 491.736427 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.960423 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.960423 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 1587502 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1587502 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 943251 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 943251 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 32579 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 32579 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 31559 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 31559 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 2530753 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 2530753 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 2530753 # number of overall hits +system.cpu1.dcache.overall_hits::total 2530753 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 209244 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 209244 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 218379 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 218379 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5510 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 5510 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 3216 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 3216 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 427623 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 427623 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 427623 # number of overall misses +system.cpu1.dcache.overall_misses::total 427623 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2938034500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2938034500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 7305073698 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 7305073698 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 55149000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 55149000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 23385500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 23385500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 10243108198 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 10243108198 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 10243108198 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 10243108198 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 1796746 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 1796746 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1161630 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1161630 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 38089 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 38089 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 34775 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 34775 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 2958376 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 2958376 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 2958376 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 2958376 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.116457 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.116457 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.187994 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.187994 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.144661 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.144661 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.092480 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.092480 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.144547 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.144547 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.144547 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.144547 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14041.188756 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14041.188756 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 33451.356119 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 33451.356119 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10008.892922 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10008.892922 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7271.610697 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7271.610697 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23953.595101 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 23953.595101 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23953.595101 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 23953.595101 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 227083 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 3033 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 4054 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 58.786020 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 56.014554 # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 62482 # number of writebacks -system.cpu1.dcache.writebacks::total 62482 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 119560 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 119560 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 148811 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 148811 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 417 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 417 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 268371 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 268371 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 268371 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 268371 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 71540 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 71540 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 33446 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 33446 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4541 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4541 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 3000 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 3000 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 104986 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 104986 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 104986 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 104986 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 843257000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 843257000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 841845993 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 841845993 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 36401500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 36401500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 16047000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 16047000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1685102993 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 1685102993 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1685102993 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 1685102993 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18098500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18098500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 603885500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 603885500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 621984000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 621984000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.043745 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.043745 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.032079 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.032079 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.130989 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.130989 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.095399 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.095399 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.039203 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.039203 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.039203 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.039203 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11787.209952 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11787.209952 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 25170.304162 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 25170.304162 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8016.185862 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8016.185862 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5349 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5349 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16050.740032 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16050.740032 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16050.740032 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16050.740032 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 72569 # number of writebacks +system.cpu1.dcache.writebacks::total 72569 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 129770 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 129770 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 179212 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 179212 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 594 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 594 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 308982 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 308982 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 308982 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 308982 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 79474 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 79474 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 39167 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 39167 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4916 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4916 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 3216 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 3216 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 118641 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 118641 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 118641 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 118641 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 893939249 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 893939249 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1081571527 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1081571527 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 37210004 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 37210004 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 16953500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 16953500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1975510776 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 1975510776 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1975510776 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 1975510776 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 23615501 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 23615501 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 628297501 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 628297501 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 651913002 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 651913002 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.044232 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.044232 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033717 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.033717 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.129066 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.129066 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.092480 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.092480 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.040103 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.040103 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.040103 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.040103 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11248.197511 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11248.197511 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27614.357163 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27614.357163 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7569.162734 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7569.162734 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5271.610697 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5271.610697 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16651.164235 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16651.164235 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16651.164235 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16651.164235 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1733,161 +2030,170 @@ system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6633 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 185817 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 65566 40.59% 40.59% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.08% 40.67% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1923 1.19% 41.86% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 201 0.12% 41.99% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 93709 58.01% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 161530 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 64589 49.22% 49.22% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.10% 49.32% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1923 1.47% 50.78% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 201 0.15% 50.94% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 64388 49.06% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 131232 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1860847795500 98.12% 98.12% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 64543000 0.00% 98.13% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 567978500 0.03% 98.16% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 98193500 0.01% 98.16% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 34862560000 1.84% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1896441070500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.985099 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6605 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 182638 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 64421 40.50% 40.50% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.08% 40.58% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1925 1.21% 41.79% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 210 0.13% 41.93% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 92368 58.07% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 159055 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 63463 49.20% 49.20% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.10% 49.30% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1925 1.49% 50.80% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 210 0.16% 50.96% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 63253 49.04% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 128982 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1863089530500 97.87% 97.87% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 64074500 0.00% 97.87% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 567937500 0.03% 97.90% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 100797000 0.01% 97.91% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 39879064000 2.09% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1903701403500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.985129 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.687106 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.812431 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed -system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed -system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed -system.cpu0.kern.syscall::6 33 14.10% 27.78% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.43% 28.21% # number of syscalls executed -system.cpu0.kern.syscall::17 10 4.27% 32.48% # number of syscalls executed -system.cpu0.kern.syscall::19 10 4.27% 36.75% # number of syscalls executed -system.cpu0.kern.syscall::20 6 2.56% 39.32% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.43% 39.74% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.28% 41.03% # number of syscalls executed -system.cpu0.kern.syscall::33 8 3.42% 44.44% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.85% 45.30% # number of syscalls executed -system.cpu0.kern.syscall::45 39 16.67% 61.97% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.28% 63.25% # number of syscalls executed -system.cpu0.kern.syscall::48 10 4.27% 67.52% # number of syscalls executed -system.cpu0.kern.syscall::54 10 4.27% 71.79% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.43% 72.22% # number of syscalls executed -system.cpu0.kern.syscall::59 6 2.56% 74.79% # number of syscalls executed -system.cpu0.kern.syscall::71 27 11.54% 86.32% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.28% 87.61% # number of syscalls executed -system.cpu0.kern.syscall::74 7 2.99% 90.60% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.43% 91.03% # number of syscalls executed -system.cpu0.kern.syscall::90 3 1.28% 92.31% # number of syscalls executed -system.cpu0.kern.syscall::92 9 3.85% 96.15% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.85% 97.01% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.85% 97.86% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.43% 98.29% # number of syscalls executed -system.cpu0.kern.syscall::144 2 0.85% 99.15% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.85% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 234 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.684793 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.810927 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 7 3.32% 3.32% # number of syscalls executed +system.cpu0.kern.syscall::3 17 8.06% 11.37% # number of syscalls executed +system.cpu0.kern.syscall::4 4 1.90% 13.27% # number of syscalls executed +system.cpu0.kern.syscall::6 29 13.74% 27.01% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.47% 27.49% # number of syscalls executed +system.cpu0.kern.syscall::17 10 4.74% 32.23% # number of syscalls executed +system.cpu0.kern.syscall::19 7 3.32% 35.55% # number of syscalls executed +system.cpu0.kern.syscall::20 4 1.90% 37.44% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.47% 37.91% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.42% 39.34% # number of syscalls executed +system.cpu0.kern.syscall::33 8 3.79% 43.13% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.95% 44.08% # number of syscalls executed +system.cpu0.kern.syscall::45 37 17.54% 61.61% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.42% 63.03% # number of syscalls executed +system.cpu0.kern.syscall::48 8 3.79% 66.82% # number of syscalls executed +system.cpu0.kern.syscall::54 9 4.27% 71.09% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.47% 71.56% # number of syscalls executed +system.cpu0.kern.syscall::59 5 2.37% 73.93% # number of syscalls executed +system.cpu0.kern.syscall::71 27 12.80% 86.73% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.42% 88.15% # number of syscalls executed +system.cpu0.kern.syscall::74 7 3.32% 91.47% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.47% 91.94% # number of syscalls executed +system.cpu0.kern.syscall::90 2 0.95% 92.89% # number of syscalls executed +system.cpu0.kern.syscall::92 7 3.32% 96.21% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.95% 97.16% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.95% 98.10% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.47% 98.58% # number of syscalls executed +system.cpu0.kern.syscall::144 1 0.47% 99.05% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.95% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 211 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 284 0.17% 0.17% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.17% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.17% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.17% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3552 2.08% 2.25% # number of callpals executed -system.cpu0.kern.callpal::tbi 51 0.03% 2.28% # number of callpals executed +system.cpu0.kern.callpal::wripir 302 0.18% 0.18% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.18% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.18% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.18% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3478 2.07% 2.26% # number of callpals executed +system.cpu0.kern.callpal::tbi 48 0.03% 2.29% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.29% # number of callpals executed -system.cpu0.kern.callpal::swpipl 154681 90.79% 93.08% # number of callpals executed -system.cpu0.kern.callpal::rdps 6653 3.90% 96.98% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.98% # number of callpals executed -system.cpu0.kern.callpal::wrusp 4 0.00% 96.98% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 96.99% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.99% # number of callpals executed -system.cpu0.kern.callpal::rti 4593 2.70% 99.69% # number of callpals executed -system.cpu0.kern.callpal::callsys 394 0.23% 99.92% # number of callpals executed -system.cpu0.kern.callpal::imb 139 0.08% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 170374 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7193 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1370 # number of protection mode switches +system.cpu0.kern.callpal::swpipl 152288 90.83% 93.12% # number of callpals executed +system.cpu0.kern.callpal::rdps 6536 3.90% 97.02% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 97.02% # number of callpals executed +system.cpu0.kern.callpal::wrusp 4 0.00% 97.02% # number of callpals executed +system.cpu0.kern.callpal::rdusp 8 0.00% 97.03% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 97.03% # number of callpals executed +system.cpu0.kern.callpal::rti 4500 2.68% 99.71% # number of callpals executed +system.cpu0.kern.callpal::callsys 345 0.21% 99.92% # number of callpals executed +system.cpu0.kern.callpal::imb 137 0.08% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 167660 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7044 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1286 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1369 -system.cpu0.kern.mode_good::user 1370 +system.cpu0.kern.mode_good::kernel 1285 +system.cpu0.kern.mode_good::user 1286 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.190324 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.182425 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.319865 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1894375479500 99.89% 99.89% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2065583000 0.11% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.308643 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1901692288000 99.89% 99.89% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2009107500 0.11% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3553 # number of times the context was actually changed +system.cpu0.kern.swap_context 3479 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2383 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 53842 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 16791 36.23% 36.23% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1921 4.14% 40.37% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 284 0.61% 40.99% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 27352 59.01% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 46348 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 16391 47.23% 47.23% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1921 5.54% 52.77% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 284 0.82% 53.59% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 16107 46.41% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 34703 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1871184919000 98.69% 98.69% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 531151500 0.03% 98.71% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 127549500 0.01% 98.72% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 24258165000 1.28% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1896101785000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.976178 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2459 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 57331 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 18009 36.73% 36.73% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1924 3.92% 40.65% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 302 0.62% 41.27% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 28797 58.73% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 49032 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 17590 47.41% 47.41% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1924 5.19% 52.59% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 302 0.81% 53.41% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 17288 46.59% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 37104 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1873168497000 98.41% 98.41% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 531845000 0.03% 98.44% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 136792000 0.01% 98.45% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 29552054000 1.55% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1903389188000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.976734 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.588878 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.748749 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed -system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed -system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed -system.cpu1.kern.syscall::17 5 5.43% 27.17% # number of syscalls executed -system.cpu1.kern.syscall::23 3 3.26% 30.43% # number of syscalls executed -system.cpu1.kern.syscall::24 3 3.26% 33.70% # number of syscalls executed -system.cpu1.kern.syscall::33 3 3.26% 36.96% # number of syscalls executed -system.cpu1.kern.syscall::45 15 16.30% 53.26% # number of syscalls executed -system.cpu1.kern.syscall::47 3 3.26% 56.52% # number of syscalls executed -system.cpu1.kern.syscall::59 1 1.09% 57.61% # number of syscalls executed -system.cpu1.kern.syscall::71 27 29.35% 86.96% # number of syscalls executed -system.cpu1.kern.syscall::74 9 9.78% 96.74% # number of syscalls executed -system.cpu1.kern.syscall::132 3 3.26% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 92 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.600340 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.756730 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::2 1 0.87% 0.87% # number of syscalls executed +system.cpu1.kern.syscall::3 13 11.30% 12.17% # number of syscalls executed +system.cpu1.kern.syscall::6 13 11.30% 23.48% # number of syscalls executed +system.cpu1.kern.syscall::15 1 0.87% 24.35% # number of syscalls executed +system.cpu1.kern.syscall::17 5 4.35% 28.70% # number of syscalls executed +system.cpu1.kern.syscall::19 3 2.61% 31.30% # number of syscalls executed +system.cpu1.kern.syscall::20 2 1.74% 33.04% # number of syscalls executed +system.cpu1.kern.syscall::23 3 2.61% 35.65% # number of syscalls executed +system.cpu1.kern.syscall::24 3 2.61% 38.26% # number of syscalls executed +system.cpu1.kern.syscall::33 3 2.61% 40.87% # number of syscalls executed +system.cpu1.kern.syscall::45 17 14.78% 55.65% # number of syscalls executed +system.cpu1.kern.syscall::47 3 2.61% 58.26% # number of syscalls executed +system.cpu1.kern.syscall::48 2 1.74% 60.00% # number of syscalls executed +system.cpu1.kern.syscall::54 1 0.87% 60.87% # number of syscalls executed +system.cpu1.kern.syscall::59 2 1.74% 62.61% # number of syscalls executed +system.cpu1.kern.syscall::71 27 23.48% 86.09% # number of syscalls executed +system.cpu1.kern.syscall::74 9 7.83% 93.91% # number of syscalls executed +system.cpu1.kern.syscall::90 1 0.87% 94.78% # number of syscalls executed +system.cpu1.kern.syscall::92 2 1.74% 96.52% # number of syscalls executed +system.cpu1.kern.syscall::132 3 2.61% 99.13% # number of syscalls executed +system.cpu1.kern.syscall::144 1 0.87% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 115 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 201 0.42% 0.42% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.43% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.43% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1067 2.24% 2.67% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.01% 2.67% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 2.69% # number of callpals executed -system.cpu1.kern.callpal::swpipl 41171 86.33% 89.01% # number of callpals executed -system.cpu1.kern.callpal::rdps 2098 4.40% 93.41% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 93.41% # number of callpals executed -system.cpu1.kern.callpal::wrusp 3 0.01% 93.42% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 93.43% # number of callpals executed -system.cpu1.kern.callpal::rti 2971 6.23% 99.66% # number of callpals executed -system.cpu1.kern.callpal::callsys 121 0.25% 99.91% # number of callpals executed -system.cpu1.kern.callpal::imb 42 0.09% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 210 0.41% 0.42% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.42% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.42% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1165 2.30% 2.72% # number of callpals executed +system.cpu1.kern.callpal::tbi 6 0.01% 2.73% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 2.75% # number of callpals executed +system.cpu1.kern.callpal::swpipl 43701 86.29% 89.04% # number of callpals executed +system.cpu1.kern.callpal::rdps 2223 4.39% 93.43% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 93.43% # number of callpals executed +system.cpu1.kern.callpal::wrusp 3 0.01% 93.44% # number of callpals executed +system.cpu1.kern.callpal::rdusp 1 0.00% 93.44% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 93.44% # number of callpals executed +system.cpu1.kern.callpal::rti 3104 6.13% 99.57% # number of callpals executed +system.cpu1.kern.callpal::callsys 172 0.34% 99.91% # number of callpals executed +system.cpu1.kern.callpal::imb 43 0.08% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 47692 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1242 # number of protection mode switches -system.cpu1.kern.mode_switch::user 368 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2406 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 576 -system.cpu1.kern.mode_good::user 368 -system.cpu1.kern.mode_good::idle 208 -system.cpu1.kern.mode_switch_good::kernel 0.463768 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 50643 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1414 # number of protection mode switches +system.cpu1.kern.mode_switch::user 459 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2447 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 685 +system.cpu1.kern.mode_good::user 459 +system.cpu1.kern.mode_good::idle 226 +system.cpu1.kern.mode_switch_good::kernel 0.484441 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.086451 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.286853 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 4070064000 0.21% 0.21% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 689483000 0.04% 0.25% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1891020032000 99.75% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1068 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.092358 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.317130 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 4654463000 0.24% 0.24% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 807268500 0.04% 0.29% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1897916233000 99.71% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1166 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 1410f747e..6711c23df 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,124 +1,124 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.854316 # Number of seconds simulated -sim_ticks 1854315535000 # Number of ticks simulated -final_tick 1854315535000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.859220 # Number of seconds simulated +sim_ticks 1859219766000 # Number of ticks simulated +final_tick 1859219766000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 136218 # Simulator instruction rate (inst/s) -host_op_rate 136218 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4770234092 # Simulator tick rate (ticks/s) -host_mem_usage 308432 # Number of bytes of host memory used -host_seconds 388.73 # Real time elapsed on the host -sim_insts 52951550 # Number of instructions simulated -sim_ops 52951550 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 963520 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24877248 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory -system.physmem.bytes_read::total 28493120 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 963520 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 963520 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7502080 # Number of bytes written to this memory -system.physmem.bytes_written::total 7502080 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15055 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388707 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 445205 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117220 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117220 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 519610 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13415866 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1430367 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15365842 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 519610 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 519610 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4045741 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4045741 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4045741 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 519610 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13415866 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1430367 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19411583 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 445205 # Total number of read requests seen -system.physmem.writeReqs 117220 # Total number of write requests seen -system.physmem.cpureqs 562608 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 28493120 # Total number of bytes read from memory -system.physmem.bytesWritten 7502080 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28493120 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7502080 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 56 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 175 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28016 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 27755 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 27572 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 27335 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 27903 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 27978 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 27988 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 27793 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 28085 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 27815 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 27957 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 27734 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 27759 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 27962 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 27777 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 27720 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7553 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7293 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7144 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 6986 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7373 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7381 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7449 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7333 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7646 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7356 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7497 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7211 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7256 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7369 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7178 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7195 # Track writes on a per bank basis +host_inst_rate 91264 # Simulator instruction rate (inst/s) +host_op_rate 91264 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3202546943 # Simulator tick rate (ticks/s) +host_mem_usage 310256 # Number of bytes of host memory used +host_seconds 580.54 # Real time elapsed on the host +sim_insts 52982774 # Number of instructions simulated +sim_ops 52982774 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 963968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24879168 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory +system.physmem.bytes_read::total 28495424 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 963968 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 963968 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7515392 # Number of bytes written to this memory +system.physmem.bytes_written::total 7515392 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15062 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388737 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory +system.physmem.num_reads::total 445241 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117428 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117428 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 518480 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13381510 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1426560 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15326550 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 518480 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 518480 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4042229 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4042229 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4042229 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 518480 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13381510 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1426560 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19368779 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 445241 # Total number of read requests seen +system.physmem.writeReqs 117428 # Total number of write requests seen +system.physmem.cpureqs 562841 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28495424 # Total number of bytes read from memory +system.physmem.bytesWritten 7515392 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28495424 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7515392 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 60 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 171 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 28229 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 27975 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 28436 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 28026 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 27802 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 27225 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 27248 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 27297 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 27658 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 27398 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 27928 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 27536 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 27551 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 28226 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 28326 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 28320 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7932 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7499 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7946 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 7517 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7344 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 6679 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 6762 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 6683 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7096 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 6802 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7320 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 6981 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7118 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7875 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 8048 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7826 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 8 # Number of times wr buffer was full causing retry -system.physmem.totGap 1854310136000 # Total gap between requests +system.physmem.numWrRetry 1 # Number of times wr buffer was full causing retry +system.physmem.totGap 1859214351000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 445205 # Categorize read packet sizes +system.physmem.readPktSize::6 445241 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 117220 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 323472 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 64407 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 19558 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 7533 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3163 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2976 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2727 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2719 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2651 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2584 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1520 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1449 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1411 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1379 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1373 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1392 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1605 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1469 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 938 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 792 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 19 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 117428 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 330939 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 63289 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 19437 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6277 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3346 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3045 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1556 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1541 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1493 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1448 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1421 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1425 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1389 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 2022 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 2332 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 2208 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1206 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 458 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 226 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 109 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see @@ -128,68 +128,248 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2939 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3695 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5067 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5083 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5086 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5088 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5097 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5097 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5097 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1402 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 971 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 893 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 356 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 9 # What write queue length does an incoming req see -system.physmem.totQLat 7478299000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 15194295250 # Sum of mem lat for all requests -system.physmem.totBusLat 2225745000 # Total cycles spent in databus access -system.physmem.totBankLat 5490251250 # Total cycles spent in bank access -system.physmem.avgQLat 16799.54 # Average queueing delay per request -system.physmem.avgBankLat 12333.51 # Average bank access latency per request +system.physmem.wrQLenPdf::0 3515 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3744 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4808 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1591 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1362 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 37468 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 960.941176 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 233.799958 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 2437.428145 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 12972 34.62% 34.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 5555 14.83% 49.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 3417 9.12% 58.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 2277 6.08% 64.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 1679 4.48% 69.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 1428 3.81% 72.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 991 2.64% 75.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 802 2.14% 77.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 632 1.69% 79.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 550 1.47% 80.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 599 1.60% 82.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 534 1.43% 83.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 276 0.74% 84.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 243 0.65% 85.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 192 0.51% 85.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 257 0.69% 86.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 103 0.27% 86.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 109 0.29% 87.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 75 0.20% 87.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 145 0.39% 87.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 226 0.60% 88.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 117 0.31% 88.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 450 1.20% 89.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 603 1.61% 91.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 73 0.19% 91.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 37 0.10% 91.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 34 0.09% 91.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 78 0.21% 91.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 30 0.08% 92.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 11 0.03% 92.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 8 0.02% 92.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 42 0.11% 92.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 24 0.06% 92.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 4 0.01% 92.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2243 2 0.01% 92.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 19 0.05% 92.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2371 6 0.02% 92.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 3 0.01% 92.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 3 0.01% 92.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2563 6 0.02% 92.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 5 0.01% 92.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 4 0.01% 92.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2755 1 0.00% 92.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 6 0.02% 92.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 5 0.01% 92.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2947 2 0.01% 92.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3011 1 0.00% 92.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 4 0.01% 92.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3203 2 0.01% 92.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3267 2 0.01% 92.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3331 3 0.01% 92.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3395 2 0.01% 92.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3523 2 0.01% 92.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3587 1 0.00% 92.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3651 1 0.00% 92.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3715 1 0.00% 92.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3843 3 0.01% 92.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3907 2 0.01% 92.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4035 2 0.01% 92.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4099 2 0.01% 92.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4227 1 0.00% 92.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4291 1 0.00% 92.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4355 1 0.00% 92.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4419 1 0.00% 92.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4483 1 0.00% 92.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4547 1 0.00% 92.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4611 1 0.00% 92.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4739 1 0.00% 92.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4803 1 0.00% 92.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4867 2 0.01% 92.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4931 2 0.01% 92.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4995 1 0.00% 92.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5059 1 0.00% 92.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5123 1 0.00% 92.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5251 1 0.00% 92.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5315 1 0.00% 92.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5507 1 0.00% 92.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5571 1 0.00% 92.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5699 1 0.00% 92.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5891 2 0.01% 92.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5955 1 0.00% 92.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6019 1 0.00% 92.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6403 2 0.01% 92.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6531 1 0.00% 92.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6595 1 0.00% 92.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6723 1 0.00% 92.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7043 1 0.00% 92.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7171 4 0.01% 92.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7235 1 0.00% 92.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7299 2 0.01% 92.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7363 2 0.01% 92.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7427 1 0.00% 92.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7811 3 0.01% 92.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7875 1 0.00% 92.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7939 1 0.00% 92.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8003 3 0.01% 92.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8067 3 0.01% 92.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8131 4 0.01% 92.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8195 2434 6.50% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8768-8771 1 0.00% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9792-9795 1 0.00% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11328-11331 1 0.00% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13696-13699 1 0.00% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13827 1 0.00% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13952-13955 1 0.00% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14016-14019 1 0.00% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14083 2 0.01% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14464-14467 1 0.00% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14656-14659 2 0.01% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14720-14723 2 0.01% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14851 1 0.00% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14915 3 0.01% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14979 1 0.00% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15171 1 0.00% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15235 1 0.00% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 16 0.04% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15808-15811 1 0.00% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16387 240 0.64% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16448-16451 5 0.01% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16512-16515 7 0.02% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16576-16579 5 0.01% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16643 5 0.01% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16704-16707 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16768-16771 2 0.01% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16832-16835 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16896-16899 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16960-16963 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17024-17027 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17088-17091 4 0.01% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17280-17283 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17536-17539 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 37468 # Bytes accessed per row activation +system.physmem.totQLat 6065400750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13430024500 # Sum of mem lat for all requests +system.physmem.totBusLat 2225905000 # Total cycles spent in databus access +system.physmem.totBankLat 5138718750 # Total cycles spent in bank access +system.physmem.avgQLat 13624.57 # Average queueing delay per request +system.physmem.avgBankLat 11542.99 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 34133.05 # Average memory access latency -system.physmem.avgRdBW 15.37 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 4.05 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 15.37 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 4.05 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 30167.56 # Average memory access latency +system.physmem.avgRdBW 15.33 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 4.04 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 15.33 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 4.04 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 7.57 # Average write queue length over time -system.physmem.readRowHits 417721 # Number of row buffer hits during reads -system.physmem.writeRowHits 91342 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.84 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 77.92 # Row buffer hit rate for writes -system.physmem.avgGap 3296990.95 # Average gap between requests +system.physmem.avgWrQLen 11.93 # Average write queue length over time +system.physmem.readRowHits 430163 # Number of row buffer hits during reads +system.physmem.writeRowHits 94965 # Number of row buffer hits during writes +system.physmem.readRowHitRate 96.63 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.87 # Row buffer hit rate for writes +system.physmem.avgGap 3304277.21 # Average gap between requests +system.membus.throughput 19411663 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 296022 # Transaction distribution +system.membus.trans_dist::ReadResp 295937 # Transaction distribution +system.membus.trans_dist::WriteReq 9598 # Transaction distribution +system.membus.trans_dist::WriteResp 9598 # Transaction distribution +system.membus.trans_dist::Writeback 117428 # Transaction distribution +system.membus.trans_dist::UpgradeReq 173 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution +system.membus.trans_dist::UpgradeResp 174 # Transaction distribution +system.membus.trans_dist::ReadExReq 156790 # Transaction distribution +system.membus.trans_dist::ReadExResp 156790 # Transaction distribution +system.membus.trans_dist::BadAddressError 85 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33056 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884132 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 170 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917358 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124679 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124679 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.bridge.slave 33056 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 1008811 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.membus.badaddr_responder.pio 170 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1042037 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44148 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30701760 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30745908 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309056 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 5309056 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.bridge.slave 44148 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 36010816 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 36054964 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 36054964 # Total data (bytes) +system.membus.snoop_data_through_bus 35584 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 29876000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 1541728249 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) +system.membus.reqLayer2.occupancy 108500 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 3763624798 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.respLayer2.occupancy 376221741 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.265062 # Cycle average of tags in use +system.iocache.tagsinuse 1.261712 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1704476481000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.265062 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.079066 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.079066 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1709369770000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 1.261712 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.078857 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.078857 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -198,14 +378,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 20927998 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 20927998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 10641558911 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10641558911 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 10662486909 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10662486909 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 10662486909 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10662486909 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21342883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21342883 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 10471007269 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10471007269 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 10492350152 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10492350152 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 10492350152 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10492350152 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -222,19 +402,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120971.086705 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 120971.086705 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 256102.207138 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 256102.207138 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 255541.927118 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 255541.927118 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 255541.927118 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 255541.927118 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 285704 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 123369.265896 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 123369.265896 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 251997.672049 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 251997.672049 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 251464.353553 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 251464.353553 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 251464.353553 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 251464.353553 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 273612 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27220 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27136 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.496106 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.082989 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -248,14 +428,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11931249 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 11931249 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8479547437 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8479547437 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 8491478686 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8491478686 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 8491478686 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8491478686 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12346133 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12346133 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8309607278 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8309607278 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 8321953411 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8321953411 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 8321953411 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8321953411 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -264,14 +444,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68966.757225 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 68966.757225 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204070.741168 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 204070.741168 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203510.573661 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 203510.573661 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203510.573661 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 203510.573661 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 71364.930636 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 71364.930636 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 199980.922170 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 199980.922170 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 199447.655147 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 199447.655147 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 199447.655147 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 199447.655147 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -285,35 +465,35 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.branchPred.lookups 13835452 # Number of BP lookups -system.cpu.branchPred.condPredicted 11604498 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 397875 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9360236 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5805061 # Number of BTB hits +system.cpu.branchPred.lookups 13839600 # Number of BP lookups +system.cpu.branchPred.condPredicted 11609173 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 399191 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9510547 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5805743 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 62.018319 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 907052 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 38979 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 61.045311 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 906368 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 39168 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9913942 # DTB read hits -system.cpu.dtb.read_misses 41971 # DTB read misses -system.cpu.dtb.read_acv 559 # DTB read access violations -system.cpu.dtb.read_accesses 941163 # DTB read accesses -system.cpu.dtb.write_hits 6591840 # DTB write hits -system.cpu.dtb.write_misses 10659 # DTB write misses +system.cpu.dtb.read_hits 9923550 # DTB read hits +system.cpu.dtb.read_misses 41274 # DTB read misses +system.cpu.dtb.read_acv 543 # DTB read access violations +system.cpu.dtb.read_accesses 941562 # DTB read accesses +system.cpu.dtb.write_hits 6598688 # DTB write hits +system.cpu.dtb.write_misses 10641 # DTB write misses system.cpu.dtb.write_acv 411 # DTB write access violations -system.cpu.dtb.write_accesses 337869 # DTB write accesses -system.cpu.dtb.data_hits 16505782 # DTB hits -system.cpu.dtb.data_misses 52630 # DTB misses -system.cpu.dtb.data_acv 970 # DTB access violations -system.cpu.dtb.data_accesses 1279032 # DTB accesses -system.cpu.itb.fetch_hits 1304387 # ITB hits -system.cpu.itb.fetch_misses 38101 # ITB misses -system.cpu.itb.fetch_acv 1094 # ITB acv -system.cpu.itb.fetch_accesses 1342488 # ITB accesses +system.cpu.dtb.write_accesses 338433 # DTB write accesses +system.cpu.dtb.data_hits 16522238 # DTB hits +system.cpu.dtb.data_misses 51915 # DTB misses +system.cpu.dtb.data_acv 954 # DTB access violations +system.cpu.dtb.data_accesses 1279995 # DTB accesses +system.cpu.itb.fetch_hits 1308614 # ITB hits +system.cpu.itb.fetch_misses 36742 # ITB misses +system.cpu.itb.fetch_acv 1058 # ITB acv +system.cpu.itb.fetch_accesses 1345356 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -326,269 +506,269 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 108709176 # number of cpu cycles simulated +system.cpu.numCycles 120145786 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 28075681 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 70625770 # Number of instructions fetch has processed -system.cpu.fetch.Branches 13835452 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 6712113 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 13231336 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1982002 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 37359508 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 32821 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 254255 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 361301 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 440 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8540739 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 263307 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 80598838 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.876263 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.220111 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 28059248 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 70722559 # Number of instructions fetch has processed +system.cpu.fetch.Branches 13839600 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6712111 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 13258692 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1994060 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 38168658 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 32286 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 254324 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 364483 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 291 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8570347 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 266679 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 81425482 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.868556 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.211321 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 67367502 83.58% 83.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 852306 1.06% 84.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1694888 2.10% 86.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 821828 1.02% 87.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2746821 3.41% 91.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 564765 0.70% 91.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 643702 0.80% 92.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1011325 1.25% 93.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4895701 6.07% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 68166790 83.72% 83.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 854823 1.05% 84.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1706158 2.10% 86.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 819634 1.01% 87.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2757548 3.39% 91.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 561946 0.69% 91.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 649151 0.80% 92.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1013766 1.25% 93.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4895666 6.01% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 80598838 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.127270 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.649676 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 29246161 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 37051175 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 12098296 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 961855 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1241350 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 583461 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 42570 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 69332672 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 129212 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1241350 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 30366961 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 13601503 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 19800886 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 11334089 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4254047 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 65583694 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 7011 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 505967 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1480663 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 43793573 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 79610392 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 79131107 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 479285 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38157493 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5636072 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1682036 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 239674 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12118674 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10434139 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6898397 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1310169 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 877649 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 58153519 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2049469 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 56771792 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 109314 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6892902 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3544978 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1388546 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 80598838 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.704375 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.365163 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 81425482 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.115190 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.588640 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 29284437 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 37811275 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 12102091 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 982484 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1245194 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 583690 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 42726 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 69419384 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 129751 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1245194 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 30419678 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 14066203 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 19996824 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 11337239 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4360342 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 65632842 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 7067 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 503743 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1590486 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 43821413 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 79676034 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 79196502 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 479532 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38182467 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 5638938 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1682867 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 239802 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12252220 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10440672 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6902467 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1316833 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 861587 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 58171642 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2051698 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 56802904 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 100593 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6885118 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3554028 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1390714 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 81425482 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.697606 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.359574 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 55952160 69.42% 69.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10819456 13.42% 82.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5161521 6.40% 89.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3379007 4.19% 93.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2642777 3.28% 96.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1459621 1.81% 98.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 760708 0.94% 99.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 329892 0.41% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 93696 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 56719527 69.66% 69.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10865996 13.34% 83.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5212450 6.40% 89.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3349939 4.11% 93.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2634366 3.24% 96.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1460723 1.79% 98.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 752656 0.92% 99.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 333424 0.41% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 96401 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 80598838 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 81425482 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 91294 11.60% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 373063 47.40% 59.00% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 322658 41.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 93250 11.76% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 372953 47.03% 58.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 326761 41.21% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 38708062 68.18% 68.19% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 61690 0.11% 68.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10346391 18.22% 86.58% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6670119 11.75% 98.33% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 949001 1.67% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 38720727 68.17% 68.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 61725 0.11% 68.29% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10357561 18.23% 86.57% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6677285 11.76% 98.33% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 949077 1.67% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 56771792 # Type of FU issued -system.cpu.iq.rate 0.522236 # Inst issue rate -system.cpu.iq.fu_busy_cnt 787015 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013863 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 194345553 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 66772978 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 55538078 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 693197 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 336730 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 327888 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 57189578 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 361943 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 597316 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 56802904 # Type of FU issued +system.cpu.iq.rate 0.472783 # Inst issue rate +system.cpu.iq.fu_busy_cnt 792964 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013960 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 195231977 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 66785301 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 55558093 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 692869 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 336906 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 327947 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 57227049 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 361533 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 597916 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1346178 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3275 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14144 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 522891 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1347952 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3269 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14100 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 524235 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 17954 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 174426 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 17914 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 199705 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1241350 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 9930800 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 684897 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 63726259 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 676325 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10434139 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6898397 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1805166 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 512910 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 18627 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14144 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 201347 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 411340 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 612687 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 56305820 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 9984116 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 465971 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1245194 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 10207267 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 699182 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 63757422 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 685568 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10440672 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6902467 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1806514 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 512114 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 18348 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14100 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 200766 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 410779 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 611545 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 56334870 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 9992999 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 468033 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3523271 # number of nop insts executed -system.cpu.iew.exec_refs 16601850 # number of memory reference insts executed -system.cpu.iew.exec_branches 8919814 # Number of branches executed -system.cpu.iew.exec_stores 6617734 # Number of stores executed -system.cpu.iew.exec_rate 0.517949 # Inst execution rate -system.cpu.iew.wb_sent 55981553 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 55865966 # cumulative count of insts written-back -system.cpu.iew.wb_producers 27748179 # num instructions producing a value -system.cpu.iew.wb_consumers 37603022 # num instructions consuming a value +system.cpu.iew.exec_nop 3534082 # number of nop insts executed +system.cpu.iew.exec_refs 16617553 # number of memory reference insts executed +system.cpu.iew.exec_branches 8923539 # Number of branches executed +system.cpu.iew.exec_stores 6624554 # Number of stores executed +system.cpu.iew.exec_rate 0.468888 # Inst execution rate +system.cpu.iew.wb_sent 55999832 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 55886040 # cumulative count of insts written-back +system.cpu.iew.wb_producers 27701007 # num instructions producing a value +system.cpu.iew.wb_consumers 37529982 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.513903 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.737924 # average fanout of values written-back +system.cpu.iew.wb_rate 0.465152 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.738103 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 7467988 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 660923 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 566730 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 79357488 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.707446 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.635929 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 7465540 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 660984 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 567902 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 80180288 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.700591 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.629829 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 58581738 73.82% 73.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8607533 10.85% 84.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4610804 5.81% 90.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2534837 3.19% 93.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1515398 1.91% 95.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 609514 0.77% 96.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 522093 0.66% 97.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 538800 0.68% 97.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1836771 2.31% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 59372363 74.05% 74.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8630775 10.76% 84.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4656269 5.81% 90.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2498281 3.12% 93.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1510890 1.88% 95.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 609736 0.76% 96.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 522635 0.65% 97.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 527296 0.66% 97.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1852043 2.31% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 79357488 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56141140 # Number of instructions committed -system.cpu.commit.committedOps 56141140 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 80180288 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56173622 # Number of instructions committed +system.cpu.commit.committedOps 56173622 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15463467 # Number of memory references committed -system.cpu.commit.loads 9087961 # Number of loads committed -system.cpu.commit.membars 226334 # Number of memory barriers committed -system.cpu.commit.branches 8436593 # Number of branches committed +system.cpu.commit.refs 15470952 # Number of memory references committed +system.cpu.commit.loads 9092720 # Number of loads committed +system.cpu.commit.membars 226359 # Number of memory barriers committed +system.cpu.commit.branches 8440448 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 51992006 # Number of committed integer instructions. -system.cpu.commit.function_calls 740231 # Number of function calls committed. -system.cpu.commit.bw_lim_events 1836771 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 52023156 # Number of committed integer instructions. +system.cpu.commit.function_calls 740622 # Number of function calls committed. +system.cpu.commit.bw_lim_events 1852043 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 140880188 # The number of ROB reads -system.cpu.rob.rob_writes 128461324 # The number of ROB writes -system.cpu.timesIdled 1178621 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 28110338 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3599915455 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 52951550 # Number of Instructions Simulated -system.cpu.committedOps 52951550 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 52951550 # Number of Instructions Simulated -system.cpu.cpi 2.052993 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.052993 # CPI: Total CPI of All Threads -system.cpu.ipc 0.487094 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.487094 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 73826909 # number of integer regfile reads -system.cpu.int_regfile_writes 40289801 # number of integer regfile writes -system.cpu.fp_regfile_reads 166028 # number of floating regfile reads -system.cpu.fp_regfile_writes 167439 # number of floating regfile writes -system.cpu.misc_regfile_reads 1985478 # number of misc regfile reads -system.cpu.misc_regfile_writes 938924 # number of misc regfile writes +system.cpu.rob.rob_reads 141717845 # The number of ROB reads +system.cpu.rob.rob_writes 128525319 # The number of ROB writes +system.cpu.timesIdled 1192872 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 38720304 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3598287306 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 52982774 # Number of Instructions Simulated +system.cpu.committedOps 52982774 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 52982774 # Number of Instructions Simulated +system.cpu.cpi 2.267639 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.267639 # CPI: Total CPI of All Threads +system.cpu.ipc 0.440987 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.440987 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 73877727 # number of integer regfile reads +system.cpu.int_regfile_writes 40299404 # number of integer regfile writes +system.cpu.fp_regfile_reads 166073 # number of floating regfile reads +system.cpu.fp_regfile_writes 167447 # number of floating regfile writes +system.cpu.misc_regfile_reads 1985193 # number of misc regfile reads +system.cpu.misc_regfile_writes 938984 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -620,193 +800,319 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu.icache.replacements 1007426 # number of replacements -system.cpu.icache.tagsinuse 510.288426 # Cycle average of tags in use -system.cpu.icache.total_refs 7476565 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1007934 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.417713 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 20275724000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.288426 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996657 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996657 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 7476566 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7476566 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7476566 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7476566 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7476566 # number of overall hits -system.cpu.icache.overall_hits::total 7476566 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1064170 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1064170 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1064170 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1064170 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1064170 # number of overall misses -system.cpu.icache.overall_misses::total 1064170 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14673680991 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14673680991 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14673680991 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14673680991 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14673680991 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14673680991 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8540736 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8540736 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8540736 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8540736 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8540736 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8540736 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124599 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.124599 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.124599 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.124599 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.124599 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.124599 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13788.850457 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13788.850457 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13788.850457 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13788.850457 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13788.850457 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13788.850457 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 6348 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 862 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 199 # number of cycles access was blocked +system.iobus.throughput 1455318 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 7103 # Transaction distribution +system.iobus.trans_dist::ReadResp 7103 # Transaction distribution +system.iobus.trans_dist::WriteReq 51150 # Transaction distribution +system.iobus.trans_dist::WriteResp 51150 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5052 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 33056 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.cchip.pio 5052 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 116506 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20208 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 44148 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.cchip.pio 20208 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 2705756 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 2705756 # Total data (bytes) +system.iobus.reqLayer0.occupancy 4663000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) +system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 13484000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer24.occupancy 1887000 # Layer occupancy (ticks) +system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) +system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) +system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer29.occupancy 378262152 # Layer occupancy (ticks) +system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 23458000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer1.occupancy 42010000 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.throughput 112025274 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2118762 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2118660 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 9598 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 9598 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 840976 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 64 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 4 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 68 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 342524 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 300973 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 85 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 2020715 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3678751 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 5699466 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 64659008 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 143612852 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 208271860 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 208261812 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 17792 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 2480878498 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1516366019 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 2115023448 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.cpu.icache.replacements 1009685 # number of replacements +system.cpu.icache.tagsinuse 509.751691 # Cycle average of tags in use +system.cpu.icache.total_refs 7503411 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1010193 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.427700 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 25536785000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 509.751691 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.995609 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.995609 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 7503412 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7503412 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7503412 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7503412 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7503412 # number of overall hits +system.cpu.icache.overall_hits::total 7503412 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1066934 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1066934 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1066934 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1066934 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1066934 # number of overall misses +system.cpu.icache.overall_misses::total 1066934 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15003433992 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15003433992 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15003433992 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15003433992 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15003433992 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15003433992 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 8570346 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8570346 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 8570346 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 8570346 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 8570346 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 8570346 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124491 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.124491 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.124491 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.124491 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.124491 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.124491 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14062.195030 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14062.195030 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14062.195030 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14062.195030 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14062.195030 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14062.195030 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 6693 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 179 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 211 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 31.899497 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 862 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 31.720379 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 179 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 56016 # 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number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12024926992 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12024926992 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12024926992 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12024926992 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12024926992 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.118041 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.118041 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.118041 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.118041 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.118041 # 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number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12286930976 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12286930976 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12286930976 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.117897 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.117897 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.117897 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.117897 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.117897 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.117897 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12160.245538 # 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number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1882603500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3216560000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3216560000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014909 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248679 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136829 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.546875 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.546875 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.250000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383345 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383345 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014909 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277584 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.167583 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014909 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277584 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.167583 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 73762.929496 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 50409.455221 # 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average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56860.023379 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38119.936673 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38817.887341 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68710.931156 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68710.931156 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73762.929496 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55834.371691 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56502.344004 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73762.929496 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55834.371691 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56502.344004 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -896,161 +1202,161 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1400143 # number of replacements -system.cpu.dcache.tagsinuse 511.995158 # Cycle average of tags in use -system.cpu.dcache.total_refs 11810847 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1400655 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 8.432374 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 21808000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.995158 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999991 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999991 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 7205070 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7205070 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4204085 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4204085 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 185954 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 185954 # 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miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.108895 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000023 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000023 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.246981 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.246981 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.246981 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.246981 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18816.932059 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 18816.932059 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33465.791477 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33465.791477 # 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number of cycles access was blocked +system.cpu.dcache.replacements 1401615 # number of replacements +system.cpu.dcache.tagsinuse 511.994565 # Cycle average of tags in use +system.cpu.dcache.total_refs 11806786 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1402127 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 8.420625 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 25214000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.994565 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999989 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 7200855 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7200855 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4204221 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4204221 # 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number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22748 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 4 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 4 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3747844 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3747844 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3747844 # number of overall misses +system.cpu.dcache.overall_misses::total 3747844 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 39515383000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 39515383000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 75738860769 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 75738860769 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 321949000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 321949000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 65000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 65000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 115254243769 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 115254243769 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 115254243769 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 115254243769 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9004912 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9004912 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6148008 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6148008 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 208694 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 208694 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 215521 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 215521 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15152920 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15152920 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15152920 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15152920 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.200341 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.200341 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316165 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.316165 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.109002 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.109002 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000019 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000019 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.247335 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.247335 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.247335 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.247335 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21903.622225 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 21903.622225 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38964.588594 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38964.588594 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14152.848602 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14152.848602 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16250 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16250 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30752.145439 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30752.145439 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30752.145439 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30752.145439 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 2955693 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 733 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 101444 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.724285 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 154.428571 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 29.136203 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 104.714286 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 840025 # number of writebacks -system.cpu.dcache.writebacks::total 840025 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 717752 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 717752 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1640976 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1640976 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5261 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 5261 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2358728 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2358728 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2358728 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2358728 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1083104 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1083104 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300236 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 300236 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17463 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17463 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1383340 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1383340 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1383340 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1383340 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21322279500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 21322279500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9864847262 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9864847262 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 200761000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 200761000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 66500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 66500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31187126762 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 31187126762 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31187126762 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 31187126762 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423835500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423835500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997377498 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997377498 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421212998 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421212998 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120266 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120266 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048856 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048856 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083684 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083684 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000023 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091302 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091302 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091302 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091302 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19686.271586 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19686.271586 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32856.976718 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32856.976718 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11496.363740 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11496.363740 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13300 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13300 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22544.802263 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22544.802263 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22544.802263 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22544.802263 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 840976 # number of writebacks +system.cpu.dcache.writebacks::total 840976 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 719736 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 719736 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1643409 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1643409 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5171 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 5171 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2363145 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2363145 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2363145 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2363145 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1084321 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1084321 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300378 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 300378 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17577 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17577 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 4 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 4 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1384699 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1384699 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1384699 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1384699 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26518641540 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 26518641540 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11550001786 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11550001786 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 202636005 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 202636005 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 57000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 57000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 38068643326 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 38068643326 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 38068643326 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 38068643326 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424047000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424047000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997793498 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997793498 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421840498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421840498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120414 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120414 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048858 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048858 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.084224 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.084224 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000019 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091382 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091382 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091382 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091382 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24456.449280 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24456.449280 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38451.556992 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38451.556992 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11528.474996 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11528.474996 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14250 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14250 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27492.359947 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 27492.359947 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27492.359947 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 27492.359947 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1059,28 +1365,28 @@ system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6440 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211001 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74662 40.97% 40.97% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6441 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211017 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74665 40.97% 40.97% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1879 1.03% 42.07% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105560 57.93% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182232 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73295 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::22 1880 1.03% 42.07% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105572 57.93% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182248 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73298 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1879 1.26% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73295 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148600 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1818327594000 98.06% 98.06% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 63775000 0.00% 98.06% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 558444000 0.03% 98.09% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 35364889500 1.91% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1854314702500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::22 1880 1.27% 50.68% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73298 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148607 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1817988566000 97.78% 97.78% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 64092000 0.00% 97.79% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 554660500 0.03% 97.82% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 40611610500 2.18% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1859218929000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981692 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694344 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815444 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694294 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815411 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -1119,29 +1425,29 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175117 91.23% 93.43% # number of callpals executed +system.cpu.kern.callpal::swpipl 175131 91.23% 93.43% # number of callpals executed system.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed -system.cpu.kern.callpal::rti 5104 2.66% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5105 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 191961 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5849 # number of protection mode switches -system.cpu.kern.mode_switch::user 1739 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1909 -system.cpu.kern.mode_good::user 1739 +system.cpu.kern.callpal::total 191976 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5853 # number of protection mode switches +system.cpu.kern.mode_switch::user 1740 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2094 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1910 +system.cpu.kern.mode_good::user 1740 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.326381 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.326328 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.394218 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29464996000 1.59% 1.59% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2711269000 0.15% 1.74% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1822138429500 98.26% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::idle 0.081184 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.394343 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 29661883000 1.60% 1.60% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2771562000 0.15% 1.74% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1826785476000 98.26% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt index 3510035fa..936d08062 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt @@ -1,142 +1,142 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.841721 # Number of seconds simulated -sim_ticks 1841721066000 # Number of ticks simulated -final_tick 1841721066000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.842698 # Number of seconds simulated +sim_ticks 1842697801000 # Number of ticks simulated +final_tick 1842697801000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 314597 # Simulator instruction rate (inst/s) -host_op_rate 314597 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8282501609 # Simulator tick rate (ticks/s) -host_mem_usage 307380 # Number of bytes of host memory used -host_seconds 222.36 # Real time elapsed on the host -sim_insts 69954713 # Number of instructions simulated -sim_ops 69954713 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 472704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 19360768 # Number of bytes read from this memory +host_inst_rate 215096 # Simulator instruction rate (inst/s) +host_op_rate 215096 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5452418287 # Simulator tick rate (ticks/s) +host_mem_usage 309280 # Number of bytes of host memory used +host_seconds 337.96 # Real time elapsed on the host +sim_insts 72693799 # Number of instructions simulated +sim_ops 72693799 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 487424 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 20019264 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 152256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2811776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 294016 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2696640 # Number of bytes read from this memory -system.physmem.bytes_read::total 28440512 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 472704 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 152256 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 294016 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 918976 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7466048 # Number of bytes written to this memory -system.physmem.bytes_written::total 7466048 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 7386 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 302512 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu1.inst 147904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2316480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 282624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2529216 # Number of bytes read from this memory +system.physmem.bytes_read::total 28435264 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 487424 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 147904 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 282624 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 917952 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7459584 # Number of bytes written to this memory +system.physmem.bytes_written::total 7459584 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 7616 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 312801 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2379 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 43934 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 4594 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 42135 # Number of read requests responded to by this memory -system.physmem.num_reads::total 444383 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 116657 # Number of write requests responded to by this memory -system.physmem.num_writes::total 116657 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 256664 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 10512324 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1440149 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 82670 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1526711 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 159642 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 1464196 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15442356 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 256664 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 82670 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 159642 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 498977 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4053843 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4053843 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4053843 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 256664 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 10512324 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1440149 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 82670 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1526711 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 159642 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1464196 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19496199 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 109805 # Total number of read requests seen -system.physmem.writeReqs 45348 # Total number of write requests seen -system.physmem.cpureqs 155202 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 7027520 # Total number of bytes read from memory -system.physmem.bytesWritten 2902272 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 7027520 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 2902272 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 5 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 42 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 6903 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 6718 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 6604 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 6507 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 6918 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 6911 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 6891 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 6873 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 7028 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 6837 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 7200 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 6974 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 6884 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 6958 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 6841 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 6753 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 2939 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 2758 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 2643 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 2556 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 2819 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 2749 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 2776 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 2848 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 3031 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 2909 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 3192 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 2889 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 2835 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 2902 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 2803 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 2699 # Track writes on a per bank basis +system.physmem.num_reads::cpu1.inst 2311 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 36195 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 4416 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 39519 # Number of read requests responded to by this memory +system.physmem.num_reads::total 444301 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 116556 # Number of write requests responded to by this memory +system.physmem.num_writes::total 116556 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 264517 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 10864106 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1439385 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 80265 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1257113 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 153375 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 1372561 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15431322 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 264517 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 80265 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 153375 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 498157 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4048186 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4048186 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4048186 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 264517 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 10864106 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1439385 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 80265 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1257113 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 153375 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1372561 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19479509 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 99716 # Total number of read requests seen +system.physmem.writeReqs 44920 # Total number of write requests seen +system.physmem.cpureqs 144680 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 6381824 # Total number of bytes read from memory +system.physmem.bytesWritten 2874880 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 6381824 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 2874880 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 11 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 44 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 6258 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 6027 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 6219 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 6346 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 5767 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 6396 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 6153 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 6072 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 6492 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 6415 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 6657 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 6000 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 6017 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 6370 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 6370 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 6146 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 2882 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 2656 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 2846 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 2961 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 2624 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 3004 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 2942 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 2707 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 3214 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 2827 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 3022 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 2441 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 2472 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 2709 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 2853 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 2760 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 7 # Number of times wr buffer was full causing retry -system.physmem.totGap 1840708761500 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 1841685476500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 109805 # Categorize read packet sizes +system.physmem.readPktSize::6 99716 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 45348 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 80824 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 9409 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5385 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1978 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1285 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1199 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1092 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1088 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1066 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1043 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 617 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 590 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 574 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 554 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 550 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 573 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 668 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 614 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 376 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 310 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 5 # What read queue length does an incoming req see +system.physmem.writePktSize::6 44920 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 68031 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 12674 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 6197 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2237 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1385 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1270 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 664 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 645 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 634 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 616 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 594 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 598 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 585 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 841 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 979 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 938 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 504 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 188 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 82 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 42 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -148,242 +148,369 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1413 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1617 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1638 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1972 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1971 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1969 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1965 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1972 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1970 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1968 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1965 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1964 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1960 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1959 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1954 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 1953 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 1953 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 1951 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 1950 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 781 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 589 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 373 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8 # What write queue length does an incoming req see -system.physmem.totQLat 2404806500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 4407346500 # Sum of mem lat for all requests -system.physmem.totBusLat 549000000 # Total cycles spent in databus access -system.physmem.totBankLat 1453540000 # Total cycles spent in bank access -system.physmem.avgQLat 21901.70 # Average queueing delay per request -system.physmem.avgBankLat 13238.07 # Average bank access latency per request +system.physmem.wrQLenPdf::0 1388 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1426 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1839 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1967 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1966 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1963 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1963 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1958 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1954 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1953 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1952 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1949 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1948 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1946 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1945 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1944 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1941 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1939 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1939 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 1938 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 1934 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 1932 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 1929 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 621 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 554 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 15781 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 586.280717 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 172.240853 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1929.214074 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 6626 41.99% 41.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 2550 16.16% 58.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 1431 9.07% 67.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 896 5.68% 72.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 638 4.04% 76.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 562 3.56% 80.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 391 2.48% 82.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 301 1.91% 84.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 260 1.65% 86.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 205 1.30% 87.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 214 1.36% 89.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 213 1.35% 90.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 77 0.49% 91.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 70 0.44% 91.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 80 0.51% 91.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 90 0.57% 92.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 36 0.23% 92.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 39 0.25% 93.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 32 0.20% 93.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 57 0.36% 93.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 48 0.30% 93.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 35 0.22% 94.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 177 1.12% 95.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 87 0.55% 95.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 34 0.22% 96.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 14 0.09% 96.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 7 0.04% 96.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 18 0.11% 96.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 14 0.09% 96.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 8 0.05% 96.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 2 0.01% 96.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 6 0.04% 96.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 6 0.04% 96.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 4 0.03% 96.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2371 1 0.01% 96.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 2 0.01% 96.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 1 0.01% 96.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 2 0.01% 96.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 1 0.01% 96.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 1 0.01% 96.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 3 0.02% 96.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3011 1 0.01% 96.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 2 0.01% 96.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3139 2 0.01% 96.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3267 1 0.01% 96.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3395 1 0.01% 96.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3459 1 0.01% 96.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3587 1 0.01% 96.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3651 1 0.01% 96.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3779 1 0.01% 96.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3843 1 0.01% 96.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3907 1 0.01% 96.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4227 1 0.01% 96.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4675 1 0.01% 96.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4931 1 0.01% 96.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5059 2 0.01% 96.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5123 1 0.01% 96.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5315 1 0.01% 96.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5699 1 0.01% 96.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6595 1 0.01% 96.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6723 1 0.01% 96.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7811 1 0.01% 96.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8003 1 0.01% 96.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8195 384 2.43% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11523 1 0.01% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14464-14467 1 0.01% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15296-15299 1 0.01% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 8 0.05% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15488-15491 1 0.01% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15552-15555 1 0.01% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16192-16195 1 0.01% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16387 111 0.70% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16448-16451 1 0.01% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16512-16515 1 0.01% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16643 3 0.02% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16704-16707 1 0.01% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16832-16835 1 0.01% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17088-17091 1 0.01% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 15781 # Bytes accessed per row activation +system.physmem.totQLat 1934459750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 3605914750 # Sum of mem lat for all requests +system.physmem.totBusLat 498525000 # Total cycles spent in databus access +system.physmem.totBankLat 1172930000 # Total cycles spent in bank access +system.physmem.avgQLat 19401.83 # Average queueing delay per request +system.physmem.avgBankLat 11764.00 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 40139.77 # Average memory access latency -system.physmem.avgRdBW 3.82 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 1.58 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 3.82 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 1.58 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 36165.84 # Average memory access latency +system.physmem.avgRdBW 3.46 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 3.46 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 1.56 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.17 # Average write queue length over time -system.physmem.readRowHits 99784 # Number of row buffer hits during reads -system.physmem.writeRowHits 34161 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.88 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.33 # Row buffer hit rate for writes -system.physmem.avgGap 11863829.65 # Average gap between requests -system.l2c.replacements 337457 # number of replacements -system.l2c.tagsinuse 65420.293999 # Cycle average of tags in use -system.l2c.total_refs 2475568 # Total number of references to valid blocks. -system.l2c.sampled_refs 402619 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.148662 # Average number of references to valid blocks. +system.physmem.readRowHits 93388 # Number of row buffer hits during reads +system.physmem.writeRowHits 35434 # Number of row buffer hits during writes +system.physmem.readRowHitRate 93.66 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.88 # Row buffer hit rate for writes +system.physmem.avgGap 12733243.98 # Average gap between requests +system.membus.throughput 19523449 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 46002 # Transaction distribution +system.membus.trans_dist::ReadResp 45972 # Transaction distribution +system.membus.trans_dist::WriteReq 3749 # Transaction distribution +system.membus.trans_dist::WriteResp 3749 # Transaction distribution +system.membus.trans_dist::Writeback 44920 # Transaction distribution +system.membus.trans_dist::UpgradeReq 46 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution +system.membus.trans_dist::UpgradeResp 47 # Transaction distribution +system.membus.trans_dist::ReadExReq 56809 # Transaction distribution +system.membus.trans_dist::ReadExResp 56809 # Transaction distribution +system.membus.trans_dist::BadAddressError 30 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 13314 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 192737 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 60 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 206111 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 51863 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 51863 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.bridge.slave 13314 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 244600 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.membus.badaddr_responder.pio 60 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 257974 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 15747 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 7047808 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 7063555 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2208896 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 2208896 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.bridge.slave 15747 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 9256704 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 9272451 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 35965768 # Total data (bytes) +system.membus.snoop_data_through_bus 10048 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 12475000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 520545500 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 35000 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 777595953 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 156419750 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.l2c.replacements 337378 # number of replacements +system.l2c.tagsinuse 65422.722236 # Cycle average of tags in use +system.l2c.total_refs 2472063 # Total number of references to valid blocks. +system.l2c.sampled_refs 402541 # Sample count of references to valid blocks. +system.l2c.avg_refs 6.141146 # Average number of references to valid blocks. system.l2c.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 54855.924450 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 2280.990805 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 2631.435167 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 619.089376 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 660.267485 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.inst 2247.126162 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.data 2125.460555 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.837035 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.034805 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.040153 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.009447 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.010075 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.inst 0.034288 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.data 0.032432 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.998234 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 516823 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 491434 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 126840 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 83916 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 295941 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 241655 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1756609 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 836144 # number of Writeback hits -system.l2c.Writeback_hits::total 836144 # number of Writeback hits +system.l2c.occ_blocks::writebacks 54907.432737 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 2460.754948 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 2679.156770 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 579.419963 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 590.394247 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.inst 2099.377178 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.data 2106.186392 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.837821 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.037548 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.040881 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.008841 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.009009 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.inst 0.032034 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.data 0.032138 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.998272 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 520270 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 493307 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 124051 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 83977 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 292923 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 239241 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1753769 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 835411 # number of Writeback hits +system.l2c.Writeback_hits::total 835411 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 1 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu2.data 4 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 8 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu2.data 1 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 92196 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 27303 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 67454 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 186953 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 516823 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 583630 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 126840 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 111219 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 295941 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 309109 # number of demand (read+write) hits -system.l2c.demand_hits::total 1943562 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 516823 # 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average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 62303.576116 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 58932.120503 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -494,14 +629,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.255737 # Cycle average of tags in use +system.iocache.tagsinuse 1.254871 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1693878100000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.255737 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.078484 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.078484 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1694871315000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 1.254871 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.078429 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.078429 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -510,14 +645,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 9177998 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 9177998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 4330975325 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 4330975325 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 4340153323 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4340153323 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 4340153323 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4340153323 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 9512963 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 9512963 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 4344125507 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 4344125507 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 4353638470 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4353638470 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 4353638470 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4353638470 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -534,19 +669,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 53052.011561 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 53052.011561 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 104230.249446 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 104230.249446 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 104018.054476 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 104018.054476 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 104018.054476 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 104018.054476 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 117509 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 54988.225434 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 54988.225434 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 104546.724755 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 104546.724755 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 104341.245536 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 104341.245536 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 104341.245536 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 104341.245536 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 113861 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 11192 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 11412 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.499375 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.977305 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -554,36 +689,36 @@ system.iocache.writebacks::writebacks 41512 # nu system.iocache.writebacks::total 41512 # number of writebacks system.iocache.ReadReq_mshr_misses::tsunami.ide 69 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 69 # number of ReadReq MSHR misses -system.iocache.WriteReq_mshr_misses::tsunami.ide 16768 # number of WriteReq MSHR misses -system.iocache.WriteReq_mshr_misses::total 16768 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 16837 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 16837 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 16837 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 16837 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5589249 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 5589249 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3458522887 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 3458522887 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 3464112136 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 3464112136 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 3464112136 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 3464112136 # number of overall MSHR miss cycles +system.iocache.WriteReq_mshr_misses::tsunami.ide 17280 # number of WriteReq MSHR misses +system.iocache.WriteReq_mshr_misses::total 17280 # number of WriteReq MSHR misses +system.iocache.demand_mshr_misses::tsunami.ide 17349 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 17349 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 17349 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 17349 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5924213 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 5924213 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3445287507 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 3445287507 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 3451211720 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 3451211720 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 3451211720 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 3451211720 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.398844 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 0.398844 # mshr miss rate for ReadReq accesses -system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 0.403543 # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::total 0.403543 # mshr miss rate for WriteReq accesses -system.iocache.demand_mshr_miss_rate::tsunami.ide 0.403523 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.403523 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::tsunami.ide 0.403523 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.403523 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 81003.608696 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 81003.608696 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 206257.328662 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 206257.328662 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 205744.024232 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 205744.024232 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 205744.024232 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 205744.024232 # average overall mshr miss latency +system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 0.415864 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total 0.415864 # mshr miss rate for WriteReq accesses +system.iocache.demand_mshr_miss_rate::tsunami.ide 0.415794 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.415794 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::tsunami.ide 0.415794 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.415794 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 85858.159420 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 85858.159420 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 199380.064062 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 199380.064062 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 198928.567641 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 198928.567641 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 198928.567641 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 198928.567641 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -601,22 +736,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 4882934 # DTB read hits -system.cpu0.dtb.read_misses 6016 # DTB read misses -system.cpu0.dtb.read_acv 120 # DTB read access violations -system.cpu0.dtb.read_accesses 427387 # DTB read accesses -system.cpu0.dtb.write_hits 3510109 # DTB write hits -system.cpu0.dtb.write_misses 663 # DTB write misses -system.cpu0.dtb.write_acv 82 # DTB write access violations -system.cpu0.dtb.write_accesses 162920 # DTB write accesses -system.cpu0.dtb.data_hits 8393043 # DTB hits -system.cpu0.dtb.data_misses 6679 # DTB misses -system.cpu0.dtb.data_acv 202 # DTB access violations -system.cpu0.dtb.data_accesses 590307 # DTB accesses -system.cpu0.itb.fetch_hits 2747668 # ITB hits -system.cpu0.itb.fetch_misses 3002 # ITB misses -system.cpu0.itb.fetch_acv 100 # ITB acv -system.cpu0.itb.fetch_accesses 2750670 # ITB accesses +system.cpu0.dtb.read_hits 4916475 # DTB read hits +system.cpu0.dtb.read_misses 6063 # DTB read misses +system.cpu0.dtb.read_acv 126 # DTB read access violations +system.cpu0.dtb.read_accesses 427415 # DTB read accesses +system.cpu0.dtb.write_hits 3510632 # DTB write hits +system.cpu0.dtb.write_misses 668 # DTB write misses +system.cpu0.dtb.write_acv 84 # DTB write access violations +system.cpu0.dtb.write_accesses 162993 # DTB write accesses +system.cpu0.dtb.data_hits 8427107 # DTB hits +system.cpu0.dtb.data_misses 6731 # DTB misses +system.cpu0.dtb.data_acv 210 # DTB access violations +system.cpu0.dtb.data_accesses 590408 # DTB accesses +system.cpu0.itb.fetch_hits 2754785 # ITB hits +system.cpu0.itb.fetch_misses 3015 # ITB misses +system.cpu0.itb.fetch_acv 104 # ITB acv +system.cpu0.itb.fetch_accesses 2757800 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -629,51 +764,51 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 928534019 # number of cpu cycles simulated +system.cpu0.numCycles 928378822 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 33030135 # Number of instructions committed -system.cpu0.committedOps 33030135 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 30904296 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 168660 # Number of float alu accesses -system.cpu0.num_func_calls 809909 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4463035 # number of instructions that are conditional controls -system.cpu0.num_int_insts 30904296 # number of integer instructions -system.cpu0.num_fp_insts 168660 # number of float instructions -system.cpu0.num_int_register_reads 43221651 # number of times the integer registers were read -system.cpu0.num_int_register_writes 22562663 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 87082 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 88661 # number of times the floating registers were written -system.cpu0.num_mem_refs 8422848 # number of memory refs -system.cpu0.num_load_insts 4904051 # Number of load instructions -system.cpu0.num_store_insts 3518797 # Number of store instructions -system.cpu0.num_idle_cycles 214028158129.505707 # Number of idle cycles -system.cpu0.num_busy_cycles -213099624110.505707 # Number of busy cycles -system.cpu0.not_idle_fraction -229.501149 # Percentage of non-idle cycles -system.cpu0.idle_fraction 230.501149 # Percentage of idle cycles +system.cpu0.committedInsts 33851772 # Number of instructions committed +system.cpu0.committedOps 33851772 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 31712153 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 169925 # Number of float alu accesses +system.cpu0.num_func_calls 812668 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4695347 # number of instructions that are conditional controls +system.cpu0.num_int_insts 31712153 # number of integer instructions +system.cpu0.num_fp_insts 169925 # number of float instructions +system.cpu0.num_int_register_reads 44553309 # number of times the integer registers were read +system.cpu0.num_int_register_writes 23136473 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 87700 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 89305 # number of times the floating registers were written +system.cpu0.num_mem_refs 8457205 # number of memory refs +system.cpu0.num_load_insts 4937806 # Number of load instructions +system.cpu0.num_store_insts 3519399 # Number of store instructions +system.cpu0.num_idle_cycles 213007832176.448029 # Number of idle cycles +system.cpu0.num_busy_cycles -212079453354.448029 # Number of busy cycles +system.cpu0.not_idle_fraction -228.440641 # Percentage of non-idle cycles +system.cpu0.idle_fraction 229.440641 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6421 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 211352 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 74794 40.97% 40.97% # number of times we switched to this ipl +system.cpu0.kern.inst.quiesce 6420 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 211383 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 74805 40.97% 40.97% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1878 1.03% 42.11% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 105677 57.89% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 182552 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 73427 49.30% 49.30% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count::22 1879 1.03% 42.11% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 105697 57.89% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 182584 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 73438 49.30% 49.30% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1878 1.26% 50.70% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 73427 49.30% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 148935 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1818574542500 98.74% 98.74% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 39495500 0.00% 98.75% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 364949500 0.02% 98.77% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 22741309000 1.23% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1841720296500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.981723 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good::22 1879 1.26% 50.70% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 73438 49.30% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 148958 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1819523663000 98.74% 98.74% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 39251000 0.00% 98.74% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 365640000 0.02% 98.76% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 22768477500 1.24% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1842697031500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.981726 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.694825 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.815850 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.694797 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.815833 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -712,29 +847,29 @@ system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu0.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu0.kern.callpal::swpipl 175295 91.20% 93.41% # number of callpals executed -system.cpu0.kern.callpal::rdps 6782 3.53% 96.94% # number of callpals executed +system.cpu0.kern.callpal::swpipl 175325 91.20% 93.41% # number of callpals executed +system.cpu0.kern.callpal::rdps 6783 3.53% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::rdusp 9 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::whami 2 0.00% 96.95% # number of callpals executed -system.cpu0.kern.callpal::rti 5175 2.69% 99.64% # number of callpals executed +system.cpu0.kern.callpal::rti 5176 2.69% 99.64% # number of callpals executed system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 192206 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 5921 # number of protection mode switches +system.cpu0.kern.callpal::total 192238 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 5923 # number of protection mode switches system.cpu0.kern.mode_switch::user 1738 # number of protection mode switches -system.cpu0.kern.mode_switch::idle 2094 # number of protection mode switches +system.cpu0.kern.mode_switch::idle 2093 # number of protection mode switches system.cpu0.kern.mode_good::kernel 1907 system.cpu0.kern.mode_good::user 1738 system.cpu0.kern.mode_good::idle 169 -system.cpu0.kern.mode_switch_good::kernel 0.322074 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.321965 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::idle 0.080707 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.391059 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 29798472500 1.62% 1.62% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2570740000 0.14% 1.76% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::idle 1809351079500 98.24% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::idle 0.080745 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::total 0.391019 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 29806042000 1.62% 1.62% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2607375500 0.14% 1.76% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::idle 1810283609500 98.24% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 4175 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -767,372 +902,458 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 953317 # number of replacements -system.cpu0.icache.tagsinuse 511.202573 # Cycle average of tags in use -system.cpu0.icache.total_refs 42520473 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 953828 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 44.578764 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 10247489000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 251.172377 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 83.809654 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu2.inst 176.220543 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.490571 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu1.inst 0.163691 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu2.inst 0.344181 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.998443 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 32512787 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 7733014 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 2274672 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 42520473 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 32512787 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 7733014 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 2274672 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 42520473 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 32512787 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 7733014 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 2274672 # number of overall hits -system.cpu0.icache.overall_hits::total 42520473 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 524229 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 129219 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 317357 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 970805 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 524229 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 129219 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 317357 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 970805 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 524229 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 129219 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 317357 # number of overall misses -system.cpu0.icache.overall_misses::total 970805 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1820764500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4451463485 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6272227985 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 1820764500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 4451463485 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 6272227985 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 1820764500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 4451463485 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 6272227985 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 33037016 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 7862233 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 2592029 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 43491278 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 33037016 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 7862233 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 2592029 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 43491278 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 33037016 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 7862233 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 2592029 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 43491278 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015868 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016435 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.122436 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.022322 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015868 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016435 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.122436 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.022322 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015868 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016435 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.122436 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.022322 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14090.532352 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14026.674959 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 6460.852576 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14090.532352 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14026.674959 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 6460.852576 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14090.532352 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14026.674959 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 6460.852576 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 7042 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 180 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 39.122222 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.toL2Bus.throughput 110454960 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 786209 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 786164 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 3749 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 3749 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 371427 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 18 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 19 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 150852 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 133572 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 30 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 847417 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 1371009 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count 2218426 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 27116864 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 55346243 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size 82463107 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 203524040 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 11072 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 2135036000 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 243000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 1907460021 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 2223763109 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.iobus.throughput 1469142 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 2977 # Transaction distribution +system.iobus.trans_dist::ReadResp 2977 # Transaction distribution +system.iobus.trans_dist::WriteReq 21029 # Transaction distribution +system.iobus.trans_dist::WriteResp 21029 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 2342 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 140 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 66 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 8346 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 2386 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 34 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 13314 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 34698 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 34698 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.cchip.pio 2342 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.pchip.pio 140 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.io.pio 66 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.uart.pio 8346 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.ide.pio 2386 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.ide-pciconf 34 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.iocache.cpu_side 34698 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 48012 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 9368 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 560 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 61 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 4173 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 1554 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 31 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 15747 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 1107368 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 1107368 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.cchip.pio 9368 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.pchip.pio 560 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.io.pio 61 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.uart.pio 4173 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.ide.pio 1554 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.ide-pciconf 31 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.iocache.cpu_side 1107368 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 1123115 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 2707184 # Total data (bytes) +system.iobus.reqLayer0.occupancy 2208000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 105000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer22.occupancy 57000 # Layer occupancy (ticks) +system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 6219000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 1797000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 20000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer29.occupancy 157278470 # Layer occupancy (ticks) +system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 9565000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer1.occupancy 17530000 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu0.icache.replacements 950939 # number of replacements +system.cpu0.icache.tagsinuse 511.192426 # Cycle average of tags in use +system.cpu0.icache.total_refs 43369559 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 951450 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 45.582594 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 10375508000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 249.451681 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu1.inst 99.242283 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu2.inst 162.498462 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.487210 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu1.inst 0.193833 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu2.inst 0.317380 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.998423 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 33330806 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 7798498 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 2240255 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 43369559 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 33330806 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 7798498 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 2240255 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 43369559 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 33330806 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 7798498 # 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number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7567 # number of LoadLockedReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 1 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 152979 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 345859 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 498838 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 152979 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 345859 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 498838 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 1973436500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4297066000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6270502500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1295329500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2136901128 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3432230628 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 24853500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 70377000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 95230500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 11000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 11000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3268766000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 6433967128 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 9702733128 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3268766000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 6433967128 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 9702733128 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 287559000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 353651000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 641210000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 356203000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 430620000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 786823000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 643762000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 784271000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1428033000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.087118 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.088515 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.041030 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.053190 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.045415 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021583 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.103394 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.099840 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.038037 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 144505 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 341032 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 485537 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 144505 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 341032 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 485537 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2060552500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4252408235 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6312960735 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1528691000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2589747290 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4118438290 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 24153500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 66206002 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 90359502 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 23000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 23000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3589243500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 6842155525 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10431399025 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3589243500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 6842155525 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10431399025 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 295697000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 311546500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 607243500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 363354500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 427379500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 790734000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 659051500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 738926000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1397977500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.083742 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.086377 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.039510 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.051114 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.046891 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021691 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.100373 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.099599 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.037310 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000019 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.072520 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.071857 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.033094 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.072520 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.071857 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.033094 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 18847.946095 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16439.918892 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17128.636129 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26831.748695 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 25295.057091 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25853.870875 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11175.134892 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12798.145117 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12330.765247 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21367.416443 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18602.861652 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19450.669612 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21367.416443 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 18602.861652 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19450.669612 # average overall mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.069824 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.070926 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.032237 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.069824 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.070926 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.032237 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 20733.659013 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16820.503202 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17924.719500 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33878.310396 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 29355.224833 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30885.816310 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11213.324048 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12230.925919 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11941.258359 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 23000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24838.195910 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20063.089461 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21484.251509 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24838.195910 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20063.089461 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21484.251509 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1147,22 +1368,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1221065 # DTB read hits -system.cpu1.dtb.read_misses 1489 # DTB read misses -system.cpu1.dtb.read_acv 40 # DTB read access violations -system.cpu1.dtb.read_accesses 143781 # DTB read accesses -system.cpu1.dtb.write_hits 929390 # DTB write hits -system.cpu1.dtb.write_misses 202 # DTB write misses -system.cpu1.dtb.write_acv 24 # DTB write access violations -system.cpu1.dtb.write_accesses 59266 # DTB write accesses -system.cpu1.dtb.data_hits 2150455 # DTB hits -system.cpu1.dtb.data_misses 1691 # DTB misses -system.cpu1.dtb.data_acv 64 # DTB access violations -system.cpu1.dtb.data_accesses 203047 # DTB accesses -system.cpu1.itb.fetch_hits 872017 # ITB hits -system.cpu1.itb.fetch_misses 756 # ITB misses -system.cpu1.itb.fetch_acv 43 # ITB acv -system.cpu1.itb.fetch_accesses 872773 # ITB accesses +system.cpu1.dtb.read_hits 1206143 # DTB read hits +system.cpu1.dtb.read_misses 1395 # DTB read misses +system.cpu1.dtb.read_acv 35 # DTB read access violations +system.cpu1.dtb.read_accesses 142828 # DTB read accesses +system.cpu1.dtb.write_hits 904590 # DTB write hits +system.cpu1.dtb.write_misses 190 # DTB write misses +system.cpu1.dtb.write_acv 23 # DTB write access violations +system.cpu1.dtb.write_accesses 58592 # DTB write accesses +system.cpu1.dtb.data_hits 2110733 # DTB hits +system.cpu1.dtb.data_misses 1585 # DTB misses +system.cpu1.dtb.data_acv 58 # DTB access violations +system.cpu1.dtb.data_accesses 201420 # DTB accesses +system.cpu1.itb.fetch_hits 862559 # ITB hits +system.cpu1.itb.fetch_misses 707 # ITB misses +system.cpu1.itb.fetch_acv 34 # ITB acv +system.cpu1.itb.fetch_accesses 863266 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1175,28 +1396,28 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 953614996 # number of cpu cycles simulated +system.cpu1.numCycles 953614983 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7860477 # Number of instructions committed -system.cpu1.committedOps 7860477 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 7311992 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 45303 # Number of float alu accesses -system.cpu1.num_func_calls 212165 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 960179 # number of instructions that are conditional controls -system.cpu1.num_int_insts 7311992 # number of integer instructions -system.cpu1.num_fp_insts 45303 # number of float instructions -system.cpu1.num_int_register_reads 10165443 # number of times the integer registers were read -system.cpu1.num_int_register_writes 5319467 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 24490 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 24717 # number of times the floating registers were written -system.cpu1.num_mem_refs 2158115 # number of memory refs -system.cpu1.num_load_insts 1226297 # Number of load instructions -system.cpu1.num_store_insts 931818 # Number of store instructions -system.cpu1.num_idle_cycles -703122010.262243 # Number of idle cycles -system.cpu1.num_busy_cycles 1656737006.262243 # Number of busy cycles -system.cpu1.not_idle_fraction 1.737323 # Percentage of non-idle cycles -system.cpu1.idle_fraction -0.737323 # Percentage of idle cycles +system.cpu1.committedInsts 7923216 # Number of instructions committed +system.cpu1.committedOps 7923216 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 7378774 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 44696 # Number of float alu accesses +system.cpu1.num_func_calls 212761 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1003934 # number of instructions that are conditional controls +system.cpu1.num_int_insts 7378774 # number of integer instructions +system.cpu1.num_fp_insts 44696 # number of float instructions +system.cpu1.num_int_register_reads 10322317 # number of times the integer registers were read +system.cpu1.num_int_register_writes 5366754 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 24140 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 24473 # number of times the floating registers were written +system.cpu1.num_mem_refs 2118035 # number of memory refs +system.cpu1.num_load_insts 1211092 # Number of load instructions +system.cpu1.num_store_insts 906943 # Number of store instructions +system.cpu1.num_idle_cycles -710985323.015638 # Number of idle cycles +system.cpu1.num_busy_cycles 1664600306.015638 # Number of busy cycles +system.cpu1.not_idle_fraction 1.745569 # Percentage of non-idle cycles +system.cpu1.idle_fraction -0.745569 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed @@ -1214,35 +1435,35 @@ system.cpu1.kern.mode_ticks::kernel 0 # nu system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu1.kern.swap_context 0 # number of times the context was actually changed -system.cpu2.branchPred.lookups 8370437 # Number of BP lookups -system.cpu2.branchPred.condPredicted 7682240 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 128031 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 6854257 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 5743720 # Number of BTB hits +system.cpu2.branchPred.lookups 8997247 # Number of BP lookups +system.cpu2.branchPred.condPredicted 8318296 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 124435 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 7453298 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 6389224 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 83.797850 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 284899 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 14987 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 85.723448 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 282371 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 13443 # Number of incorrect RAS predictions. system.cpu2.dtb.fetch_hits 0 # ITB hits system.cpu2.dtb.fetch_misses 0 # ITB misses system.cpu2.dtb.fetch_acv 0 # ITB acv system.cpu2.dtb.fetch_accesses 0 # ITB accesses -system.cpu2.dtb.read_hits 3211638 # DTB read hits -system.cpu2.dtb.read_misses 11756 # DTB read misses -system.cpu2.dtb.read_acv 123 # DTB read access violations -system.cpu2.dtb.read_accesses 216825 # DTB read accesses -system.cpu2.dtb.write_hits 1985602 # DTB write hits -system.cpu2.dtb.write_misses 2511 # DTB write misses -system.cpu2.dtb.write_acv 137 # DTB write access violations -system.cpu2.dtb.write_accesses 81903 # DTB write accesses -system.cpu2.dtb.data_hits 5197240 # DTB hits -system.cpu2.dtb.data_misses 14267 # DTB misses -system.cpu2.dtb.data_acv 260 # DTB access violations -system.cpu2.dtb.data_accesses 298728 # DTB accesses -system.cpu2.itb.fetch_hits 370869 # ITB hits -system.cpu2.itb.fetch_misses 5705 # ITB misses -system.cpu2.itb.fetch_acv 274 # ITB acv -system.cpu2.itb.fetch_accesses 376574 # ITB accesses +system.cpu2.dtb.read_hits 3184667 # DTB read hits +system.cpu2.dtb.read_misses 11563 # DTB read misses +system.cpu2.dtb.read_acv 122 # DTB read access violations +system.cpu2.dtb.read_accesses 218108 # DTB read accesses +system.cpu2.dtb.write_hits 2003168 # DTB write hits +system.cpu2.dtb.write_misses 2582 # DTB write misses +system.cpu2.dtb.write_acv 105 # DTB write access violations +system.cpu2.dtb.write_accesses 82984 # DTB write accesses +system.cpu2.dtb.data_hits 5187835 # DTB hits +system.cpu2.dtb.data_misses 14145 # DTB misses +system.cpu2.dtb.data_acv 227 # DTB access violations +system.cpu2.dtb.data_accesses 301092 # DTB accesses +system.cpu2.itb.fetch_hits 370432 # ITB hits +system.cpu2.itb.fetch_misses 5697 # ITB misses +system.cpu2.itb.fetch_acv 245 # ITB acv +system.cpu2.itb.fetch_accesses 376129 # ITB accesses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.read_acv 0 # DTB read access violations @@ -1255,270 +1476,270 @@ system.cpu2.itb.data_hits 0 # DT system.cpu2.itb.data_misses 0 # DTB misses system.cpu2.itb.data_acv 0 # DTB access violations system.cpu2.itb.data_accesses 0 # DTB accesses -system.cpu2.numCycles 30454355 # number of cpu cycles simulated +system.cpu2.numCycles 31194709 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 8502723 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 34791371 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 8370437 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 6028619 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 8097928 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 618452 # Number of cycles fetch has spent squashing -system.cpu2.fetch.BlockedCycles 9649671 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 10614 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 1974 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 63437 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 88147 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 485 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 2592037 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 89025 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 26817742 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.297327 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.307851 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 8336463 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 36595534 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 8997247 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 6671595 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 8714180 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 607609 # Number of cycles fetch has spent squashing +system.cpu2.fetch.BlockedCycles 9678498 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 11323 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 1980 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 64467 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 86613 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 511 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 2554168 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 86055 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 27288913 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.341040 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.295561 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 18719814 69.80% 69.80% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 271918 1.01% 70.82% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 439106 1.64% 72.46% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 4240914 15.81% 88.27% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 731900 2.73% 91.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 166811 0.62% 91.62% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 194731 0.73% 92.35% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 431926 1.61% 93.96% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 1620622 6.04% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 18574733 68.07% 68.07% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 269160 0.99% 69.05% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 428961 1.57% 70.63% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 4866915 17.83% 88.46% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 754326 2.76% 91.22% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 165422 0.61% 91.83% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 191254 0.70% 92.53% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 429367 1.57% 94.10% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 1608775 5.90% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 26817742 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.274852 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.142410 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 8640997 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 9744638 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 7501940 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 293665 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 390587 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 167981 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 12867 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 34389263 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 40403 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 390587 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 8994385 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 2850333 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 5733998 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 7360278 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 1242256 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 33240737 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 2380 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 234906 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 409580 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 22320164 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 41423386 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 41259446 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 163940 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 20500425 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 1819739 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 502711 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 59638 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3682174 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 3369954 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 2075842 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 372990 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 254270 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 30724821 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 626542 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 30272457 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 30970 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 2165066 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 1087715 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 442386 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 26817742 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.128822 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.564509 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 27288913 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.288422 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.173133 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 8484758 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 9763089 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 8105885 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 306526 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 382761 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 165822 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 12764 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 36197990 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 39851 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 382761 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 8844170 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 2798398 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 5770090 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 7975185 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 1272419 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 35047656 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 2444 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 232046 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 447152 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 23489226 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 43822690 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 43659490 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 163200 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 21694214 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 1795012 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 501276 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 59320 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3724979 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 3343402 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 2093050 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 368261 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 257932 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 32557394 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 620599 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 32107794 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 34091 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 2143269 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 1080696 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 438167 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 27288913 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.176588 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.573888 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 15272797 56.95% 56.95% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 3099841 11.56% 68.51% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 1551477 5.79% 74.29% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 5057037 18.86% 93.15% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 907037 3.38% 96.53% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 485633 1.81% 98.34% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 283575 1.06% 99.40% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 141972 0.53% 99.93% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 18373 0.07% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 15150790 55.52% 55.52% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 3070151 11.25% 66.77% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 1548988 5.68% 72.45% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 5689584 20.85% 93.30% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 903005 3.31% 96.61% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 480338 1.76% 98.37% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 283929 1.04% 99.41% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 143393 0.53% 99.93% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 18735 0.07% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 26817742 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 27288913 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 34129 13.74% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 111357 44.84% 58.58% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 102854 41.42% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 33803 13.75% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 111727 45.45% 59.20% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 100297 40.80% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 2448 0.01% 0.01% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 24602631 81.27% 81.28% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 20294 0.07% 81.35% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 81.35% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 8465 0.03% 81.37% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 81.37% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 81.37% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 81.37% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 1224 0.00% 81.38% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 81.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 81.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 81.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 81.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 81.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 81.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 81.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 81.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 81.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 81.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 81.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 81.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 81.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 81.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 81.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 81.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 81.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 81.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 81.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 81.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 81.38% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 3340354 11.03% 92.41% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 2007868 6.63% 99.04% # Type of FU issued -system.cpu2.iq.FU_type_0::IprAccess 289173 0.96% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 26449669 82.38% 82.39% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 20147 0.06% 82.45% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 82.45% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 8446 0.03% 82.47% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 82.47% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 82.47% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 82.47% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 1224 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 3312033 10.32% 92.79% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 2025467 6.31% 99.10% # Type of FU issued +system.cpu2.iq.FU_type_0::IprAccess 288360 0.90% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 30272457 # Type of FU issued -system.cpu2.iq.rate 0.994027 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 248340 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.008203 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 87406741 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 33405587 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 29873950 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 235225 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 114899 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 111509 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 30395868 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 122481 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 188565 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 32107794 # Type of FU issued +system.cpu2.iq.rate 1.029271 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 245827 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.007656 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 91550157 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 35210267 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 31710626 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 234262 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 114809 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 110859 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 32229265 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 121908 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 186278 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 411297 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 939 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 4131 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 160227 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 409987 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1098 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 3916 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 156672 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 4708 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 24260 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 4171 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 28368 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 390587 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 2070216 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 210596 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 32630441 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 224813 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 3369954 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 2075842 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 556425 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 148713 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 2116 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 4131 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 65748 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 128933 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 194681 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 30112166 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 3231643 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 160291 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 382761 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 2017515 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 205037 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 34446466 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 224960 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 3343402 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 2093050 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 551127 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 142834 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 2166 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 3916 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 63764 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 127616 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 191380 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 31948816 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 3204490 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 158978 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 1279078 # number of nop insts executed -system.cpu2.iew.exec_refs 5224243 # number of memory reference insts executed -system.cpu2.iew.exec_branches 6789433 # Number of branches executed -system.cpu2.iew.exec_stores 1992600 # Number of stores executed -system.cpu2.iew.exec_rate 0.988764 # Inst execution rate -system.cpu2.iew.wb_sent 30017965 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 29985459 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 17323993 # num instructions producing a value -system.cpu2.iew.wb_consumers 20546016 # num instructions consuming a value +system.cpu2.iew.exec_nop 1268473 # number of nop insts executed +system.cpu2.iew.exec_refs 5214665 # number of memory reference insts executed +system.cpu2.iew.exec_branches 7427208 # Number of branches executed +system.cpu2.iew.exec_stores 2010175 # Number of stores executed +system.cpu2.iew.exec_rate 1.024174 # Inst execution rate +system.cpu2.iew.wb_sent 31853816 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 31821485 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 18500784 # num instructions producing a value +system.cpu2.iew.wb_consumers 21694431 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.984603 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.843180 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.020092 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.852790 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 2350466 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 184156 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 180720 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 26427155 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.144119 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.849310 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 2318994 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 182432 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 176935 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 26906152 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.192355 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.846387 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 16325181 61.77% 61.77% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 2317842 8.77% 70.54% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1215370 4.60% 75.14% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 4792789 18.14% 93.28% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 500443 1.89% 95.17% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 186108 0.70% 95.88% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 178909 0.68% 96.55% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 180996 0.68% 97.24% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 729517 2.76% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 16157542 60.05% 60.05% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 2331595 8.67% 68.72% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1218913 4.53% 73.25% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 5433463 20.19% 93.44% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 503772 1.87% 95.31% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 185469 0.69% 96.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 177448 0.66% 96.66% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 178843 0.66% 97.33% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 719107 2.67% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 26427155 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 30235823 # Number of instructions committed -system.cpu2.commit.committedOps 30235823 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 26906152 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 32081688 # Number of instructions committed +system.cpu2.commit.committedOps 32081688 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 4874272 # Number of memory references committed -system.cpu2.commit.loads 2958657 # Number of loads committed -system.cpu2.commit.membars 64665 # Number of memory barriers committed -system.cpu2.commit.branches 6641301 # Number of branches committed -system.cpu2.commit.fp_insts 110294 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 28781664 # Number of committed integer instructions. -system.cpu2.commit.function_calls 230734 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 729517 # number cycles where commit BW limit reached +system.cpu2.commit.refs 4869793 # Number of memory references committed +system.cpu2.commit.loads 2933415 # Number of loads committed +system.cpu2.commit.membars 63859 # Number of memory barriers committed +system.cpu2.commit.branches 7280639 # Number of branches committed +system.cpu2.commit.fp_insts 109636 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 30638732 # Number of committed integer instructions. +system.cpu2.commit.function_calls 228563 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 719107 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 58211181 # The number of ROB reads -system.cpu2.rob.rob_writes 65562875 # The number of ROB writes -system.cpu2.timesIdled 242498 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 3636613 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 1745370399 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 29064101 # Number of Instructions Simulated -system.cpu2.committedOps 29064101 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 29064101 # Number of Instructions Simulated -system.cpu2.cpi 1.047834 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.047834 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.954350 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.954350 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 39595533 # number of integer regfile reads -system.cpu2.int_regfile_writes 21195830 # number of integer regfile writes -system.cpu2.fp_regfile_reads 68078 # number of floating regfile reads -system.cpu2.fp_regfile_writes 68404 # number of floating regfile writes -system.cpu2.misc_regfile_reads 4592506 # number of misc regfile reads -system.cpu2.misc_regfile_writes 258747 # number of misc regfile writes +system.cpu2.rob.rob_reads 60513787 # The number of ROB reads +system.cpu2.rob.rob_writes 69183653 # The number of ROB writes +system.cpu2.timesIdled 245794 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 3905796 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 1746583104 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 30918811 # Number of Instructions Simulated +system.cpu2.committedOps 30918811 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 30918811 # Number of Instructions Simulated +system.cpu2.cpi 1.008923 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.008923 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.991156 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.991156 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 42017360 # number of integer regfile reads +system.cpu2.int_regfile_writes 22376128 # number of integer regfile writes +system.cpu2.fp_regfile_reads 67819 # number of floating regfile reads +system.cpu2.fp_regfile_writes 67985 # number of floating regfile writes +system.cpu2.misc_regfile_reads 5215792 # number of misc regfile reads +system.cpu2.misc_regfile_writes 257331 # number of misc regfile writes system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu2.kern.inst.hwrei 0 # number of hwrei instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 0b387654e..bab672da1 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,134 +1,134 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.533116 # Number of seconds simulated -sim_ticks 2533115780500 # Number of ticks simulated -final_tick 2533115780500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.534279 # Number of seconds simulated +sim_ticks 2534279149500 # Number of ticks simulated +final_tick 2534279149500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 55678 # Simulator instruction rate (inst/s) -host_op_rate 71642 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2338649550 # Simulator tick rate (ticks/s) -host_mem_usage 398880 # Number of bytes of host memory used -host_seconds 1083.15 # Real time elapsed on the host -sim_insts 60307726 # Number of instructions simulated -sim_ops 77599286 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 2624 # Number of bytes read from this memory +host_inst_rate 43780 # Simulator instruction rate (inst/s) +host_op_rate 56332 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1839722930 # Simulator tick rate (ticks/s) +host_mem_usage 400528 # Number of bytes of host memory used +host_seconds 1377.53 # Real time elapsed on the host +sim_insts 60307893 # Number of instructions simulated +sim_ops 77599512 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::realview.clcd 119547392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 2880 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 796160 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9093200 # Number of bytes read from this memory -system.physmem.bytes_read::total 129429776 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 796160 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 796160 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3781760 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 796992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9094160 # Number of bytes read from this memory +system.physmem.bytes_read::total 129441552 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 796992 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 796992 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3783360 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6797832 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 41 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 6799432 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 14943424 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 45 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12440 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142115 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096806 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59090 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 12453 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142130 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15098054 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59115 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813108 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47189972 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1036 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 813133 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47172148 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1136 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 314301 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3589729 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51095089 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 314301 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314301 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1492928 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1190657 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2683585 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1492928 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47189972 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1036 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 314485 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3588460 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51076280 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 314485 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314485 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1492874 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1190110 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2682985 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1492874 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47172148 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1136 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 314301 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4780386 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53778674 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15096806 # Total number of read requests seen -system.physmem.writeReqs 813108 # Total number of write requests seen -system.physmem.cpureqs 218339 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 966195584 # Total number of bytes read from memory -system.physmem.bytesWritten 52038912 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 129429776 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6797832 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 312 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4687 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 943937 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 943440 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 943392 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 944197 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 943973 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 943153 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 943272 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 943872 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 943794 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 943286 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 943217 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 943610 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 943691 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 943079 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 942979 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 943602 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50829 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 50406 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50439 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51150 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50909 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50184 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50277 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50865 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51361 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 50899 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50798 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51185 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51244 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 50710 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 50627 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51225 # Track writes on a per bank basis +system.physmem.bw_total::cpu.inst 314485 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4778571 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53759265 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15098054 # Total number of read requests seen +system.physmem.writeReqs 813133 # Total number of write requests seen +system.physmem.cpureqs 218381 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 966275456 # Total number of bytes read from memory +system.physmem.bytesWritten 52040512 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 129441552 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6799432 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 339 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4672 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 944601 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 943433 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 943409 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 943592 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 943465 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 943701 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 943525 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 943240 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 944001 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 943648 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 943214 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 942809 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 943923 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 943684 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 943779 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 943691 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 49135 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 48909 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50973 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51086 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 51003 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 51258 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 51261 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51198 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51347 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51095 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50750 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 50404 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51353 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 50977 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51264 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51120 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 32506 # Number of times wr buffer was full causing retry -system.physmem.totGap 2533114676500 # Total gap between requests +system.physmem.numWrRetry 32444 # Number of times wr buffer was full causing retry +system.physmem.totGap 2534279100000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 36 # Categorize read packet sizes -system.physmem.readPktSize::3 14942208 # Categorize read packet sizes +system.physmem.readPktSize::3 14943424 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154562 # Categorize read packet sizes +system.physmem.readPktSize::6 154594 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 754018 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 59090 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1040416 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 981351 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 950574 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3550435 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2676222 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2687728 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2649399 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 60672 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 59169 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 108674 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 157504 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 108150 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 16730 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 16584 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 20063 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 12694 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 112 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 9 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59115 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1052560 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 982701 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 988227 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3681755 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2757300 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2755283 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2712082 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 17052 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 15182 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 27533 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 39830 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 27503 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 10257 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 10197 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 13755 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 6392 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 94 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -139,59 +139,326 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2575 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2624 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2659 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2706 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2730 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2756 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2782 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2805 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 2829 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32778 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32729 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32694 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32647 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32623 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 32597 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 32571 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 32548 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 32524 # What write queue length does an incoming req see -system.physmem.totQLat 393224294250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 485624283000 # Sum of mem lat for all requests -system.physmem.totBusLat 75482470000 # Total cycles spent in databus access -system.physmem.totBankLat 16917518750 # Total cycles spent in bank access -system.physmem.avgQLat 26047.39 # Average queueing delay per request -system.physmem.avgBankLat 1120.63 # Average bank access latency per request +system.physmem.wrQLenPdf::0 2591 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2647 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2703 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2761 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2791 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2818 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 2847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 2874 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 2892 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32763 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32707 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32651 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32593 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32563 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32536 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 32507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 32480 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 32462 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 42559 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 23924.789210 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 1816.195393 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 32272.883514 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-95 8308 19.52% 19.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-159 3417 8.03% 27.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-223 2234 5.25% 32.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-287 1796 4.22% 37.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-351 1258 2.96% 39.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-415 1103 2.59% 42.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-479 837 1.97% 44.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-543 830 1.95% 46.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-607 538 1.26% 47.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-671 533 1.25% 49.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-735 414 0.97% 49.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-799 384 0.90% 50.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-863 258 0.61% 51.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-927 273 0.64% 52.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-991 193 0.45% 52.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1055 240 0.56% 53.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1119 148 0.35% 53.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1183 144 0.34% 53.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1247 105 0.25% 54.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1311 120 0.28% 54.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1375 89 0.21% 54.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1439 396 0.93% 55.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1503 1932 4.54% 60.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1567 440 1.03% 61.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1631 89 0.21% 61.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1695 139 0.33% 61.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1759 56 0.13% 61.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1823 104 0.24% 61.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1887 40 0.09% 62.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1951 62 0.15% 62.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-2015 22 0.05% 62.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2079 58 0.14% 62.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2143 29 0.07% 62.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2207 47 0.11% 62.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2271 13 0.03% 62.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2335 37 0.09% 62.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2399 11 0.03% 62.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2463 28 0.07% 62.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2527 17 0.04% 62.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2591 25 0.06% 62.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2655 7 0.02% 62.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2719 18 0.04% 62.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2783 4 0.01% 62.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2847 18 0.04% 63.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2911 6 0.01% 63.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2975 14 0.03% 63.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3039 6 0.01% 63.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3103 12 0.03% 63.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3167 2 0.00% 63.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3231 7 0.02% 63.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3295 6 0.01% 63.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3359 17 0.04% 63.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3423 5 0.01% 63.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3487 8 0.02% 63.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3551 3 0.01% 63.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3615 5 0.01% 63.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3679 6 0.01% 63.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3743 9 0.02% 63.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3807 1 0.00% 63.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3871 5 0.01% 63.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3935 4 0.01% 63.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3999 9 0.02% 63.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4063 4 0.01% 63.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4127 39 0.09% 63.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4191 5 0.01% 63.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4255 7 0.02% 63.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4319 4 0.01% 63.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4383 6 0.01% 63.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4447 2 0.00% 63.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4511 3 0.01% 63.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4575 4 0.01% 63.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4639 4 0.01% 63.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4767 6 0.01% 63.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4831 1 0.00% 63.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4895 8 0.02% 63.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4959 3 0.01% 63.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-5023 5 0.01% 63.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5151 5 0.01% 63.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5215 1 0.00% 63.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5279 1 0.00% 63.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5343 1 0.00% 63.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5407 1 0.00% 63.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5471 2 0.00% 63.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5535 3 0.01% 63.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5599 1 0.00% 63.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5663 2 0.00% 63.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5727 3 0.01% 63.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5919 3 0.01% 63.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6047 3 0.01% 63.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6111 1 0.00% 63.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6175 6 0.01% 63.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6239 3 0.01% 63.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6303 1 0.00% 63.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6431 1 0.00% 63.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6495 2 0.00% 63.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6559 3 0.01% 63.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6623 2 0.00% 63.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6687 3 0.01% 63.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6751 1 0.00% 63.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6815 18 0.04% 63.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6879 5 0.01% 63.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6943 1 0.00% 63.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7071 8 0.02% 63.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7199 6 0.01% 63.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7327 1 0.00% 63.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7391 1 0.00% 63.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7455 8 0.02% 63.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7583 9 0.02% 63.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7647 2 0.00% 63.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7711 6 0.01% 63.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7839 3 0.01% 63.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7903 3 0.01% 63.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7967 4 0.01% 63.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8031 5 0.01% 63.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8095 7 0.02% 63.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8159 4 0.01% 63.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8223 322 0.76% 64.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8735 1 0.00% 64.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8991 1 0.00% 64.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9152-9183 1 0.00% 64.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9247 2 0.00% 64.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9503 1 0.00% 64.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9536-9567 1 0.00% 64.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10271 19 0.04% 64.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10527 1 0.00% 64.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11039 1 0.00% 64.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11295 1 0.00% 64.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11551 2 0.00% 64.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11904-11935 1 0.00% 64.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12319 1 0.00% 64.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12575 2 0.00% 64.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13343 4 0.01% 64.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13599 1 0.00% 64.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13855 1 0.00% 64.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14367 2 0.00% 64.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14623 1 0.00% 64.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14879 2 0.00% 64.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15040-15071 1 0.00% 64.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15199 1 0.00% 64.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15391 3 0.01% 64.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15647 2 0.00% 64.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16159 1 0.00% 64.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16415 2 0.00% 64.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16671 1 0.00% 64.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16896-16927 3 0.01% 64.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17183 2 0.00% 64.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17216-17247 2 0.00% 64.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17344-17375 1 0.00% 64.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17439 2 0.00% 64.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17792-17823 1 0.00% 64.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17951 2 0.00% 64.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17984-18015 1 0.00% 64.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18207 2 0.00% 64.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18463 2 0.00% 64.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19231 2 0.00% 64.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19840-19871 1 0.00% 64.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20224-20255 3 0.01% 64.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20544-20575 1 0.00% 64.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20736-20767 1 0.00% 64.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21248-21279 1 0.00% 64.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21312-21343 1 0.00% 64.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21535 2 0.00% 64.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22016-22047 1 0.00% 64.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22272-22303 1 0.00% 64.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22400-22431 1 0.00% 64.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22559 1 0.00% 64.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22592-22623 1 0.00% 64.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22784-22815 1 0.00% 64.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23040-23071 1 0.00% 64.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23583 2 0.00% 64.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23808-23839 2 0.00% 64.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24351 2 0.00% 64.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24607 4 0.01% 64.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25088-25119 1 0.00% 64.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25631 3 0.01% 64.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25664-25695 1 0.00% 64.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25728-25759 1 0.00% 64.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26399 1 0.00% 64.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26655 2 0.00% 64.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27328-27359 1 0.00% 64.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27456-27487 1 0.00% 64.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27679 1 0.00% 64.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28447 1 0.00% 64.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28703 1 0.00% 64.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28736-28767 1 0.00% 64.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28959 2 0.00% 64.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29215 1 0.00% 64.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29376-29407 1 0.00% 64.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29471 1 0.00% 64.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29727 1 0.00% 64.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-29983 1 0.00% 64.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30016-30047 1 0.00% 64.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30239 3 0.01% 64.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30592-30623 1 0.00% 64.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30751 1 0.00% 64.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31104-31135 1 0.00% 64.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31263 1 0.00% 64.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31424-31455 1 0.00% 64.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31519 1 0.00% 64.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31775 2 0.00% 64.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32287 1 0.00% 64.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33664-33695 2 0.00% 64.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33728-33759 1 0.00% 64.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33823 44 0.10% 65.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34176-34207 1 0.00% 65.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34752-34783 1 0.00% 65.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36608-36639 1 0.00% 65.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36895 2 0.00% 65.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37248-37279 1 0.00% 65.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39296-39327 1 0.00% 65.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39808-39839 1 0.00% 65.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40000-40031 1 0.00% 65.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-42015 1 0.00% 65.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42048-42079 1 0.00% 65.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42527 2 0.00% 65.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43295 1 0.00% 65.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44672-44703 1 0.00% 65.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44831 1 0.00% 65.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45343 1 0.00% 65.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47647 1 0.00% 65.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47936-47967 1 0.00% 65.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48159 1 0.00% 65.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48671 1 0.00% 65.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48927 1 0.00% 65.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49183 1 0.00% 65.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49920-49951 1 0.00% 65.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50176-50207 2 0.00% 65.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50432-50463 1 0.00% 65.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50688-50719 1 0.00% 65.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::54272-54303 1 0.00% 65.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::56000-56031 1 0.00% 65.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::56832-56863 1 0.00% 65.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::57344-57375 1 0.00% 65.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::58368-58399 1 0.00% 65.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::58944-58975 1 0.00% 65.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::59840-59871 1 0.00% 65.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::62208-62239 1 0.00% 65.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::62848-62879 1 0.00% 65.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::63232-63263 1 0.00% 65.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::63488-63519 2 0.00% 65.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::64256-64287 1 0.00% 65.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::64704-64735 1 0.00% 65.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65024-65055 13 0.03% 65.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65152-65183 18 0.04% 65.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65280-65311 18 0.04% 65.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65344-65375 8 0.02% 65.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65472-65503 18 0.04% 65.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65536-65567 14406 33.85% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::113216-113247 1 0.00% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::129664-129695 1 0.00% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::129792-129823 1 0.00% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::129984-130015 1 0.00% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::130432-130463 1 0.00% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::131072-131103 325 0.76% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::131200-131231 1 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::132096-132127 3 0.01% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::136576-136607 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::168704-168735 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::169664-169695 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::190464-190495 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::196352-196383 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::196608-196639 9 0.02% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 42559 # Bytes accessed per row activation +system.physmem.totQLat 355117101750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 446336213000 # Sum of mem lat for all requests +system.physmem.totBusLat 75488575000 # Total cycles spent in databus access +system.physmem.totBankLat 15730536250 # Total cycles spent in bank access +system.physmem.avgQLat 23521.25 # Average queueing delay per request +system.physmem.avgBankLat 1041.92 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 32168.02 # Average memory access latency -system.physmem.avgRdBW 381.43 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 20.54 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 51.10 # Average consumed read bandwidth in MB/s +system.physmem.avgMemAccLat 29563.16 # Average memory access latency +system.physmem.avgRdBW 381.28 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 20.53 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 51.08 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 2.68 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.14 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.19 # Average read queue length over time -system.physmem.avgWrQLen 11.11 # Average write queue length over time -system.physmem.readRowHits 15020181 # Number of row buffer hits during reads -system.physmem.writeRowHits 793022 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.49 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 97.53 # Row buffer hit rate for writes -system.physmem.avgGap 159216.11 # Average gap between requests +system.physmem.avgRdQLen 0.18 # Average read queue length over time +system.physmem.avgWrQLen 11.71 # Average write queue length over time +system.physmem.readRowHits 15070837 # Number of row buffer hits during reads +system.physmem.writeRowHits 797438 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.82 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 98.07 # Row buffer hit rate for writes +system.physmem.avgGap 159276.56 # Average gap between requests system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -204,43 +471,258 @@ system.realview.nvmem.bw_inst_read::cpu.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 54705448 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16150672 # Transaction distribution +system.membus.trans_dist::ReadResp 16150669 # Transaction distribution +system.membus.trans_dist::WriteReq 763336 # Transaction distribution +system.membus.trans_dist::WriteResp 763336 # Transaction distribution +system.membus.trans_dist::Writeback 59115 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4669 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4672 # Transaction distribution +system.membus.trans_dist::ReadExReq 131424 # Transaction distribution +system.membus.trans_dist::ReadExResp 131424 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382946 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885755 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3770 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272475 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29886845 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 29886845 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.bridge.slave 2382946 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 31772600 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.realview.gic.pio 3770 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 34159320 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390309 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16693592 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7540 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19091509 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119547368 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 119547368 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.bridge.slave 2390309 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 136240960 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.realview.gic.pio 7540 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 138638877 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 138638877 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 1491846000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 17371820500 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.7 # Layer utilization (%) +system.membus.reqLayer3.occupancy 3645000 # Layer occupancy (ticks) +system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer5.occupancy 1500 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 4719558707 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.respLayer2.occupancy 33739093743 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 1.3 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu.branchPred.lookups 14672817 # Number of BP lookups -system.cpu.branchPred.condPredicted 11756302 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 704420 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9794195 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7944325 # Number of BTB hits +system.iobus.throughput 48115298 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16126739 # Transaction distribution +system.iobus.trans_dist::ReadResp 16126726 # Transaction distribution +system.iobus.trans_dist::WriteReq 8158 # Transaction distribution +system.iobus.trans_dist::WriteResp 8158 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7936 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 518 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1026 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382946 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 29886835 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 29886835 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.realview_io.pio 7936 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.timer0.pio 518 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.timer1.pio 1026 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.iocache.cpu_side 29886835 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 32269781 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15872 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1036 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2052 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390309 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 119547288 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::total 119547288 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.realview_io.pio 15872 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.timer0.pio 1036 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.timer1.pio 2052 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.iocache.cpu_side 119547288 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 121937597 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 121937597 # Total data (bytes) +system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 3973000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 518000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 519000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) +system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) +system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks) +system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) +system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 14943424000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) +system.iobus.respLayer0.occupancy 2374788000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) +system.iobus.respLayer1.occupancy 29886822000 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 1.2 # Layer utilization (%) +system.cpu.branchPred.lookups 14673159 # Number of BP lookups +system.cpu.branchPred.condPredicted 11756965 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 704729 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9767663 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7945266 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 81.112588 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1400354 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72452 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 81.342548 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1399657 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 72413 # Number of incorrect RAS predictions. system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 14987449 # DTB read hits -system.cpu.checker.dtb.read_misses 7302 # DTB read misses -system.cpu.checker.dtb.write_hits 11227758 # DTB write hits +system.cpu.checker.dtb.read_hits 14987453 # DTB read hits +system.cpu.checker.dtb.read_misses 7307 # DTB read misses +system.cpu.checker.dtb.write_hits 11227781 # DTB write hits system.cpu.checker.dtb.write_misses 2189 # DTB write misses system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.checker.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.checker.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.checker.dtb.flush_entries 6416 # Number of entries that have been flushed from TLB +system.cpu.checker.dtb.flush_entries 6410 # Number of entries that have been flushed from TLB system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.checker.dtb.prefetch_faults 178 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 14994751 # DTB read accesses -system.cpu.checker.dtb.write_accesses 11229947 # DTB write accesses +system.cpu.checker.dtb.read_accesses 14994760 # DTB read accesses +system.cpu.checker.dtb.write_accesses 11229970 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 26215207 # DTB hits -system.cpu.checker.dtb.misses 9491 # DTB misses -system.cpu.checker.dtb.accesses 26224698 # DTB accesses -system.cpu.checker.itb.inst_hits 61481725 # ITB inst hits +system.cpu.checker.dtb.hits 26215234 # DTB hits +system.cpu.checker.dtb.misses 9496 # DTB misses +system.cpu.checker.dtb.accesses 26224730 # DTB accesses +system.cpu.checker.itb.inst_hits 61481893 # ITB inst hits system.cpu.checker.itb.inst_misses 4471 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -257,36 +739,36 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 61486196 # ITB inst accesses -system.cpu.checker.itb.hits 61481725 # DTB hits +system.cpu.checker.itb.inst_accesses 61486364 # ITB inst accesses +system.cpu.checker.itb.hits 61481893 # DTB hits system.cpu.checker.itb.misses 4471 # DTB misses -system.cpu.checker.itb.accesses 61486196 # DTB accesses -system.cpu.checker.numCycles 77885092 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 61486364 # DTB accesses +system.cpu.checker.numCycles 77885319 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51400888 # DTB read hits -system.cpu.dtb.read_misses 64225 # DTB read misses -system.cpu.dtb.write_hits 11700104 # DTB write hits -system.cpu.dtb.write_misses 15848 # DTB write misses +system.cpu.dtb.read_hits 51397173 # DTB read hits +system.cpu.dtb.read_misses 63986 # DTB read misses +system.cpu.dtb.write_hits 11699533 # DTB write hits +system.cpu.dtb.write_misses 15890 # DTB write misses system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 6555 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2395 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 408 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 6549 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2402 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 405 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1336 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51465113 # DTB read accesses -system.cpu.dtb.write_accesses 11715952 # DTB write accesses +system.cpu.dtb.perms_faults 1410 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51461159 # DTB read accesses +system.cpu.dtb.write_accesses 11715423 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63100992 # DTB hits -system.cpu.dtb.misses 80073 # DTB misses -system.cpu.dtb.accesses 63181065 # DTB accesses -system.cpu.itb.inst_hits 12331220 # ITB inst hits -system.cpu.itb.inst_misses 11422 # ITB inst misses +system.cpu.dtb.hits 63096706 # DTB hits +system.cpu.dtb.misses 79876 # DTB misses +system.cpu.dtb.accesses 63176582 # DTB accesses +system.cpu.itb.inst_hits 12260245 # ITB inst hits +system.cpu.itb.inst_misses 11468 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -295,113 +777,113 @@ system.cpu.itb.flush_tlb 4 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 4954 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 4980 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2905 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2998 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 12342642 # ITB inst accesses -system.cpu.itb.hits 12331220 # DTB hits -system.cpu.itb.misses 11422 # DTB misses -system.cpu.itb.accesses 12342642 # DTB accesses -system.cpu.numCycles 471822965 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 12271713 # ITB inst accesses +system.cpu.itb.hits 12260245 # DTB hits +system.cpu.itb.misses 11468 # DTB misses +system.cpu.itb.accesses 12271713 # DTB accesses +system.cpu.numCycles 475189978 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 30573370 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 96017663 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14672817 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9344679 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21160566 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5295047 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 124247 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 93127049 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2641 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 86502 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 2607471 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 357 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 12327822 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 900542 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5477 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 151317698 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.785150 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.150169 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 30497823 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 96057374 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14673159 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9344923 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21151922 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5296118 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 123395 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 94706901 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2678 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 86562 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 2683934 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 445 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 12256747 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 864492 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5531 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 152887644 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.777320 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.141699 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 130172761 86.03% 86.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1303441 0.86% 86.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1712324 1.13% 88.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2496425 1.65% 89.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2221306 1.47% 91.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1109073 0.73% 91.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2756927 1.82% 93.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 745885 0.49% 94.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8799556 5.82% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 131751310 86.18% 86.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1303513 0.85% 87.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1714679 1.12% 88.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2493622 1.63% 89.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2205066 1.44% 91.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1108856 0.73% 91.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2738323 1.79% 93.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 743817 0.49% 94.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8828458 5.77% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 151317698 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.031098 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.203504 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32529947 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 95168576 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19190992 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 961902 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3466281 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1957763 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 171745 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 112647177 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 568207 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3466281 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 34471547 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36699353 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52502253 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18154395 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6023869 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 106113727 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 20537 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 985646 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4066140 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 795 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 110515015 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 485506390 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 485415520 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 90870 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78390038 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 32124976 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 830416 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 736951 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12148327 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 20331207 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13516553 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1968455 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2470685 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 97921870 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1983479 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 124325634 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 167955 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 21739212 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 56995294 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 501084 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 151317698 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.821620 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.535306 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 152887644 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.030879 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.202145 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32458089 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 96821111 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19172249 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 971461 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3464734 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1958214 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 171741 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 112504503 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 568893 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3464734 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 34365136 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 38157390 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52654113 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18177530 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6068741 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 106257538 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 20628 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1016430 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4078403 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 665 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 110740396 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 486151881 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 486061534 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 90347 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78390288 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 32350107 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 830682 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 737164 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12219946 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 20282216 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13494315 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1963339 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2435947 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 97859231 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1984036 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 124319403 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 165680 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 21668523 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 56420296 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 501641 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 152887644 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.813142 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.528360 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 107101494 70.78% 70.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13519014 8.93% 79.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7070833 4.67% 84.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5935604 3.92% 88.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12601558 8.33% 96.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2800079 1.85% 98.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1698500 1.12% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 464413 0.31% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 126203 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 108584137 71.02% 71.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13613798 8.90% 79.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7066944 4.62% 84.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5988746 3.92% 88.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12566780 8.22% 96.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2768589 1.81% 98.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1723460 1.13% 99.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 446866 0.29% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 128324 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 151317698 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 152887644 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 62151 0.70% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 62053 0.70% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 3 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available @@ -430,383 +912,416 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8366348 94.60% 95.30% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 415303 4.70% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8365072 94.62% 95.32% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 413828 4.68% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58625951 47.16% 47.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93085 0.07% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 24 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 16 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 16 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52921154 42.57% 90.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12319608 9.91% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58665929 47.19% 47.48% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93120 0.07% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 16 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 1 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 11 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 11 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52876194 42.53% 90.09% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12318342 9.91% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 124325634 # Type of FU issued -system.cpu.iq.rate 0.263501 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8843805 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071134 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 409037091 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 121660776 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85961644 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23336 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12538 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10309 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 132793364 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12409 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 623444 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 124319403 # Type of FU issued +system.cpu.iq.rate 0.261620 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8840956 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071115 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 410589228 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 121528348 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 86069861 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23359 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12446 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10285 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 132784241 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12452 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 624311 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4676644 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6237 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 29883 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1784459 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4627641 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6443 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30069 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1762200 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107775 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 892558 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107875 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 918337 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3466281 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 27944782 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 433344 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100126481 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 202692 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 20331207 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13516553 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1410337 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 113091 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3418 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 29883 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 350144 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 269265 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 619409 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 121539796 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52087723 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2785838 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3464734 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 29357042 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 436051 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100064926 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 205472 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 20282216 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13494315 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1410818 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 114442 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3537 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30069 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 350642 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 268888 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 619530 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 121646726 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52084248 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2672677 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 221132 # number of nop insts executed -system.cpu.iew.exec_refs 64299655 # number of memory reference insts executed -system.cpu.iew.exec_branches 11557425 # Number of branches executed -system.cpu.iew.exec_stores 12211932 # Number of stores executed -system.cpu.iew.exec_rate 0.257596 # Inst execution rate -system.cpu.iew.wb_sent 120381824 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85971953 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47248258 # num instructions producing a value -system.cpu.iew.wb_consumers 88196266 # num instructions consuming a value +system.cpu.iew.exec_nop 221659 # number of nop insts executed +system.cpu.iew.exec_refs 64295158 # number of memory reference insts executed +system.cpu.iew.exec_branches 11560329 # Number of branches executed +system.cpu.iew.exec_stores 12210910 # Number of stores executed +system.cpu.iew.exec_rate 0.255996 # Inst execution rate +system.cpu.iew.wb_sent 120490085 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 86080146 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47268053 # num instructions producing a value +system.cpu.iew.wb_consumers 88199499 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.182212 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.535717 # average fanout of values written-back +system.cpu.iew.wb_rate 0.181149 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.535922 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 21471534 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 21408137 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1482395 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 535206 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 147851417 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.525864 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.516226 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 535479 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 149422910 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.520334 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.507055 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 120424253 81.45% 81.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13319272 9.01% 90.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3880838 2.62% 93.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2123082 1.44% 94.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1929256 1.30% 95.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 967576 0.65% 96.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1605493 1.09% 97.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 701565 0.47% 98.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2900082 1.96% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 121949451 81.61% 81.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13299405 8.90% 90.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3946740 2.64% 93.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2141050 1.43% 94.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1955041 1.31% 95.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 959721 0.64% 96.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1537792 1.03% 97.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 781343 0.52% 98.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2852367 1.91% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 147851417 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60458107 # Number of instructions committed -system.cpu.commit.committedOps 77749667 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 149422910 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60458274 # Number of instructions committed +system.cpu.commit.committedOps 77749893 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27386657 # Number of memory references committed -system.cpu.commit.loads 15654563 # Number of loads committed -system.cpu.commit.membars 403601 # Number of memory barriers committed -system.cpu.commit.branches 9961339 # Number of branches committed +system.cpu.commit.refs 27386690 # Number of memory references committed +system.cpu.commit.loads 15654575 # Number of loads committed +system.cpu.commit.membars 403596 # Number of memory barriers committed +system.cpu.commit.branches 9961373 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68854898 # Number of committed integer instructions. -system.cpu.commit.function_calls 991261 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2900082 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 68855105 # Number of committed integer instructions. +system.cpu.commit.function_calls 991268 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2852367 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 242323943 # The number of ROB reads -system.cpu.rob.rob_writes 202004834 # The number of ROB writes -system.cpu.timesIdled 1771447 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 320505267 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4594325554 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60307726 # Number of Instructions Simulated -system.cpu.committedOps 77599286 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60307726 # Number of Instructions Simulated -system.cpu.cpi 7.823591 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.823591 # CPI: Total CPI of All Threads -system.cpu.ipc 0.127819 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.127819 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 550297303 # number of integer regfile reads -system.cpu.int_regfile_writes 88455601 # number of integer regfile writes -system.cpu.fp_regfile_reads 8347 # number of floating regfile reads -system.cpu.fp_regfile_writes 2910 # number of floating regfile writes -system.cpu.misc_regfile_reads 30123534 # number of misc regfile reads -system.cpu.misc_regfile_writes 831893 # number of misc regfile writes -system.cpu.icache.replacements 979954 # number of replacements -system.cpu.icache.tagsinuse 511.616585 # Cycle average of tags in use -system.cpu.icache.total_refs 11267650 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 980466 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 11.492137 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 6410377000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.616585 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.999251 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.999251 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 11267650 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11267650 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11267650 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11267650 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11267650 # number of overall hits -system.cpu.icache.overall_hits::total 11267650 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1060047 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1060047 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1060047 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1060047 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1060047 # number of overall misses -system.cpu.icache.overall_misses::total 1060047 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14006301995 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14006301995 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14006301995 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14006301995 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14006301995 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14006301995 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12327697 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12327697 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12327697 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12327697 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12327697 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12327697 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.085989 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.085989 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.085989 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.085989 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.085989 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.085989 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13212.906593 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13212.906593 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13212.906593 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13212.906593 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13212.906593 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13212.906593 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 5383 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 802 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 290 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 18.562069 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 802 # average number of cycles each access was blocked +system.cpu.rob.rob_reads 243879966 # The number of ROB reads +system.cpu.rob.rob_writes 201882555 # The number of ROB writes +system.cpu.timesIdled 1780421 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 322302334 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4593285278 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60307893 # Number of Instructions Simulated +system.cpu.committedOps 77599512 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60307893 # Number of Instructions Simulated +system.cpu.cpi 7.879399 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.879399 # CPI: Total CPI of All Threads +system.cpu.ipc 0.126913 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.126913 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 550704703 # number of integer regfile reads +system.cpu.int_regfile_writes 88578313 # number of integer regfile writes +system.cpu.fp_regfile_reads 8302 # number of floating regfile reads +system.cpu.fp_regfile_writes 2882 # number of floating regfile writes +system.cpu.misc_regfile_reads 30116391 # number of misc regfile reads +system.cpu.misc_regfile_writes 831896 # number of misc regfile writes +system.cpu.toL2Bus.throughput 58661050 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2657246 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2657245 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 763336 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 763336 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 607669 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2958 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 15 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2973 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 246055 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 246055 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1960500 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 5796171 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma 30982 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma 126318 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 7913971 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 62698816 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 85512245 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma 42284 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma 208804 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 148462149 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 148462149 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 201328 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3128322117 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1471549889 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 2533210636 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer2.occupancy 20419483 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer3.occupancy 74237753 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.cpu.icache.replacements 980157 # number of replacements +system.cpu.icache.tagsinuse 511.579914 # Cycle average of tags in use +system.cpu.icache.total_refs 11196212 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 980669 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 11.416912 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 6837358000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 511.579914 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.999180 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.999180 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 11196212 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11196212 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11196212 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11196212 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11196212 # number of overall hits +system.cpu.icache.overall_hits::total 11196212 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1060409 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1060409 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1060409 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1060409 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1060409 # number of overall misses +system.cpu.icache.overall_misses::total 1060409 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14257699991 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14257699991 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14257699991 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14257699991 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14257699991 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14257699991 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 12256621 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12256621 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12256621 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12256621 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12256621 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12256621 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.086517 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.086517 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.086517 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.086517 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.086517 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.086517 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13445.472446 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13445.472446 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13445.472446 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13445.472446 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13445.472446 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13445.472446 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 6872 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 372 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 18.473118 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # 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mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986500 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.176471 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.176471 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541220 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541220 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000782 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000190 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012581 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223367 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.092632 # 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average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7387753007 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7387753007 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 3481250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 105750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 755022750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8056699254 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 8815309004 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 3481250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 105750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 755022750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8056699254 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 8815309004 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 7078250 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166940694000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166947772250 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 26398880620 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 26398880620 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 7078250 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 193339574620 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 193346652870 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000862 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000189 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012591 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026822 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016006 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.984449 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.984449 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.200000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.200000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541265 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541265 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000862 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000189 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012591 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223418 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.092654 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000862 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000189 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012591 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223418 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.092654 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 77361.111111 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 52875 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61214.751905 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62694.118744 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61930.328272 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001.343407 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.343407 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38253.282311 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38253.282311 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 59537.585366 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 46625.500000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43967.943105 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38854.369098 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39263.244027 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 59537.585366 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 46625.500000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43967.943105 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38854.369098 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39263.244027 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55471.523768 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55471.523768 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 77361.111111 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 52875 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61214.751905 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56007.252324 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56424.477725 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 77361.111111 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 52875 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61214.751905 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56007.252324 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56424.477725 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -927,161 +1442,161 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # 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number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13758946 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7259114 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7259114 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 242919 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 242919 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247600 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 247600 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21018060 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21018060 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21018060 # number of overall hits -system.cpu.dcache.overall_hits::total 21018060 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 736156 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 736156 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2963249 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2963249 # number of WriteReq misses +system.cpu.dcache.replacements 643353 # number of replacements +system.cpu.dcache.tagsinuse 511.992092 # Cycle average of tags in use +system.cpu.dcache.total_refs 21505591 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 643865 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 33.400777 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 48193000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.992092 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999985 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999985 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 13753583 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13753583 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7258444 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7258444 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 242854 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 242854 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247602 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247602 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21012027 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21012027 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21012027 # number of overall hits +system.cpu.dcache.overall_hits::total 21012027 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 737498 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 737498 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2963942 # 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number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10222363 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10222363 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256458 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 256458 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_misses::cpu.data 15 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 15 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3701440 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3701440 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3701440 # number of overall misses +system.cpu.dcache.overall_misses::total 3701440 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10068067500 # 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number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14491081 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14491081 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10222386 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10222386 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256393 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 256393 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 247617 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 247617 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24717465 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24717465 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24717465 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24717465 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050787 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.050787 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289879 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.289879 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052792 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052792 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000069 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000069 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.149668 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.149668 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.149668 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.149668 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13229.919338 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13229.919338 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35337.426328 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35337.426328 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13413.213679 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13413.213679 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15117.647059 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15117.647059 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30938.185392 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30938.185392 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30938.185392 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30938.185392 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 30435 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 19416 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2583 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 249 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.782811 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 77.975904 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 24713467 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24713467 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24713467 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24713467 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050893 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.050893 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289946 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.289946 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052806 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052806 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000061 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000061 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.149774 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.149774 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.149774 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.149774 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13651.653971 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13651.653971 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44736.245086 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 44736.245086 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13575.670286 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13575.670286 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15400 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15400 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 38542.757206 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 38542.757206 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 38542.757206 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 38542.757206 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 32274 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 26462 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2637 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 287 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.238908 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 92.202091 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 607758 # number of writebacks -system.cpu.dcache.writebacks::total 607758 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 350427 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 350427 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714248 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2714248 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1344 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1344 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3064675 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3064675 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3064675 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3064675 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385729 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 385729 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249001 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 249001 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12195 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12195 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 17 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 17 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 634730 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 634730 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 634730 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 634730 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4803158500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4803158500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8205851415 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8205851415 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 142277500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 142277500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 223000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 223000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13009009915 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13009009915 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13009009915 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13009009915 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182395749000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182395749000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 36727240405 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 36727240405 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 219122989405 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 219122989405 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026611 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026611 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024358 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024358 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047552 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047552 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000069 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000069 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025679 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025679 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025679 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025679 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12452.158121 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12452.158121 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32955.094216 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32955.094216 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11666.871669 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11666.871669 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13117.647059 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13117.647059 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20495.344343 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20495.344343 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20495.344343 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20495.344343 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 607669 # number of writebacks +system.cpu.dcache.writebacks::total 607669 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351798 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 351798 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2715004 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2715004 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1354 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1354 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3066802 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3066802 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3066802 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3066802 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385700 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385700 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248938 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 248938 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12185 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12185 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 15 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 15 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 634638 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634638 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634638 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634638 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4965601859 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4965601859 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10500826931 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10500826931 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 144262002 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 144262002 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 201000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 201000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15466428790 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 15466428790 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15466428790 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15466428790 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182333907000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182333907000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 35770060494 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 35770060494 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 218103967494 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 218103967494 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026616 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026616 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024352 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024352 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047525 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047525 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000061 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000061 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025680 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025680 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025680 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025680 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12874.259422 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12874.259422 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42182.498980 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42182.498980 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11839.310792 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11839.310792 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13400 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13400 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24370.473861 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24370.473861 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24370.473861 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24370.473861 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1103,16 +1618,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229569916889 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1229569916889 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229569916889 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1229569916889 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1488848485257 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1488848485257 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1488848485257 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1488848485257 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83043 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 83044 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 960d43f01..7f7f9360b 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,149 +1,149 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.102954 # Number of seconds simulated -sim_ticks 1102954033500 # Number of ticks simulated -final_tick 1102954033500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.613797 # Number of seconds simulated +sim_ticks 2613796876500 # Number of ticks simulated +final_tick 2613796876500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 66183 # Simulator instruction rate (inst/s) -host_op_rate 85190 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1185337549 # Simulator tick rate (ticks/s) -host_mem_usage 402972 # Number of bytes of host memory used -host_seconds 930.50 # Real time elapsed on the host -sim_insts 61582952 # Number of instructions simulated -sim_ops 79269552 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::realview.clcd 48758784 # Number of bytes read from this memory +host_inst_rate 54493 # Simulator instruction rate (inst/s) +host_op_rate 70162 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2268463215 # Simulator tick rate (ticks/s) +host_mem_usage 404628 # Number of bytes of host memory used +host_seconds 1152.23 # Real time elapsed on the host +sim_insts 62788171 # Number of instructions simulated +sim_ops 80843130 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 410112 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4380532 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 1024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 404608 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5226032 # Number of bytes read from this memory -system.physmem.bytes_read::total 59181988 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 410112 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 404608 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 814720 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4260416 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 395008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4352820 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 1152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 426432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5278640 # Number of bytes read from this memory +system.physmem.bytes_read::total 131565412 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 395008 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 426432 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 821440 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4275200 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7287760 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 6094848 # Number of read requests responded to by this memory +system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory +system.physmem.bytes_written::total 7304336 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 11 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6408 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 68518 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 16 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6322 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 81683 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6257809 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66569 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6172 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 68085 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 18 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6663 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 82505 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15302272 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66800 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 823405 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 44207449 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 638 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 174 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 371831 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3971636 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 928 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 366840 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4738214 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 53657710 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 371831 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 366840 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 738671 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3862732 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 15413 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2729347 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6607492 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3862732 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 44207449 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 638 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 174 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 371831 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3987049 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 928 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 366840 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 7467561 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 60265202 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 6257809 # Total number of read requests seen -system.physmem.writeReqs 823405 # Total number of write requests seen -system.physmem.cpureqs 242034 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 400499776 # Total number of bytes read from memory -system.physmem.bytesWritten 52697920 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 59181988 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7287760 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 69 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 12609 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 391396 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 391210 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 390867 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 391605 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 391533 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 390879 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 390924 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 391633 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 391393 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 390703 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 390862 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 391239 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 391232 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 390529 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 390469 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 391266 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 51407 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 51229 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 51010 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51679 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 51546 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50964 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50973 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51667 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 52037 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51352 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 51503 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51884 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51844 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51249 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51170 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51891 # Track writes on a per bank basis +system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory +system.physmem.num_writes::total 824084 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 46335096 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 269 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 151124 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1665325 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 441 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 163147 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 2019530 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50334979 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 151124 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 163147 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314271 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1635628 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6504 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 1152399 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2794531 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1635628 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 46335096 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 269 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 151124 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1671828 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 441 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 163147 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 3171928 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53129510 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15302272 # Total number of read requests seen +system.physmem.writeReqs 824084 # Total number of write requests seen +system.physmem.cpureqs 244248 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 979345408 # Total number of bytes read from memory +system.physmem.bytesWritten 52741376 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 131565412 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7304336 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 446 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 14097 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 956408 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 956129 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 956336 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 956715 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 957144 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 956669 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 956165 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 955908 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 956711 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 956880 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 955935 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 955453 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 956251 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 956326 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 956540 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 956256 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 49946 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 49763 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 51937 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 52171 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 52441 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 51960 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 51720 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51713 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51876 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 52086 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 51258 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 50919 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51540 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 51490 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51756 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51508 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 32620 # Number of times wr buffer was full causing retry -system.physmem.totGap 1102952897500 # Total gap between requests +system.physmem.numWrRetry 32582 # Number of times wr buffer was full causing retry +system.physmem.totGap 2613795718500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 105 # Categorize read packet sizes -system.physmem.readPktSize::3 6094848 # Categorize read packet sizes +system.physmem.readPktSize::3 15138816 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 162856 # Categorize read packet sizes +system.physmem.readPktSize::6 163351 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 756836 # Categorize write packet sizes +system.physmem.writePktSize::2 757284 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 66569 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 493795 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 430407 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 391611 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1441549 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1086056 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1098465 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1064627 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 26919 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 24797 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 44432 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 63777 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 44227 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 12032 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 11790 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 15214 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 7879 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 148 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 10 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66800 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1071823 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1000587 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1004460 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3729147 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2791599 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2788638 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2744704 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 17899 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 15634 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 28056 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 40361 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 27838 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 10343 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 10275 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 13794 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 6509 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 126 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 19 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -156,59 +156,350 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2891 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2958 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3001 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3064 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3088 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32910 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32843 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32757 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 32712 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 32687 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 32659 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 32633 # What write queue length does an incoming req see -system.physmem.totQLat 199184958750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 239005190000 # Sum of mem lat for all requests -system.physmem.totBusLat 31288700000 # Total cycles spent in databus access -system.physmem.totBankLat 8531531250 # Total cycles spent in bank access -system.physmem.avgQLat 31830.17 # Average queueing delay per request -system.physmem.avgBankLat 1363.36 # Average bank access latency per request +system.physmem.wrQLenPdf::0 2919 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2991 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3038 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3211 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 3225 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35829 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35829 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35829 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35829 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35829 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35829 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32911 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32839 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32724 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32698 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32677 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 32644 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 32619 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 32605 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 48021 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 21491.760022 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 1412.636943 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 31347.507834 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-95 10706 22.29% 22.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-159 4255 8.86% 31.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-223 2654 5.53% 36.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-287 2034 4.24% 40.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-351 1364 2.84% 43.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-415 1232 2.57% 46.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-479 971 2.02% 48.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-543 916 1.91% 50.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-607 629 1.31% 51.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-671 621 1.29% 52.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-735 497 1.03% 53.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-799 447 0.93% 54.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-863 308 0.64% 55.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-927 288 0.60% 56.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-991 206 0.43% 56.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1055 291 0.61% 57.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1119 124 0.26% 57.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1183 166 0.35% 57.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1247 102 0.21% 57.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1311 142 0.30% 58.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1375 76 0.16% 58.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1439 430 0.90% 59.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1503 2116 4.41% 63.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1567 511 1.06% 64.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1631 96 0.20% 64.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1695 187 0.39% 65.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1759 61 0.13% 65.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1823 129 0.27% 65.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1887 42 0.09% 65.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1951 82 0.17% 65.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-2015 32 0.07% 66.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2079 81 0.17% 66.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2143 30 0.06% 66.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2207 40 0.08% 66.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2271 20 0.04% 66.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2335 38 0.08% 66.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2399 8 0.02% 66.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2463 24 0.05% 66.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2527 13 0.03% 66.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2591 21 0.04% 66.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2655 4 0.01% 66.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2719 15 0.03% 66.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2783 7 0.01% 66.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2847 25 0.05% 66.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2911 10 0.02% 66.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2975 14 0.03% 66.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3039 5 0.01% 66.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3103 16 0.03% 66.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3167 3 0.01% 66.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3231 10 0.02% 66.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3295 6 0.01% 66.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3359 12 0.02% 66.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3423 3 0.01% 66.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3487 12 0.02% 66.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3551 7 0.01% 66.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3615 8 0.02% 66.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3679 5 0.01% 66.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3743 6 0.01% 66.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3807 4 0.01% 66.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3871 10 0.02% 67.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3935 8 0.02% 67.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3999 9 0.02% 67.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4063 7 0.01% 67.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4127 36 0.07% 67.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4191 3 0.01% 67.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4255 8 0.02% 67.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4319 3 0.01% 67.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4383 8 0.02% 67.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4447 1 0.00% 67.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4511 7 0.01% 67.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4575 4 0.01% 67.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4703 1 0.00% 67.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4767 1 0.00% 67.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4831 5 0.01% 67.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4895 4 0.01% 67.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4959 2 0.00% 67.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-5023 3 0.01% 67.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5087 3 0.01% 67.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5151 10 0.02% 67.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5215 3 0.01% 67.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5279 3 0.01% 67.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5343 2 0.00% 67.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5407 1 0.00% 67.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5471 1 0.00% 67.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5535 2 0.00% 67.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5599 3 0.01% 67.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5663 4 0.01% 67.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5791 2 0.00% 67.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5919 5 0.01% 67.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5983 2 0.00% 67.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6047 1 0.00% 67.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6111 1 0.00% 67.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6175 7 0.01% 67.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6239 1 0.00% 67.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6303 4 0.01% 67.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6367 2 0.00% 67.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6431 2 0.00% 67.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6495 1 0.00% 67.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6559 3 0.01% 67.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6687 1 0.00% 67.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6751 2 0.00% 67.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6815 13 0.03% 67.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6879 2 0.00% 67.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6943 6 0.01% 67.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-7007 1 0.00% 67.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7071 3 0.01% 67.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7199 5 0.01% 67.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7263 3 0.01% 67.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7455 2 0.00% 67.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7583 6 0.01% 67.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7647 1 0.00% 67.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7711 4 0.01% 67.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7775 1 0.00% 67.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7839 4 0.01% 67.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7903 3 0.01% 67.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7967 6 0.01% 67.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8031 1 0.00% 67.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8095 6 0.01% 67.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8159 4 0.01% 67.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8223 320 0.67% 68.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8479 2 0.00% 68.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8735 3 0.01% 68.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8991 2 0.00% 68.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9408-9439 1 0.00% 68.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9503 3 0.01% 68.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9759 1 0.00% 68.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9920-9951 1 0.00% 68.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10271 16 0.03% 68.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10432-10463 1 0.00% 68.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10783 1 0.00% 68.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11295 4 0.01% 68.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11328-11359 1 0.00% 68.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11551 1 0.00% 68.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11807 1 0.00% 68.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12319 1 0.00% 68.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12575 1 0.00% 68.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12864-12895 1 0.00% 68.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12928-12959 1 0.00% 68.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13087 1 0.00% 68.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13343 2 0.00% 68.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13855 1 0.00% 68.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14111 1 0.00% 68.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14367 1 0.00% 68.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14623 2 0.00% 68.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14879 2 0.00% 68.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15199 1 0.00% 68.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15391 2 0.00% 68.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15424-15455 1 0.00% 68.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16159 2 0.00% 68.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16415 2 0.00% 68.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16671 1 0.00% 68.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16896-16927 2 0.00% 68.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17183 1 0.00% 68.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17216-17247 1 0.00% 68.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17439 1 0.00% 68.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17792-17823 1 0.00% 68.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17856-17887 1 0.00% 68.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17951 1 0.00% 68.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18463 1 0.00% 68.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18688-18719 1 0.00% 68.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19072-19103 1 0.00% 68.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19231 1 0.00% 68.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19487 3 0.01% 68.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19968-19999 1 0.00% 68.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20224-20255 1 0.00% 68.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20511 15 0.03% 68.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20608-20639 1 0.00% 68.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21535 4 0.01% 68.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22272-22303 2 0.00% 68.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22559 1 0.00% 68.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22784-22815 3 0.01% 68.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23040-23071 3 0.01% 68.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23360-23391 1 0.00% 68.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23583 3 0.01% 68.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23872-23903 1 0.00% 68.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24064-24095 2 0.00% 68.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24351 1 0.00% 68.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24607 3 0.01% 68.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24832-24863 2 0.00% 68.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25088-25119 1 0.00% 68.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25631 2 0.00% 68.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25856-25887 1 0.00% 68.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25920-25951 1 0.00% 68.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26112-26143 2 0.00% 68.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26399 2 0.00% 68.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26655 2 0.00% 68.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27136-27167 1 0.00% 68.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27423 2 0.00% 68.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27584-27615 1 0.00% 68.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27679 3 0.01% 68.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27935 1 0.00% 68.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28160-28191 1 0.00% 68.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28447 1 0.00% 68.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28703 2 0.00% 68.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28959 4 0.01% 68.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29215 1 0.00% 68.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29471 2 0.00% 68.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-29983 1 0.00% 68.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30239 2 0.00% 68.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30751 7 0.01% 68.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31263 1 0.00% 68.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31519 1 0.00% 68.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31775 3 0.01% 68.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32287 1 0.00% 68.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32543 3 0.01% 68.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33055 3 0.01% 68.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33311 2 0.00% 68.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33728-33759 1 0.00% 68.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33823 55 0.11% 68.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33984-34015 1 0.00% 68.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34048-34079 1 0.00% 68.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34847 2 0.00% 68.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35328-35359 1 0.00% 68.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35871 1 0.00% 68.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35968-35999 1 0.00% 68.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36096-36127 2 0.00% 68.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36480-36511 1 0.00% 68.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36608-36639 1 0.00% 68.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38175 1 0.00% 68.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39168-39199 1 0.00% 68.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39232-39263 1 0.00% 68.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39616-39647 1 0.00% 68.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40384-40415 1 0.00% 68.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41247 2 0.00% 68.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-42015 2 0.00% 68.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42240-42271 1 0.00% 68.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42688-42719 1 0.00% 68.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42783 1 0.00% 68.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43039 1 0.00% 68.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44063 3 0.01% 68.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44416-44447 1 0.00% 68.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44672-44703 1 0.00% 68.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46623 1 0.00% 68.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46912-46943 1 0.00% 68.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46976-47007 1 0.00% 68.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48671 1 0.00% 68.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48927 1 0.00% 68.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49408-49439 2 0.00% 68.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50688-50719 1 0.00% 68.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50880-50911 1 0.00% 68.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51200-51231 2 0.00% 68.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::52224-52255 2 0.00% 68.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::52608-52639 1 0.00% 68.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::53248-53279 1 0.00% 68.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::54784-54815 1 0.00% 68.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::55296-55327 1 0.00% 68.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::55616-55647 1 0.00% 68.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::56064-56095 1 0.00% 68.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::56832-56863 1 0.00% 68.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::57088-57119 2 0.00% 68.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::58112-58143 1 0.00% 68.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::59584-59615 1 0.00% 68.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::59648-59679 1 0.00% 68.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::59840-59871 1 0.00% 68.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::60416-60447 1 0.00% 68.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::61184-61215 1 0.00% 68.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::61568-61599 1 0.00% 68.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::61952-61983 1 0.00% 68.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::62976-63007 1 0.00% 68.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::63488-63519 1 0.00% 68.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::64064-64095 1 0.00% 68.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::64512-64543 1 0.00% 68.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65024-65055 25 0.05% 68.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65088-65119 6 0.01% 68.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65152-65183 7 0.01% 68.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65280-65311 19 0.04% 68.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65408-65439 7 0.01% 68.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65472-65503 18 0.04% 68.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65536-65567 14562 30.32% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::97536-97567 1 0.00% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::103680-103711 1 0.00% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::129664-129695 1 0.00% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::130176-130207 1 0.00% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::130624-130655 1 0.00% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::130688-130719 1 0.00% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::131072-131103 321 0.67% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::131200-131231 1 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::131328-131359 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::132096-132127 2 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::136576-136607 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::140032-140063 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::160768-160799 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::162560-162591 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::169728-169759 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::182528-182559 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::196608-196639 8 0.02% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 48021 # Bytes accessed per row activation +system.physmem.totQLat 359781455750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 452374882000 # Sum of mem lat for all requests +system.physmem.totBusLat 76509130000 # Total cycles spent in databus access +system.physmem.totBankLat 16084296250 # Total cycles spent in bank access +system.physmem.avgQLat 23512.32 # Average queueing delay per request +system.physmem.avgBankLat 1051.14 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 38193.53 # Average memory access latency -system.physmem.avgRdBW 363.12 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 47.78 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 53.66 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 6.61 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 29563.46 # Average memory access latency +system.physmem.avgRdBW 374.68 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 20.18 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 50.33 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 2.79 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.21 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.22 # Average read queue length over time -system.physmem.avgWrQLen 10.07 # Average write queue length over time -system.physmem.readRowHits 6213915 # Number of row buffer hits during reads -system.physmem.writeRowHits 799980 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.30 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 97.16 # Row buffer hit rate for writes -system.physmem.avgGap 155757.60 # Average gap between requests +system.physmem.busUtil 3.08 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.17 # Average read queue length over time +system.physmem.avgWrQLen 13.40 # Average write queue length over time +system.physmem.readRowHits 15272830 # Number of row buffer hits during reads +system.physmem.writeRowHits 805042 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.81 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 97.69 # Row buffer hit rate for writes +system.physmem.avgGap 162082.23 # Average gap between requests system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory @@ -218,246 +509,307 @@ system.realview.nvmem.bytes_inst_read::total 448 system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 58 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 348 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 406 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 58 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 348 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 406 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 58 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 348 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 406 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 72561 # number of replacements -system.l2c.tagsinuse 53740.730134 # Cycle average of tags in use -system.l2c.total_refs 1839807 # Total number of references to valid blocks. -system.l2c.sampled_refs 137757 # Sample count of references to valid blocks. -system.l2c.avg_refs 13.355452 # Average number of references to valid blocks. +system.realview.nvmem.bw_read::cpu0.inst 24 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 147 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 171 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 24 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 147 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 171 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 24 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 147 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 171 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 54057191 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16352590 # Transaction distribution +system.membus.trans_dist::ReadResp 16352590 # Transaction distribution +system.membus.trans_dist::WriteReq 769166 # Transaction distribution +system.membus.trans_dist::WriteResp 769166 # Transaction distribution +system.membus.trans_dist::Writeback 66800 # Transaction distribution +system.membus.trans_dist::UpgradeReq 35679 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 18283 # Transaction distribution +system.membus.trans_dist::UpgradeResp 14097 # Transaction distribution +system.membus.trans_dist::ReadExReq 138270 # Transaction distribution +system.membus.trans_dist::ReadExResp 137887 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384276 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1976722 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13830 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 2050 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4376896 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.bridge.slave 2384276 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 32254354 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.realview.gic.pio 13830 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.realview.local_cpu_timer.pio 2050 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 34654528 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2392552 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17759220 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 27660 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 4100 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 20183988 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.bridge.slave 2392552 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 138869748 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.realview.gic.pio 27660 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.realview.local_cpu_timer.pio 4100 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 141294516 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 141294516 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 1493240500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 17657749750 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.7 # Layer utilization (%) +system.membus.reqLayer3.occupancy 11792000 # Layer occupancy (ticks) +system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer5.occupancy 3000 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer6.occupancy 1805500 # Layer occupancy (ticks) +system.membus.reqLayer6.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 4833822840 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.respLayer2.occupancy 34180950731 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 1.3 # Layer utilization (%) +system.l2c.replacements 73069 # number of replacements +system.l2c.tagsinuse 53059.477869 # Cycle average of tags in use +system.l2c.total_refs 1873536 # Total number of references to valid blocks. +system.l2c.sampled_refs 138222 # Sample count of references to valid blocks. +system.l2c.avg_refs 13.554543 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 39373.368087 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 3.826392 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.258184 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4017.777159 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 2831.337785 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 9.908379 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 3708.426786 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 3795.827361 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.600790 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000058 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.061306 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.043203 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000151 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.056586 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.057920 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.820018 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 21639 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4056 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 386080 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 166672 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 30823 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 4930 # 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mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.774536 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.784562 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.566494 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.568074 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.567362 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000478 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000432 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015141 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.245126 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000550 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010776 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.243045 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.097105 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000478 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000432 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015141 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.245126 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000550 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010776 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.243045 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.097105 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 68750 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60710.915551 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61102.112440 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 72805.555556 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 64546.768836 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 66724.991783 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 63327.411493 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10028.099965 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10029.024613 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10028.503682 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10047.908740 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10031.811644 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10041.006608 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 54663.358211 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58809.379683 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 56945.687406 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 68750 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60710.915551 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 55244.578629 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 72805.555556 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 64546.768836 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 59407.747799 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 57919.172045 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 68750 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60710.915551 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 55244.578629 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 72805.555556 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 64546.768836 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 59407.747799 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 57919.172045 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -648,38 +1000,247 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 5994746 # Number of BP lookups -system.cpu0.branchPred.condPredicted 4572445 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 294986 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 3765254 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 2911375 # Number of BTB hits +system.toL2Bus.throughput 58542991 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2739841 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2739840 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 769166 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 769166 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 583280 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 34832 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 18657 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 53489 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 259511 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 259511 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 800088 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 1073172 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma 13793 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma 57051 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 1229933 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 4820895 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma 15468 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma 74350 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count 8084750 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 25585472 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 34695904 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma 18508 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma 92124 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 39339008 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 48266196 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma 22912 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma 131012 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size 148151136 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 148151136 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 4868352 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4921338984 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 1802175919 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 1506283904 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 9191448 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 34164696 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 2769642515 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer5.occupancy 3249270250 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 9767440 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 41898883 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 0.0 # Layer utilization (%) +system.iobus.throughput 47250451 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16322888 # Transaction distribution +system.iobus.trans_dist::ReadResp 16322888 # Transaction distribution +system.iobus.trans_dist::WriteReq 8066 # Transaction distribution +system.iobus.trans_dist::WriteResp 8066 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30842 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8848 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1032 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 736 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2384276 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart.pio 30842 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.realview_io.pio 8848 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.timer1.pio 1032 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.kmi1.pio 736 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 32661908 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40560 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 17696 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2064 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 392 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2392552 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart.pio 40560 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.realview_io.pio 17696 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.timer1.pio 2064 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.kmi1.pio 392 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 123503080 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 123503080 # Total data (bytes) +system.iobus.reqLayer0.occupancy 21645000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 4430000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 522000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) +system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) +system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer6.occupancy 440000 # Layer occupancy (ticks) +system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) +system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) +system.iobus.respLayer0.occupancy 2376210000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) +system.iobus.respLayer1.occupancy 30277632000 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 1.2 # Layer utilization (%) +system.cpu0.branchPred.lookups 6073314 # Number of BP lookups +system.cpu0.branchPred.condPredicted 4627623 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 295826 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 3795187 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 2949225 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 77.322141 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 671631 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 28577 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 77.709610 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 683153 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 28183 # Number of incorrect RAS predictions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 8900432 # DTB read hits -system.cpu0.dtb.read_misses 28720 # DTB read misses -system.cpu0.dtb.write_hits 5136537 # DTB write hits -system.cpu0.dtb.write_misses 5640 # DTB write misses +system.cpu0.dtb.read_hits 8970256 # DTB read hits +system.cpu0.dtb.read_misses 29375 # DTB read misses +system.cpu0.dtb.write_hits 5214738 # DTB write hits +system.cpu0.dtb.write_misses 5731 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1815 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1027 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 311 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 1812 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1038 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 270 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 553 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 8929152 # DTB read accesses -system.cpu0.dtb.write_accesses 5142177 # DTB write accesses +system.cpu0.dtb.perms_faults 591 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 8999631 # DTB read accesses +system.cpu0.dtb.write_accesses 5220469 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14036969 # DTB hits -system.cpu0.dtb.misses 34360 # DTB misses -system.cpu0.dtb.accesses 14071329 # DTB accesses -system.cpu0.itb.inst_hits 4213831 # ITB inst hits -system.cpu0.itb.inst_misses 5055 # ITB inst misses +system.cpu0.dtb.hits 14184994 # DTB hits +system.cpu0.dtb.misses 35106 # DTB misses +system.cpu0.dtb.accesses 14220100 # DTB accesses +system.cpu0.itb.inst_hits 4276462 # ITB inst hits +system.cpu0.itb.inst_misses 5070 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -688,530 +1249,530 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1341 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1351 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1480 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1356 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 4218886 # ITB inst accesses -system.cpu0.itb.hits 4213831 # DTB hits -system.cpu0.itb.misses 5055 # DTB misses -system.cpu0.itb.accesses 4218886 # DTB accesses -system.cpu0.numCycles 67827180 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 4281532 # ITB inst accesses +system.cpu0.itb.hits 4276462 # DTB hits +system.cpu0.itb.misses 5070 # DTB misses +system.cpu0.itb.accesses 4281532 # DTB accesses +system.cpu0.numCycles 69613456 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 11769589 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 31997398 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 5994746 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3583006 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 7510057 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1450935 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 59891 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 19410639 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 4833 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 47194 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 1299057 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 233 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 4212263 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 157193 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2052 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 41143300 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.004817 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.385260 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 11926468 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 32461716 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 6073314 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3632378 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 7613392 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1460130 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 63151 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 20074417 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 5834 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 46093 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 1371911 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 309 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 4274981 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 157877 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2111 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 42149460 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.995068 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.376418 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 33640645 81.76% 81.76% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 563027 1.37% 83.13% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 816788 1.99% 85.12% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 677485 1.65% 86.76% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 772099 1.88% 88.64% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 558236 1.36% 90.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 667723 1.62% 91.62% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 351865 0.86% 92.48% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3095432 7.52% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 34543319 81.95% 81.95% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 572779 1.36% 83.31% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 825233 1.96% 85.27% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 684006 1.62% 86.89% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 778589 1.85% 88.74% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 565339 1.34% 90.08% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 679715 1.61% 91.70% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 356870 0.85% 92.54% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3143610 7.46% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 41143300 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.088383 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.471749 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 12271204 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 20567331 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 6814121 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 512354 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 978290 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 934838 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 64553 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 39983053 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 212073 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 978290 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 12839379 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 5742381 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 12712172 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 6708467 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 2162611 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 38883586 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 1814 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 436137 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1233923 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 17 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 39230664 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 175613245 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 175579140 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 34105 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 30916187 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 8314476 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 411042 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 370243 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5355635 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7643947 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5684540 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1124242 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1215247 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 36809311 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 895353 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 37222613 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 81088 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6285112 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 13160919 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 256794 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 41143300 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.904707 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.513127 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 42149460 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.087243 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.466314 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 12452855 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 21284567 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 6905227 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 522550 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 984261 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 948796 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 64785 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 40574738 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 212216 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 984261 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 13028707 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 5941224 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 13201317 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6800913 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 2193038 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 39456506 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 1875 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 442978 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1248488 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 66 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 39834265 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 178291734 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 178257443 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 34291 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 31450110 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 8384154 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 420012 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 376763 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5452877 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7762434 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5776236 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1132872 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1233884 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 37360552 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 904892 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 37716432 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 82271 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6323448 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 13282471 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 257104 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 42149460 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.894826 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.507768 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 26016757 63.23% 63.23% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 5731331 13.93% 77.16% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3155319 7.67% 84.83% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2471251 6.01% 90.84% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2103314 5.11% 95.95% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 932641 2.27% 98.22% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 493188 1.20% 99.42% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 184690 0.45% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 54809 0.13% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 26809075 63.60% 63.60% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5821539 13.81% 77.42% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3209963 7.62% 85.03% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2497911 5.93% 90.96% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2123670 5.04% 96.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 939017 2.23% 98.22% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 502938 1.19% 99.42% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 188935 0.45% 99.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 56412 0.13% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 41143300 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 42149460 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 26572 2.49% 2.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 453 0.04% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 841830 78.79% 81.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 199561 18.68% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 27471 2.55% 2.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 463 0.04% 2.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 839894 78.10% 80.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 207538 19.30% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 52149 0.14% 0.14% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 22321556 59.97% 60.11% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 46948 0.13% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 9 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 6 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 700 0.00% 60.24% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.24% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 60.24% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.24% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9357811 25.14% 85.38% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5443427 14.62% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 52344 0.14% 0.14% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 22648900 60.05% 60.19% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 47937 0.13% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 12 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 8 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 680 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9431477 25.01% 85.32% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5535066 14.68% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 37222613 # Type of FU issued -system.cpu0.iq.rate 0.548786 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1068416 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.028703 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 116763775 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 43997708 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 34321266 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 8390 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 4632 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 3861 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 38234480 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 4400 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 306660 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 37716432 # Type of FU issued +system.cpu0.iq.rate 0.541798 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1075366 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.028512 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 118766388 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 44596758 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 34851054 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 8389 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 4662 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 3872 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 38735073 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 4381 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 316422 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1372064 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2343 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13106 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 537968 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1379018 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2578 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 13049 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 541624 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2192754 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5299 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2149592 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 6129 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 978290 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 4120588 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 98455 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 37822346 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 84553 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7643947 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5684540 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 571228 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 39920 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 2911 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13106 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 150072 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 117309 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 267381 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 36846322 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9215739 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 376291 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 984261 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 4297602 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 105996 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 38383622 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 87186 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7762434 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5776236 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 577553 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 40750 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 2975 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 13049 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 150118 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 117853 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 267971 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 37335026 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9287293 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 381406 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 117682 # number of nop insts executed -system.cpu0.iew.exec_refs 14611771 # number of memory reference insts executed -system.cpu0.iew.exec_branches 4852307 # Number of branches executed -system.cpu0.iew.exec_stores 5396032 # Number of stores executed -system.cpu0.iew.exec_rate 0.543238 # Inst execution rate -system.cpu0.iew.wb_sent 36653422 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 34325127 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 18280728 # num instructions producing a value -system.cpu0.iew.wb_consumers 35164479 # num instructions consuming a value +system.cpu0.iew.exec_nop 118178 # number of nop insts executed +system.cpu0.iew.exec_refs 14774953 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4916788 # Number of branches executed +system.cpu0.iew.exec_stores 5487660 # Number of stores executed +system.cpu0.iew.exec_rate 0.536319 # Inst execution rate +system.cpu0.iew.wb_sent 37140556 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 34854926 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 18563816 # num instructions producing a value +system.cpu0.iew.wb_consumers 35689656 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.506067 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.519863 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.500692 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.520146 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6092264 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 638559 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 231469 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 40165010 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.778528 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.739872 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6130188 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 647788 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 232202 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 41165199 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.772263 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.733134 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 28490647 70.93% 70.93% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 5723698 14.25% 85.18% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1913208 4.76% 89.95% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 977623 2.43% 92.38% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 784001 1.95% 94.33% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 521196 1.30% 95.63% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 385694 0.96% 96.59% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 221095 0.55% 97.14% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1147848 2.86% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 29286812 71.14% 71.14% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 5810011 14.11% 85.26% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1968218 4.78% 90.04% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 996844 2.42% 92.46% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 804428 1.95% 94.42% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 515457 1.25% 95.67% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 392582 0.95% 96.62% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 223885 0.54% 97.17% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1166962 2.83% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 40165010 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 23670535 # Number of instructions committed -system.cpu0.commit.committedOps 31269580 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 41165199 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 24069809 # Number of instructions committed +system.cpu0.commit.committedOps 31790359 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 11418455 # Number of memory references committed -system.cpu0.commit.loads 6271883 # Number of loads committed -system.cpu0.commit.membars 229601 # Number of memory barriers committed -system.cpu0.commit.branches 4243632 # Number of branches committed +system.cpu0.commit.refs 11618028 # Number of memory references committed +system.cpu0.commit.loads 6383416 # Number of loads committed +system.cpu0.commit.membars 231880 # Number of memory barriers committed +system.cpu0.commit.branches 4307208 # Number of branches committed system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 27627385 # Number of committed integer instructions. -system.cpu0.commit.function_calls 489162 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1147848 # number cycles where commit BW limit reached +system.cpu0.commit.int_insts 28099612 # Number of committed integer instructions. +system.cpu0.commit.function_calls 498731 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1166962 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 75528065 # The number of ROB reads -system.cpu0.rob.rob_writes 75703855 # The number of ROB writes -system.cpu0.timesIdled 360661 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 26683880 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2138039181 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 23589793 # Number of Instructions Simulated -system.cpu0.committedOps 31188838 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 23589793 # Number of Instructions Simulated -system.cpu0.cpi 2.875277 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.875277 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.347793 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.347793 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 171736211 # number of integer regfile reads -system.cpu0.int_regfile_writes 34071636 # number of integer regfile writes -system.cpu0.fp_regfile_reads 3249 # number of floating regfile reads -system.cpu0.fp_regfile_writes 898 # number of floating regfile writes -system.cpu0.misc_regfile_reads 12999243 # number of misc regfile reads -system.cpu0.misc_regfile_writes 450984 # number of misc regfile writes -system.cpu0.icache.replacements 392403 # number of replacements -system.cpu0.icache.tagsinuse 511.011252 # Cycle average of tags in use -system.cpu0.icache.total_refs 3789022 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 392915 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 9.643363 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 6567370000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 511.011252 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.998069 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.998069 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 3789022 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 3789022 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 3789022 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 3789022 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 3789022 # number of overall hits -system.cpu0.icache.overall_hits::total 3789022 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 423106 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 423106 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 423106 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 423106 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 423106 # number of overall misses -system.cpu0.icache.overall_misses::total 423106 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5802286496 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5802286496 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5802286496 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5802286496 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5802286496 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5802286496 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 4212128 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 4212128 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 4212128 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 4212128 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 4212128 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 4212128 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100449 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.100449 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100449 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.100449 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100449 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.100449 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13713.552859 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13713.552859 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13713.552859 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13713.552859 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13713.552859 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13713.552859 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 4195 # number of cycles access was blocked +system.cpu0.rob.rob_reads 77052413 # The number of ROB reads +system.cpu0.rob.rob_writes 76827079 # The number of ROB writes +system.cpu0.timesIdled 370271 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 27463996 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5157937915 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 23989067 # Number of Instructions Simulated +system.cpu0.committedOps 31709617 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 23989067 # Number of Instructions Simulated +system.cpu0.cpi 2.901883 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.901883 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.344604 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.344604 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 174143996 # number of integer regfile reads +system.cpu0.int_regfile_writes 34604534 # number of integer regfile writes +system.cpu0.fp_regfile_reads 3264 # number of floating regfile reads +system.cpu0.fp_regfile_writes 896 # number of floating regfile writes +system.cpu0.misc_regfile_reads 13203658 # number of misc regfile reads +system.cpu0.misc_regfile_writes 457594 # number of misc regfile writes +system.cpu0.icache.replacements 399659 # number of replacements +system.cpu0.icache.tagsinuse 511.575445 # Cycle average of tags in use +system.cpu0.icache.total_refs 3842942 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 400171 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 9.603250 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 6980726000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 511.575445 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.999171 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.999171 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 3842942 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 3842942 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 3842942 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 3842942 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 3842942 # number of overall hits +system.cpu0.icache.overall_hits::total 3842942 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 431911 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 431911 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 431911 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 431911 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 431911 # number of overall misses +system.cpu0.icache.overall_misses::total 431911 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5969636493 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5969636493 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5969636493 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5969636493 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5969636493 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5969636493 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 4274853 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 4274853 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 4274853 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 4274853 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 4274853 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 4274853 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.101035 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.101035 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.101035 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.101035 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.101035 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.101035 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13821.450468 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13821.450468 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13821.450468 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13821.450468 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13821.450468 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13821.450468 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 3644 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 183 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 174 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 22.923497 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 20.942529 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 30174 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 30174 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 30174 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 30174 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 30174 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 30174 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 392932 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 392932 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 392932 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 392932 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 392932 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 392932 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4748967496 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4748967496 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4748967496 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4748967496 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4748967496 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4748967496 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7889500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7889500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7889500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 7889500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093286 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093286 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093286 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.093286 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093286 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.093286 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12085.977971 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12085.977971 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12085.977971 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12085.977971 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12085.977971 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12085.977971 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 31718 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 31718 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 31718 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 31718 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 31718 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 31718 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 400193 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 400193 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 400193 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 400193 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 400193 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 400193 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4864756575 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4864756575 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4864756575 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4864756575 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4864756575 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4864756575 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 9682500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 9682500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 9682500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 9682500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093616 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093616 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093616 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.093616 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093616 # 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number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5774321 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3157289 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3157289 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139126 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 139126 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137035 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 137035 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 8931610 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 8931610 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 8931610 # number of overall hits -system.cpu0.dcache.overall_hits::total 8931610 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 392659 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 392659 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1582356 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1582356 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8783 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 8783 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7478 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7478 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1975015 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1975015 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1975015 # number of overall misses -system.cpu0.dcache.overall_misses::total 1975015 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5465751000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5465751000 # 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number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6166980 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4739645 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4739645 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 147909 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 147909 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144513 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 144513 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 10906625 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 10906625 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 10906625 # 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miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.181084 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.181084 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13919.841389 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13919.841389 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38468.700067 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 38468.700067 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10074.120460 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10074.120460 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6241.642150 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6241.642150 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33588.063566 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 33588.063566 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33588.063566 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 33588.063566 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 8548 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 2163 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 649 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 77 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.171032 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 28.090909 # average number of cycles each access was blocked +system.cpu0.dcache.replacements 275313 # number of replacements +system.cpu0.dcache.tagsinuse 479.702966 # Cycle average of tags in use +system.cpu0.dcache.total_refs 9426114 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 275825 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 34.174255 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 49336000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 479.702966 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.936920 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.936920 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5876643 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5876643 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3228072 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3228072 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139641 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 139641 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137200 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 137200 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 9104715 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 9104715 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 9104715 # number of overall hits +system.cpu0.dcache.overall_hits::total 9104715 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 392586 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 392586 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1585207 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1585207 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8832 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 8832 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7754 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7754 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1977793 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1977793 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1977793 # number of overall misses +system.cpu0.dcache.overall_misses::total 1977793 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5514730000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5514730000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 76877974883 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 76877974883 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 89351500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 89351500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 49685500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 49685500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 82392704883 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 82392704883 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 82392704883 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 82392704883 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6269229 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6269229 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4813279 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4813279 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 148473 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 148473 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144954 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 144954 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 11082508 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 11082508 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 11082508 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 11082508 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.062621 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.062621 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.329340 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.329340 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059486 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059486 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053493 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053493 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.178461 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.178461 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.178461 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.178461 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14047.189660 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14047.189660 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 48497.120492 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 48497.120492 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10116.791214 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10116.791214 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6407.725045 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6407.725045 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 41658.912173 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 41658.912173 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 41658.912173 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 41658.912173 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 10507 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 10018 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 605 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 134 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 17.366942 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 74.761194 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 256417 # number of writebacks -system.cpu0.dcache.writebacks::total 256417 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 203981 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 203981 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1452148 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1452148 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 473 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 473 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1656129 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1656129 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1656129 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1656129 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188678 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 188678 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130208 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 130208 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8310 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8310 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7477 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7477 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 318886 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 318886 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 318886 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 318886 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2371660000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2371660000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4050141991 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4050141991 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66675500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66675500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31721000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31721000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6421801991 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 6421801991 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6421801991 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 6421801991 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13513534500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13513534500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1180320378 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1180320378 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14693854878 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14693854878 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030595 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030595 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027472 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027472 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056183 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056183 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051739 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051739 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029238 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.029238 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029238 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.029238 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12569.880961 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12569.880961 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31105.170120 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31105.170120 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8023.525872 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8023.525872 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4242.476929 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4242.476929 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20138.237461 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20138.237461 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20138.237461 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20138.237461 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 255296 # number of writebacks +system.cpu0.dcache.writebacks::total 255296 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 203565 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 203565 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1454109 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1454109 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 475 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 475 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1657674 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1657674 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1657674 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1657674 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189021 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 189021 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131098 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 131098 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8357 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8357 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7751 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7751 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 320119 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 320119 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 320119 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 320119 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2392342380 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2392342380 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5118910660 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5118910660 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 67659513 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 67659513 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 34183001 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 34183001 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7511253040 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 7511253040 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7511253040 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 7511253040 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13429863028 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13429863028 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1251424879 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1251424879 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14681287907 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14681287907 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030151 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030151 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027237 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027237 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056286 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056286 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053472 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053472 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028885 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.028885 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028885 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.028885 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12656.489914 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12656.489914 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39046.443577 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39046.443577 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8096.148498 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8096.148498 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4410.140756 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4410.140756 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23463.940097 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23463.940097 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23463.940097 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23463.940097 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1219,38 +1780,38 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 9076266 # Number of BP lookups -system.cpu1.branchPred.condPredicted 7463483 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 407973 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 6084116 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 5247879 # Number of BTB hits +system.cpu1.branchPred.lookups 9253585 # Number of BP lookups +system.cpu1.branchPred.condPredicted 7592303 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 416171 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 6192388 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 5325484 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 86.255407 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 773475 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 42302 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 86.000490 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 798470 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 43798 # Number of incorrect RAS predictions. system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 42903620 # DTB read hits -system.cpu1.dtb.read_misses 37068 # DTB read misses -system.cpu1.dtb.write_hits 6823215 # DTB write hits -system.cpu1.dtb.write_misses 10679 # DTB write misses +system.cpu1.dtb.read_hits 43179554 # DTB read hits +system.cpu1.dtb.read_misses 37431 # DTB read misses +system.cpu1.dtb.write_hits 6972554 # DTB write hits +system.cpu1.dtb.write_misses 10848 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2009 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 2777 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 305 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2005 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 2926 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 258 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 663 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 42940688 # DTB read accesses -system.cpu1.dtb.write_accesses 6833894 # DTB write accesses +system.cpu1.dtb.perms_faults 669 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 43216985 # DTB read accesses +system.cpu1.dtb.write_accesses 6983402 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 49726835 # DTB hits -system.cpu1.dtb.misses 47747 # DTB misses -system.cpu1.dtb.accesses 49774582 # DTB accesses -system.cpu1.itb.inst_hits 8394995 # ITB inst hits -system.cpu1.itb.inst_misses 5378 # ITB inst misses +system.cpu1.dtb.hits 50152108 # DTB hits +system.cpu1.dtb.misses 48279 # DTB misses +system.cpu1.dtb.accesses 50200387 # DTB accesses +system.cpu1.itb.inst_hits 8467709 # ITB inst hits +system.cpu1.itb.inst_misses 5542 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1259,114 +1820,114 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1532 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1527 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1500 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1492 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8400373 # ITB inst accesses -system.cpu1.itb.hits 8394995 # DTB hits -system.cpu1.itb.misses 5378 # DTB misses -system.cpu1.itb.accesses 8400373 # DTB accesses -system.cpu1.numCycles 408777731 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 8473251 # ITB inst accesses +system.cpu1.itb.hits 8467709 # DTB hits +system.cpu1.itb.misses 5542 # DTB misses +system.cpu1.itb.accesses 8473251 # DTB accesses +system.cpu1.numCycles 412553366 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 19817241 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 66077936 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 9076266 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 6021354 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 14149044 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3958978 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 63415 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 75978247 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 4643 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 42826 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 1407438 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 103 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 8393192 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 739597 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2716 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 114161892 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.700766 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.044841 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 20142179 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 67124404 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 9253585 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 6123954 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 14367636 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3996679 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 69030 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 77666254 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 5814 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 41513 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 1490350 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 198 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 8465907 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 710561 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2899 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 116503477 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.698188 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.043258 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 100020305 87.61% 87.61% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 795953 0.70% 88.31% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 939001 0.82% 89.13% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1889167 1.65% 90.79% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1518004 1.33% 92.12% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 578108 0.51% 92.62% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 2132011 1.87% 94.49% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 410005 0.36% 94.85% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 5879338 5.15% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 102143196 87.67% 87.67% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 814134 0.70% 88.37% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 962782 0.83% 89.20% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1912655 1.64% 90.84% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1508621 1.29% 92.14% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 586161 0.50% 92.64% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 2143967 1.84% 94.48% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 421141 0.36% 94.84% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 6010820 5.16% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 114161892 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.022203 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.161648 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 21336269 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 76905312 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 12792890 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 524784 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2602637 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1103950 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 97871 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 75228090 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 324995 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 2602637 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 22719770 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 31941572 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 40729697 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 11839035 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 4329181 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 69767929 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 18791 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 669754 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 3086107 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 334 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 73761871 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 321211401 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 321151882 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 59519 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 49052831 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 24709040 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 445091 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 388163 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 7873081 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 13208830 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 8144792 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1029727 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1553546 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 63522315 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1158429 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 89134167 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 94409 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 16267434 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 45777798 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 277724 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 114161892 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.780770 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.519105 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 116503477 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.022430 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.162705 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 21695015 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 78657608 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 12988209 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 540911 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2621734 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1137928 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 100371 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 76331637 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 334218 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 2621734 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 23056356 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 33279261 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 41089956 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 12073504 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 4382666 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 71129037 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 18835 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 684998 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 3107715 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 374 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 75211284 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 327489941 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 327430919 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 59022 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 50108296 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 25102988 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 461152 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 401338 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 8025308 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 13414582 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 8304810 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1056481 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1432553 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 64611179 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1174620 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 90302569 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 94169 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 16313013 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 45540722 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 275640 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 116503477 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.775106 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.513735 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 83758719 73.37% 73.37% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 8417078 7.37% 80.74% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4293584 3.76% 84.50% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3776789 3.31% 87.81% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 10574202 9.26% 97.07% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1966117 1.72% 98.80% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1029866 0.90% 99.70% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 271331 0.24% 99.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 74206 0.07% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 85607171 73.48% 73.48% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 8609069 7.39% 80.87% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4398916 3.78% 84.65% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3887525 3.34% 87.98% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 10612061 9.11% 97.09% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1964931 1.69% 98.78% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1085414 0.93% 99.71% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 259410 0.22% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 78980 0.07% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 114161892 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 116503477 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 32060 0.41% 0.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 998 0.01% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 32357 0.41% 0.41% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 996 0.01% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.42% # attempts to use FU when none available @@ -1394,395 +1955,395 @@ system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.42% # at system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 7549280 95.84% 96.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 294896 3.74% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 7572484 95.70% 96.12% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 307046 3.88% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 313932 0.35% 0.35% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 37620086 42.21% 42.56% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 59138 0.07% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 13 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 10 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1510 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 10 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 43968936 49.33% 91.96% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7170532 8.04% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 38359652 42.48% 42.83% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 61197 0.07% 42.89% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.89% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.89% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.89% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.89% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.89% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.89% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 14 0.00% 42.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 10 0.00% 42.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1701 0.00% 42.90% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.90% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 10 0.00% 42.90% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.90% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 44223929 48.97% 91.87% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7342124 8.13% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 89134167 # Type of FU issued -system.cpu1.iq.rate 0.218050 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 7877234 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.088375 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 300434418 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 80956642 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 53641825 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 15018 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 8136 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6869 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 96689561 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 7908 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 342287 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 90302569 # Type of FU issued +system.cpu1.iq.rate 0.218887 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 7912883 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.087626 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 305148356 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 82107584 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 54845197 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 15407 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 8039 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6808 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 97893314 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 8206 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 355446 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 3455090 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 3893 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 17135 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1305851 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 3436601 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 3841 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 17378 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1303587 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 31905929 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 888458 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 31958921 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 917809 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2602637 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 24185109 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 359685 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 64785366 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 111899 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 13208830 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 8144792 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 869085 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 64974 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3561 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 17135 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 202123 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 154728 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 356851 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 86703480 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 43273897 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 2430687 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 2621734 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 25482277 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 363023 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 65889169 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 115264 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 13414582 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 8304810 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 878172 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 66494 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3874 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 17378 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 205598 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 157346 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 362944 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 87965313 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 43561744 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 2337256 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 104622 # number of nop insts executed -system.cpu1.iew.exec_refs 50383100 # number of memory reference insts executed -system.cpu1.iew.exec_branches 6997981 # Number of branches executed -system.cpu1.iew.exec_stores 7109203 # Number of stores executed -system.cpu1.iew.exec_rate 0.212104 # Inst execution rate -system.cpu1.iew.wb_sent 85724428 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 53648694 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 29926721 # num instructions producing a value -system.cpu1.iew.wb_consumers 53389506 # num instructions consuming a value +system.cpu1.iew.exec_nop 103370 # number of nop insts executed +system.cpu1.iew.exec_refs 50840273 # number of memory reference insts executed +system.cpu1.iew.exec_branches 7156944 # Number of branches executed +system.cpu1.iew.exec_stores 7278529 # Number of stores executed +system.cpu1.iew.exec_rate 0.213222 # Inst execution rate +system.cpu1.iew.wb_sent 86983330 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 54852005 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 30529736 # num instructions producing a value +system.cpu1.iew.wb_consumers 54511543 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.131242 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.560536 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.132957 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.560060 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 16147511 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 880705 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 311675 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 111559255 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.431612 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.399673 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 16208484 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 898980 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 317402 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 113881743 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.432055 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.398122 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 94810700 84.99% 84.99% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 8240774 7.39% 92.37% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2114811 1.90% 94.27% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1254575 1.12% 95.39% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1245157 1.12% 96.51% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 568382 0.51% 97.02% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 999815 0.90% 97.92% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 505524 0.45% 98.37% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1819517 1.63% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 96739305 84.95% 84.95% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 8399776 7.38% 92.32% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2206670 1.94% 94.26% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1295256 1.14% 95.40% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1289720 1.13% 96.53% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 586162 0.51% 97.05% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 954092 0.84% 97.88% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 596070 0.52% 98.41% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1814692 1.59% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 111559255 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 38062798 # Number of instructions committed -system.cpu1.commit.committedOps 48150353 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 113881743 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 38868743 # Number of instructions committed +system.cpu1.commit.committedOps 49203152 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 16592681 # Number of memory references committed -system.cpu1.commit.loads 9753740 # Number of loads committed -system.cpu1.commit.membars 190132 # Number of memory barriers committed -system.cpu1.commit.branches 5967363 # Number of branches committed -system.cpu1.commit.fp_insts 6822 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 42685619 # Number of committed integer instructions. -system.cpu1.commit.function_calls 534609 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1819517 # number cycles where commit BW limit reached +system.cpu1.commit.refs 16979204 # Number of memory references committed +system.cpu1.commit.loads 9977981 # Number of loads committed +system.cpu1.commit.membars 195491 # Number of memory barriers committed +system.cpu1.commit.branches 6119212 # Number of branches committed +system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 43616743 # Number of committed integer instructions. +system.cpu1.commit.function_calls 553203 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1814692 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 172993511 # The number of ROB reads -system.cpu1.rob.rob_writes 131291211 # The number of ROB writes -system.cpu1.timesIdled 1408204 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 294615839 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 1796493799 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 37993159 # Number of Instructions Simulated -system.cpu1.committedOps 48080714 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 37993159 # Number of Instructions Simulated -system.cpu1.cpi 10.759246 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 10.759246 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.092943 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.092943 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 387964882 # number of integer regfile reads -system.cpu1.int_regfile_writes 56217113 # number of integer regfile writes -system.cpu1.fp_regfile_reads 4997 # number of floating regfile reads -system.cpu1.fp_regfile_writes 2346 # number of floating regfile writes -system.cpu1.misc_regfile_reads 18468785 # number of misc regfile reads -system.cpu1.misc_regfile_writes 405479 # number of misc regfile writes -system.cpu1.icache.replacements 595625 # number of replacements -system.cpu1.icache.tagsinuse 480.695488 # Cycle average of tags in use -system.cpu1.icache.total_refs 7752260 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 596137 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 13.004158 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 74233129000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 480.695488 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.938858 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.938858 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 7752260 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 7752260 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 7752260 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 7752260 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 7752260 # number of overall hits -system.cpu1.icache.overall_hits::total 7752260 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 640881 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 640881 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 640881 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 640881 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 640881 # number of overall misses -system.cpu1.icache.overall_misses::total 640881 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8621805995 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 8621805995 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 8621805995 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 8621805995 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 8621805995 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 8621805995 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 8393141 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 8393141 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 8393141 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 8393141 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 8393141 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 8393141 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.076358 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.076358 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.076358 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.076358 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.076358 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.076358 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13453.052899 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13453.052899 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13453.052899 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13453.052899 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13453.052899 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13453.052899 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 2044 # number of cycles access was blocked +system.cpu1.rob.rob_reads 176412864 # The number of ROB reads +system.cpu1.rob.rob_writes 133542996 # The number of ROB writes +system.cpu1.timesIdled 1428534 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 296049889 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 4814402067 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 38799104 # Number of Instructions Simulated +system.cpu1.committedOps 49133513 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 38799104 # Number of Instructions Simulated +system.cpu1.cpi 10.633064 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 10.633064 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.094046 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.094046 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 393827212 # number of integer regfile reads +system.cpu1.int_regfile_writes 57409312 # number of integer regfile writes +system.cpu1.fp_regfile_reads 5077 # number of floating regfile reads +system.cpu1.fp_regfile_writes 2342 # number of floating regfile writes +system.cpu1.misc_regfile_reads 18946986 # number of misc regfile reads +system.cpu1.misc_regfile_writes 419134 # number of misc regfile writes +system.cpu1.icache.replacements 614670 # number of replacements +system.cpu1.icache.tagsinuse 498.803951 # Cycle average of tags in use +system.cpu1.icache.total_refs 7804426 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 615182 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 12.686369 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 74831061000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 498.803951 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.974226 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.974226 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 7804426 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 7804426 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 7804426 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 7804426 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 7804426 # number of overall hits +system.cpu1.icache.overall_hits::total 7804426 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 661434 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 661434 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 661434 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 661434 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 661434 # number of overall misses +system.cpu1.icache.overall_misses::total 661434 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8993382992 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 8993382992 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 8993382992 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 8993382992 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 8993382992 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 8993382992 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 8465860 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 8465860 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 8465860 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 8465860 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 8465860 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 8465860 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.078130 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.078130 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.078130 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.078130 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.078130 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.078130 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13596.795738 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13596.795738 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13596.795738 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13596.795738 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13596.795738 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13596.795738 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 3054 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 172 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 205 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.883721 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.897561 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 44715 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 44715 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 44715 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 44715 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 44715 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 44715 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 596166 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 596166 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 596166 # 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number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 57807000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 57807000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 81902853515 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 81902853515 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 81902853515 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 81902853515 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 8911306 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 8911306 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 5834744 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 5834744 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 113984 # 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miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.124535 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.124535 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.101022 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.101022 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.133414 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.133414 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.133414 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.133414 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15457.698721 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15457.698721 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 48374.579140 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 48374.579140 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9248.502994 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9248.502994 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5299.504950 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5299.504950 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 41631.625064 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 41631.625064 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 41631.625064 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 41631.625064 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 31799 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 19293 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 3299 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 180 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.638982 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 107.183333 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 324632 # number of writebacks -system.cpu1.dcache.writebacks::total 324632 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 171788 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 171788 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1394549 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 1394549 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1443 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1443 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1566337 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1566337 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1566337 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1566337 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 228268 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 228268 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161573 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 161573 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12513 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12513 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10605 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10605 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 389841 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 389841 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 389841 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 389841 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2854852000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2854852000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5117226213 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5117226213 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89555500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89555500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32658000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32658000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7972078213 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 7972078213 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7972078213 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 7972078213 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168989815500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168989815500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 35679552148 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 35679552148 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 204669367648 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 204669367648 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026210 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026210 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028369 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028369 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112247 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112247 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100539 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100539 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027064 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.027064 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027064 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.027064 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12506.579985 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12506.579985 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31671.295408 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31671.295408 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7156.996723 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7156.996723 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3079.490806 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3079.490806 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20449.563317 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20449.563317 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20449.563317 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20449.563317 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 327984 # number of writebacks +system.cpu1.dcache.writebacks::total 327984 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 171525 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 171525 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1401265 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1401265 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1449 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1449 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1572790 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1572790 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1572790 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1572790 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 231477 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 231477 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 163056 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 163056 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12746 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12746 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10906 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10906 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 394533 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 394533 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 394533 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 394533 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2900781135 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2900781135 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 6520340298 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 6520340298 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 90030007 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 90030007 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 35995000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 35995000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9421121433 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 9421121433 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9421121433 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 9421121433 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169236235005 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169236235005 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 34877229187 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 34877229187 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 204113464192 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 204113464192 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025976 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025976 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027946 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027946 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.111823 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.111823 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.101003 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.101003 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026755 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026755 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026755 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026755 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12531.617115 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12531.617115 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 39988.349389 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 39988.349389 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7063.392986 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7063.392986 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3300.476802 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3300.476802 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23879.172168 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23879.172168 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23879.172168 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23879.172168 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1804,18 +2365,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 540125454155 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 540125454155 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 540125454155 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 540125454155 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1508067529269 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1508067529269 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1508067529269 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1508067529269 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 41707 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 42383 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 48865 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 50336 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index d0699dda9..b3687441c 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,134 +1,134 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.533116 # Number of seconds simulated -sim_ticks 2533115780500 # Number of ticks simulated -final_tick 2533115780500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.534279 # Number of seconds simulated +sim_ticks 2534279149500 # Number of ticks simulated +final_tick 2534279149500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 64757 # Simulator instruction rate (inst/s) -host_op_rate 83325 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2720016614 # Simulator tick rate (ticks/s) -host_mem_usage 398876 # Number of bytes of host memory used -host_seconds 931.29 # Real time elapsed on the host -sim_insts 60307726 # Number of instructions simulated -sim_ops 77599286 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 2624 # Number of bytes read from this memory +host_inst_rate 51469 # Simulator instruction rate (inst/s) +host_op_rate 66227 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2162854547 # Simulator tick rate (ticks/s) +host_mem_usage 400508 # Number of bytes of host memory used +host_seconds 1171.73 # Real time elapsed on the host +sim_insts 60307893 # Number of instructions simulated +sim_ops 77599512 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::realview.clcd 119547392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 2880 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 796160 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9093200 # Number of bytes read from this memory -system.physmem.bytes_read::total 129429776 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 796160 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 796160 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3781760 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 796992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9094160 # Number of bytes read from this memory +system.physmem.bytes_read::total 129441552 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 796992 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 796992 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3783360 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6797832 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 41 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 6799432 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 14943424 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 45 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12440 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142115 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096806 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59090 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 12453 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142130 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15098054 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59115 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813108 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47189972 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1036 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 813133 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47172148 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1136 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 314301 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3589729 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51095089 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 314301 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314301 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1492928 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1190657 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2683585 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1492928 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47189972 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1036 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 314485 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3588460 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51076280 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 314485 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314485 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1492874 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1190110 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2682985 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1492874 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47172148 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1136 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 314301 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4780386 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53778674 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15096806 # Total number of read requests seen -system.physmem.writeReqs 813108 # Total number of write requests seen -system.physmem.cpureqs 218339 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 966195584 # Total number of bytes read from memory -system.physmem.bytesWritten 52038912 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 129429776 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6797832 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 312 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4687 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 943937 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 943440 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 943392 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 944197 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 943973 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 943153 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 943272 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 943872 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 943794 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 943286 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 943217 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 943610 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 943691 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 943079 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 942979 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 943602 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50829 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 50406 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50439 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51150 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50909 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50184 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50277 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50865 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51361 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 50899 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50798 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51185 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51244 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 50710 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 50627 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51225 # Track writes on a per bank basis +system.physmem.bw_total::cpu.inst 314485 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4778571 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53759265 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15098054 # Total number of read requests seen +system.physmem.writeReqs 813133 # Total number of write requests seen +system.physmem.cpureqs 218381 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 966275456 # Total number of bytes read from memory +system.physmem.bytesWritten 52040512 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 129441552 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6799432 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 339 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4672 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 944601 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 943433 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 943409 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 943592 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 943465 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 943701 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 943525 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 943240 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 944001 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 943648 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 943214 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 942809 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 943923 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 943684 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 943779 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 943691 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 49135 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 48909 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50973 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51086 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 51003 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 51258 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 51261 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51198 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51347 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51095 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50750 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 50404 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51353 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 50977 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51264 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51120 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 32506 # Number of times wr buffer was full causing retry -system.physmem.totGap 2533114676500 # Total gap between requests +system.physmem.numWrRetry 32444 # Number of times wr buffer was full causing retry +system.physmem.totGap 2534279100000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 36 # Categorize read packet sizes -system.physmem.readPktSize::3 14942208 # Categorize read packet sizes +system.physmem.readPktSize::3 14943424 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154562 # Categorize read packet sizes +system.physmem.readPktSize::6 154594 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 754018 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 59090 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1040416 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 981351 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 950574 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3550435 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2676222 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2687728 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2649399 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 60672 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 59169 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 108674 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 157504 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 108150 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 16730 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 16584 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 20063 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 12694 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 112 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 9 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59115 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1052560 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 982701 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 988227 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3681755 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2757300 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2755283 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2712082 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 17052 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 15182 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 27533 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 39830 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 27503 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 10257 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 10197 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 13755 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 6392 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 94 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -139,59 +139,326 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2575 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2624 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2659 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2706 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2730 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2756 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2782 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2805 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 2829 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32778 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32729 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32694 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32647 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32623 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 32597 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 32571 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 32548 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 32524 # What write queue length does an incoming req see -system.physmem.totQLat 393224294250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 485624283000 # Sum of mem lat for all requests -system.physmem.totBusLat 75482470000 # Total cycles spent in databus access -system.physmem.totBankLat 16917518750 # Total cycles spent in bank access -system.physmem.avgQLat 26047.39 # Average queueing delay per request -system.physmem.avgBankLat 1120.63 # Average bank access latency per request +system.physmem.wrQLenPdf::0 2591 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2647 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2703 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2761 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2791 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2818 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 2847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 2874 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 2892 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32763 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32707 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32651 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32593 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32563 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32536 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 32507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 32480 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 32462 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 42559 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 23924.789210 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 1816.195393 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 32272.883514 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-95 8308 19.52% 19.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-159 3417 8.03% 27.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-223 2234 5.25% 32.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-287 1796 4.22% 37.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-351 1258 2.96% 39.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-415 1103 2.59% 42.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-479 837 1.97% 44.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-543 830 1.95% 46.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-607 538 1.26% 47.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-671 533 1.25% 49.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-735 414 0.97% 49.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-799 384 0.90% 50.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-863 258 0.61% 51.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-927 273 0.64% 52.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-991 193 0.45% 52.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1055 240 0.56% 53.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1119 148 0.35% 53.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1183 144 0.34% 53.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1247 105 0.25% 54.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1311 120 0.28% 54.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1375 89 0.21% 54.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1439 396 0.93% 55.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1503 1932 4.54% 60.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1567 440 1.03% 61.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1631 89 0.21% 61.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1695 139 0.33% 61.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1759 56 0.13% 61.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1823 104 0.24% 61.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1887 40 0.09% 62.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1951 62 0.15% 62.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-2015 22 0.05% 62.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2079 58 0.14% 62.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2143 29 0.07% 62.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2207 47 0.11% 62.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2271 13 0.03% 62.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2335 37 0.09% 62.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2399 11 0.03% 62.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2463 28 0.07% 62.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2527 17 0.04% 62.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2591 25 0.06% 62.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2655 7 0.02% 62.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2719 18 0.04% 62.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2783 4 0.01% 62.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2847 18 0.04% 63.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2911 6 0.01% 63.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2975 14 0.03% 63.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3039 6 0.01% 63.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3103 12 0.03% 63.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3167 2 0.00% 63.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3231 7 0.02% 63.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3295 6 0.01% 63.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3359 17 0.04% 63.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3423 5 0.01% 63.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3487 8 0.02% 63.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3551 3 0.01% 63.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3615 5 0.01% 63.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3679 6 0.01% 63.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3743 9 0.02% 63.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3807 1 0.00% 63.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3871 5 0.01% 63.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3935 4 0.01% 63.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3999 9 0.02% 63.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4063 4 0.01% 63.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4127 39 0.09% 63.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4191 5 0.01% 63.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4255 7 0.02% 63.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4319 4 0.01% 63.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4383 6 0.01% 63.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4447 2 0.00% 63.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4511 3 0.01% 63.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4575 4 0.01% 63.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4639 4 0.01% 63.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4767 6 0.01% 63.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4831 1 0.00% 63.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4895 8 0.02% 63.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4959 3 0.01% 63.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-5023 5 0.01% 63.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5151 5 0.01% 63.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5215 1 0.00% 63.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5279 1 0.00% 63.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5343 1 0.00% 63.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5407 1 0.00% 63.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5471 2 0.00% 63.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5535 3 0.01% 63.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5599 1 0.00% 63.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5663 2 0.00% 63.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5727 3 0.01% 63.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5919 3 0.01% 63.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6047 3 0.01% 63.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6111 1 0.00% 63.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6175 6 0.01% 63.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6239 3 0.01% 63.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6303 1 0.00% 63.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6431 1 0.00% 63.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6495 2 0.00% 63.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6559 3 0.01% 63.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6623 2 0.00% 63.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6687 3 0.01% 63.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6751 1 0.00% 63.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6815 18 0.04% 63.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6879 5 0.01% 63.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6943 1 0.00% 63.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7071 8 0.02% 63.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7199 6 0.01% 63.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7327 1 0.00% 63.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7391 1 0.00% 63.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7455 8 0.02% 63.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7583 9 0.02% 63.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7647 2 0.00% 63.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7711 6 0.01% 63.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7839 3 0.01% 63.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7903 3 0.01% 63.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7967 4 0.01% 63.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8031 5 0.01% 63.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8095 7 0.02% 63.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8159 4 0.01% 63.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8223 322 0.76% 64.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8735 1 0.00% 64.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8991 1 0.00% 64.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9152-9183 1 0.00% 64.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9247 2 0.00% 64.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9503 1 0.00% 64.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9536-9567 1 0.00% 64.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10271 19 0.04% 64.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10527 1 0.00% 64.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11039 1 0.00% 64.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11295 1 0.00% 64.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11551 2 0.00% 64.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11904-11935 1 0.00% 64.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12319 1 0.00% 64.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12575 2 0.00% 64.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13343 4 0.01% 64.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13599 1 0.00% 64.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13855 1 0.00% 64.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14367 2 0.00% 64.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14623 1 0.00% 64.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14879 2 0.00% 64.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15040-15071 1 0.00% 64.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15199 1 0.00% 64.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15391 3 0.01% 64.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15647 2 0.00% 64.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16159 1 0.00% 64.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16415 2 0.00% 64.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16671 1 0.00% 64.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16896-16927 3 0.01% 64.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17183 2 0.00% 64.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17216-17247 2 0.00% 64.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17344-17375 1 0.00% 64.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17439 2 0.00% 64.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17792-17823 1 0.00% 64.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17951 2 0.00% 64.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17984-18015 1 0.00% 64.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18207 2 0.00% 64.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18463 2 0.00% 64.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19231 2 0.00% 64.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19840-19871 1 0.00% 64.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20224-20255 3 0.01% 64.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20544-20575 1 0.00% 64.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20736-20767 1 0.00% 64.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21248-21279 1 0.00% 64.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21312-21343 1 0.00% 64.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21535 2 0.00% 64.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22016-22047 1 0.00% 64.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22272-22303 1 0.00% 64.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22400-22431 1 0.00% 64.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22559 1 0.00% 64.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22592-22623 1 0.00% 64.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22784-22815 1 0.00% 64.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23040-23071 1 0.00% 64.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23583 2 0.00% 64.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23808-23839 2 0.00% 64.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24351 2 0.00% 64.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24607 4 0.01% 64.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25088-25119 1 0.00% 64.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25631 3 0.01% 64.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25664-25695 1 0.00% 64.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25728-25759 1 0.00% 64.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26399 1 0.00% 64.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26655 2 0.00% 64.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27328-27359 1 0.00% 64.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27456-27487 1 0.00% 64.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27679 1 0.00% 64.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28447 1 0.00% 64.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28703 1 0.00% 64.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28736-28767 1 0.00% 64.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28959 2 0.00% 64.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29215 1 0.00% 64.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29376-29407 1 0.00% 64.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29471 1 0.00% 64.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29727 1 0.00% 64.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-29983 1 0.00% 64.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30016-30047 1 0.00% 64.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30239 3 0.01% 64.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30592-30623 1 0.00% 64.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30751 1 0.00% 64.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31104-31135 1 0.00% 64.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31263 1 0.00% 64.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31424-31455 1 0.00% 64.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31519 1 0.00% 64.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31775 2 0.00% 64.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32287 1 0.00% 64.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33664-33695 2 0.00% 64.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33728-33759 1 0.00% 64.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33823 44 0.10% 65.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34176-34207 1 0.00% 65.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34752-34783 1 0.00% 65.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36608-36639 1 0.00% 65.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36895 2 0.00% 65.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37248-37279 1 0.00% 65.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39296-39327 1 0.00% 65.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39808-39839 1 0.00% 65.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40000-40031 1 0.00% 65.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-42015 1 0.00% 65.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42048-42079 1 0.00% 65.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42527 2 0.00% 65.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43295 1 0.00% 65.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44672-44703 1 0.00% 65.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44831 1 0.00% 65.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45343 1 0.00% 65.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47647 1 0.00% 65.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47936-47967 1 0.00% 65.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48159 1 0.00% 65.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48671 1 0.00% 65.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48927 1 0.00% 65.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49183 1 0.00% 65.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49920-49951 1 0.00% 65.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50176-50207 2 0.00% 65.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50432-50463 1 0.00% 65.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50688-50719 1 0.00% 65.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::54272-54303 1 0.00% 65.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::56000-56031 1 0.00% 65.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::56832-56863 1 0.00% 65.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::57344-57375 1 0.00% 65.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::58368-58399 1 0.00% 65.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::58944-58975 1 0.00% 65.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::59840-59871 1 0.00% 65.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::62208-62239 1 0.00% 65.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::62848-62879 1 0.00% 65.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::63232-63263 1 0.00% 65.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::63488-63519 2 0.00% 65.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::64256-64287 1 0.00% 65.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::64704-64735 1 0.00% 65.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65024-65055 13 0.03% 65.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65152-65183 18 0.04% 65.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65280-65311 18 0.04% 65.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65344-65375 8 0.02% 65.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65472-65503 18 0.04% 65.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65536-65567 14406 33.85% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::113216-113247 1 0.00% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::129664-129695 1 0.00% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::129792-129823 1 0.00% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::129984-130015 1 0.00% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::130432-130463 1 0.00% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::131072-131103 325 0.76% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::131200-131231 1 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::132096-132127 3 0.01% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::136576-136607 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::168704-168735 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::169664-169695 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::190464-190495 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::196352-196383 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::196608-196639 9 0.02% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 42559 # Bytes accessed per row activation +system.physmem.totQLat 355117101750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 446336213000 # Sum of mem lat for all requests +system.physmem.totBusLat 75488575000 # Total cycles spent in databus access +system.physmem.totBankLat 15730536250 # Total cycles spent in bank access +system.physmem.avgQLat 23521.25 # Average queueing delay per request +system.physmem.avgBankLat 1041.92 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 32168.02 # Average memory access latency -system.physmem.avgRdBW 381.43 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 20.54 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 51.10 # Average consumed read bandwidth in MB/s +system.physmem.avgMemAccLat 29563.16 # Average memory access latency +system.physmem.avgRdBW 381.28 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 20.53 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 51.08 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 2.68 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.14 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.19 # Average read queue length over time -system.physmem.avgWrQLen 11.11 # Average write queue length over time -system.physmem.readRowHits 15020181 # Number of row buffer hits during reads -system.physmem.writeRowHits 793022 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.49 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 97.53 # Row buffer hit rate for writes -system.physmem.avgGap 159216.11 # Average gap between requests +system.physmem.avgRdQLen 0.18 # Average read queue length over time +system.physmem.avgWrQLen 11.71 # Average write queue length over time +system.physmem.readRowHits 15070837 # Number of row buffer hits during reads +system.physmem.writeRowHits 797438 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.82 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 98.07 # Row buffer hit rate for writes +system.physmem.avgGap 159276.56 # Average gap between requests system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -204,44 +471,259 @@ system.realview.nvmem.bw_inst_read::cpu.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 54705448 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16150672 # Transaction distribution +system.membus.trans_dist::ReadResp 16150669 # Transaction distribution +system.membus.trans_dist::WriteReq 763336 # Transaction distribution +system.membus.trans_dist::WriteResp 763336 # Transaction distribution +system.membus.trans_dist::Writeback 59115 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4669 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4672 # Transaction distribution +system.membus.trans_dist::ReadExReq 131424 # Transaction distribution +system.membus.trans_dist::ReadExResp 131424 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382946 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885755 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3770 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272475 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29886845 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 29886845 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.bridge.slave 2382946 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 31772600 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.realview.gic.pio 3770 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 34159320 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390309 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16693592 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7540 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19091509 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119547368 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 119547368 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.bridge.slave 2390309 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 136240960 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.realview.gic.pio 7540 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 138638877 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 138638877 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 1491846000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 17371820500 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.7 # Layer utilization (%) +system.membus.reqLayer3.occupancy 3645000 # Layer occupancy (ticks) +system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer5.occupancy 1500 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 4719558707 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.respLayer2.occupancy 33739093743 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 1.3 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu.branchPred.lookups 14672817 # Number of BP lookups -system.cpu.branchPred.condPredicted 11756302 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 704420 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9794195 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7944325 # Number of BTB hits +system.iobus.throughput 48115298 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16126739 # Transaction distribution +system.iobus.trans_dist::ReadResp 16126726 # Transaction distribution +system.iobus.trans_dist::WriteReq 8158 # Transaction distribution +system.iobus.trans_dist::WriteResp 8158 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7936 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 518 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1026 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382946 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 29886835 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 29886835 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.realview_io.pio 7936 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.timer0.pio 518 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.timer1.pio 1026 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.iocache.cpu_side 29886835 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 32269781 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15872 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1036 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2052 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390309 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 119547288 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::total 119547288 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.realview_io.pio 15872 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.timer0.pio 1036 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.timer1.pio 2052 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.iocache.cpu_side 119547288 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 121937597 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 121937597 # Total data (bytes) +system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 3973000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 518000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 519000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) +system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) +system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks) +system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) +system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 14943424000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) +system.iobus.respLayer0.occupancy 2374788000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) +system.iobus.respLayer1.occupancy 29886822000 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 1.2 # Layer utilization (%) +system.cpu.branchPred.lookups 14673159 # Number of BP lookups +system.cpu.branchPred.condPredicted 11756965 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 704729 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9767663 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7945266 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 81.112588 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1400354 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72452 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 81.342548 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1399657 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 72413 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51400888 # DTB read hits -system.cpu.dtb.read_misses 64225 # DTB read misses -system.cpu.dtb.write_hits 11700104 # DTB write hits -system.cpu.dtb.write_misses 15848 # DTB write misses +system.cpu.dtb.read_hits 51397173 # DTB read hits +system.cpu.dtb.read_misses 63986 # DTB read misses +system.cpu.dtb.write_hits 11699533 # DTB write hits +system.cpu.dtb.write_misses 15890 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3565 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2395 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 408 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 3562 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2402 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 405 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1336 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51465113 # DTB read accesses -system.cpu.dtb.write_accesses 11715952 # DTB write accesses +system.cpu.dtb.perms_faults 1410 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51461159 # DTB read accesses +system.cpu.dtb.write_accesses 11715423 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63100992 # DTB hits -system.cpu.dtb.misses 80073 # DTB misses -system.cpu.dtb.accesses 63181065 # DTB accesses -system.cpu.itb.inst_hits 12331220 # ITB inst hits -system.cpu.itb.inst_misses 11422 # ITB inst misses +system.cpu.dtb.hits 63096706 # DTB hits +system.cpu.dtb.misses 79876 # DTB misses +system.cpu.dtb.accesses 63176582 # DTB accesses +system.cpu.itb.inst_hits 12260245 # ITB inst hits +system.cpu.itb.inst_misses 11468 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -250,113 +732,113 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2480 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2492 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2905 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2998 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 12342642 # ITB inst accesses -system.cpu.itb.hits 12331220 # DTB hits -system.cpu.itb.misses 11422 # DTB misses -system.cpu.itb.accesses 12342642 # DTB accesses -system.cpu.numCycles 471822965 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 12271713 # ITB inst accesses +system.cpu.itb.hits 12260245 # DTB hits +system.cpu.itb.misses 11468 # DTB misses +system.cpu.itb.accesses 12271713 # DTB accesses +system.cpu.numCycles 475189978 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 30573370 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 96017663 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14672817 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9344679 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21160566 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5295047 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 124247 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 93127049 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2641 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 86502 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 2607471 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 357 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 12327822 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 900542 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5477 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 151317698 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.785150 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.150169 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 30497823 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 96057374 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14673159 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9344923 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21151922 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5296118 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 123395 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 94706901 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2678 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 86562 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 2683934 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 445 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 12256747 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 864492 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5531 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 152887644 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.777320 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.141699 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 130172761 86.03% 86.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1303441 0.86% 86.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1712324 1.13% 88.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2496425 1.65% 89.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2221306 1.47% 91.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1109073 0.73% 91.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2756927 1.82% 93.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 745885 0.49% 94.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8799556 5.82% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 131751310 86.18% 86.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1303513 0.85% 87.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1714679 1.12% 88.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2493622 1.63% 89.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2205066 1.44% 91.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1108856 0.73% 91.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2738323 1.79% 93.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 743817 0.49% 94.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8828458 5.77% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 151317698 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.031098 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.203504 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32529947 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 95168576 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19190992 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 961902 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3466281 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1957763 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 171745 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 112647177 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 568207 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3466281 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 34471547 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36699353 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52502253 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18154395 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6023869 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 106113727 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 20537 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 985646 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4066140 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 795 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 110515015 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 485506390 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 485415520 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 90870 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78390038 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 32124976 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 830416 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 736951 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12148327 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 20331207 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13516553 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1968455 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2470685 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 97921870 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1983479 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 124325634 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 167955 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 21739212 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 56995294 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 501084 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 151317698 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.821620 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.535306 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 152887644 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.030879 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.202145 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32458089 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 96821111 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19172249 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 971461 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3464734 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1958214 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 171741 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 112504503 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 568893 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3464734 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 34365136 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 38157390 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52654113 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18177530 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6068741 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 106257538 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 20628 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1016430 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4078403 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 665 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 110740396 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 486151881 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 486061534 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 90347 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78390288 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 32350107 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 830682 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 737164 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12219946 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 20282216 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13494315 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1963339 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2435947 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 97859231 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1984036 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 124319403 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 165680 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 21668523 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 56420296 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 501641 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 152887644 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.813142 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.528360 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 107101494 70.78% 70.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13519014 8.93% 79.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7070833 4.67% 84.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5935604 3.92% 88.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12601558 8.33% 96.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2800079 1.85% 98.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1698500 1.12% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 464413 0.31% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 126203 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 108584137 71.02% 71.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13613798 8.90% 79.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7066944 4.62% 84.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5988746 3.92% 88.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12566780 8.22% 96.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2768589 1.81% 98.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1723460 1.13% 99.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 446866 0.29% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 128324 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 151317698 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 152887644 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 62151 0.70% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 62053 0.70% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 3 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available @@ -385,383 +867,416 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8366348 94.60% 95.30% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 415303 4.70% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8365072 94.62% 95.32% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 413828 4.68% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58625951 47.16% 47.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93085 0.07% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 24 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 16 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 16 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52921154 42.57% 90.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12319608 9.91% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58665929 47.19% 47.48% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93120 0.07% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 16 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 1 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 11 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 11 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52876194 42.53% 90.09% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12318342 9.91% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 124325634 # Type of FU issued -system.cpu.iq.rate 0.263501 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8843805 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071134 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 409037091 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 121660776 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85961644 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23336 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12538 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10309 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 132793364 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12409 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 623444 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 124319403 # Type of FU issued +system.cpu.iq.rate 0.261620 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8840956 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071115 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 410589228 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 121528348 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 86069861 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23359 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12446 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10285 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 132784241 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12452 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 624311 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4676644 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6237 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 29883 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1784459 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4627641 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6443 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30069 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1762200 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107775 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 892558 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107875 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 918337 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3466281 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 27944782 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 433344 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100126481 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 202692 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 20331207 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13516553 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1410337 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 113091 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3418 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 29883 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 350144 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 269265 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 619409 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 121539796 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52087723 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2785838 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3464734 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 29357042 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 436051 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100064926 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 205472 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 20282216 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13494315 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1410818 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 114442 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3537 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30069 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 350642 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 268888 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 619530 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 121646726 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52084248 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2672677 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 221132 # number of nop insts executed -system.cpu.iew.exec_refs 64299655 # number of memory reference insts executed -system.cpu.iew.exec_branches 11557425 # Number of branches executed -system.cpu.iew.exec_stores 12211932 # Number of stores executed -system.cpu.iew.exec_rate 0.257596 # Inst execution rate -system.cpu.iew.wb_sent 120381824 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85971953 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47248258 # num instructions producing a value -system.cpu.iew.wb_consumers 88196266 # num instructions consuming a value +system.cpu.iew.exec_nop 221659 # number of nop insts executed +system.cpu.iew.exec_refs 64295158 # number of memory reference insts executed +system.cpu.iew.exec_branches 11560329 # Number of branches executed +system.cpu.iew.exec_stores 12210910 # Number of stores executed +system.cpu.iew.exec_rate 0.255996 # Inst execution rate +system.cpu.iew.wb_sent 120490085 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 86080146 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47268053 # num instructions producing a value +system.cpu.iew.wb_consumers 88199499 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.182212 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.535717 # average fanout of values written-back +system.cpu.iew.wb_rate 0.181149 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.535922 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 21471534 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 21408137 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1482395 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 535206 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 147851417 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.525864 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.516226 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 535479 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 149422910 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.520334 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.507055 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 120424253 81.45% 81.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13319272 9.01% 90.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3880838 2.62% 93.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2123082 1.44% 94.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1929256 1.30% 95.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 967576 0.65% 96.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1605493 1.09% 97.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 701565 0.47% 98.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2900082 1.96% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 121949451 81.61% 81.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13299405 8.90% 90.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3946740 2.64% 93.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2141050 1.43% 94.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1955041 1.31% 95.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 959721 0.64% 96.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1537792 1.03% 97.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 781343 0.52% 98.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2852367 1.91% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 147851417 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60458107 # Number of instructions committed -system.cpu.commit.committedOps 77749667 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 149422910 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60458274 # Number of instructions committed +system.cpu.commit.committedOps 77749893 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27386657 # Number of memory references committed -system.cpu.commit.loads 15654563 # Number of loads committed -system.cpu.commit.membars 403601 # Number of memory barriers committed -system.cpu.commit.branches 9961339 # Number of branches committed +system.cpu.commit.refs 27386690 # Number of memory references committed +system.cpu.commit.loads 15654575 # Number of loads committed +system.cpu.commit.membars 403596 # Number of memory barriers committed +system.cpu.commit.branches 9961373 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68854898 # Number of committed integer instructions. -system.cpu.commit.function_calls 991261 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2900082 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 68855105 # Number of committed integer instructions. +system.cpu.commit.function_calls 991268 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2852367 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 242323943 # The number of ROB reads -system.cpu.rob.rob_writes 202004834 # The number of ROB writes -system.cpu.timesIdled 1771447 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 320505267 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4594325554 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60307726 # Number of Instructions Simulated -system.cpu.committedOps 77599286 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60307726 # Number of Instructions Simulated -system.cpu.cpi 7.823591 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.823591 # CPI: Total CPI of All Threads -system.cpu.ipc 0.127819 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.127819 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 550297300 # number of integer regfile reads -system.cpu.int_regfile_writes 88455600 # number of integer regfile writes -system.cpu.fp_regfile_reads 8347 # number of floating regfile reads -system.cpu.fp_regfile_writes 2910 # number of floating regfile writes -system.cpu.misc_regfile_reads 30123534 # number of misc regfile reads -system.cpu.misc_regfile_writes 831893 # number of misc regfile writes -system.cpu.icache.replacements 979954 # number of replacements -system.cpu.icache.tagsinuse 511.616585 # Cycle average of tags in use -system.cpu.icache.total_refs 11267650 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 980466 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 11.492137 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 6410377000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.616585 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.999251 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.999251 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 11267650 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11267650 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11267650 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11267650 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11267650 # number of overall hits -system.cpu.icache.overall_hits::total 11267650 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1060047 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1060047 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1060047 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1060047 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1060047 # number of overall misses -system.cpu.icache.overall_misses::total 1060047 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14006301995 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14006301995 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14006301995 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14006301995 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14006301995 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14006301995 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12327697 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12327697 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12327697 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12327697 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12327697 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12327697 # 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average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13212.906593 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 5383 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 802 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 290 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 18.562069 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 802 # average number of cycles each access was blocked +system.cpu.rob.rob_reads 243879966 # The number of ROB reads +system.cpu.rob.rob_writes 201882555 # The number of ROB writes +system.cpu.timesIdled 1780421 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 322302334 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4593285278 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60307893 # Number of Instructions Simulated +system.cpu.committedOps 77599512 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60307893 # Number of Instructions Simulated +system.cpu.cpi 7.879399 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.879399 # CPI: Total CPI of All Threads +system.cpu.ipc 0.126913 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.126913 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 550704700 # number of integer regfile reads +system.cpu.int_regfile_writes 88578312 # number of integer regfile writes +system.cpu.fp_regfile_reads 8302 # number of floating regfile reads +system.cpu.fp_regfile_writes 2882 # number of floating regfile writes +system.cpu.misc_regfile_reads 30116391 # number of misc regfile reads +system.cpu.misc_regfile_writes 831896 # number of misc regfile writes +system.cpu.toL2Bus.throughput 58661050 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2657246 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2657245 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 763336 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 763336 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 607669 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2958 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 15 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2973 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 246055 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 246055 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1960500 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 5796171 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma 30982 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma 126318 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 7913971 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 62698816 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 85512245 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma 42284 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma 208804 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 148462149 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 148462149 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 201328 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3128322117 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1471549889 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 2533210636 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer2.occupancy 20419483 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer3.occupancy 74237753 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.cpu.icache.replacements 980157 # number of replacements +system.cpu.icache.tagsinuse 511.579914 # Cycle average of tags in use +system.cpu.icache.total_refs 11196212 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 980669 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 11.416912 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 6837358000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 511.579914 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.999180 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.999180 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 11196212 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11196212 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11196212 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11196212 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11196212 # number of overall hits +system.cpu.icache.overall_hits::total 11196212 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1060409 # 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number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12256621 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12256621 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12256621 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12256621 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12256621 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.086517 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.086517 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.086517 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.086517 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.086517 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.086517 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13445.472446 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13445.472446 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13445.472446 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13445.472446 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13445.472446 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13445.472446 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 6872 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 372 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 18.473118 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # 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number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 980506 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 980506 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11382269996 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11382269996 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11382269996 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11382269996 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11382269996 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11382269996 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7555000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7555000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7555000 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 7555000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.079537 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.079537 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.079537 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.079537 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.079537 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.079537 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11608.567409 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11608.567409 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11608.567409 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11608.567409 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11608.567409 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11608.567409 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79698 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 79698 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 79698 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 79698 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 79698 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 79698 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980711 # 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number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 9547000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 9547000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 9547000 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 9547000 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.080015 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.080015 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.080015 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.080015 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.080015 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.080015 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11811.268153 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11811.268153 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11811.268153 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11811.268153 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11811.268153 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11811.268153 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # 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Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.563637 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000409 # Average percentage of cache occupancy +system.cpu.l2cache.replacements 64365 # number of replacements +system.cpu.l2cache.tagsinuse 51350.135703 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1885273 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 129757 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 14.529259 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 2499221448500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 36903.083753 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.dtb.walker 33.180761 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000367 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 8167.882252 # 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number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13758946 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7259114 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7259114 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 242919 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 242919 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247600 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 247600 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21018060 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21018060 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21018060 # number of overall hits -system.cpu.dcache.overall_hits::total 21018060 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 736156 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 736156 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2963249 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2963249 # number of WriteReq misses +system.cpu.dcache.replacements 643353 # number of replacements +system.cpu.dcache.tagsinuse 511.992092 # Cycle average of tags in use +system.cpu.dcache.total_refs 21505591 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 643865 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 33.400777 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 48193000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.992092 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999985 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999985 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 13753583 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13753583 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7258444 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7258444 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 242854 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 242854 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247602 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247602 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21012027 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21012027 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21012027 # number of overall hits +system.cpu.dcache.overall_hits::total 21012027 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 737498 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 737498 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2963942 # 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number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 104713593229 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 181601500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 181601500 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 257000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 257000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 114452877729 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 114452877729 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 114452877729 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 114452877729 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14495102 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 14495102 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10222363 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10222363 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256458 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 256458 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_misses::cpu.data 15 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 15 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3701440 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3701440 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3701440 # number of overall misses +system.cpu.dcache.overall_misses::total 3701440 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10068067500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10068067500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 132595635732 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 132595635732 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 183801000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 183801000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 231000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 231000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 142663703232 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 142663703232 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 142663703232 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 142663703232 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14491081 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14491081 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10222386 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10222386 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256393 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 256393 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 247617 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 247617 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24717465 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24717465 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24717465 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24717465 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050787 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.050787 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289879 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.289879 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052792 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052792 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000069 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000069 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.149668 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.149668 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.149668 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.149668 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13229.919338 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13229.919338 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35337.426328 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35337.426328 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13413.213679 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13413.213679 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15117.647059 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15117.647059 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30938.185392 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30938.185392 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30938.185392 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30938.185392 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 30435 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 19416 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2583 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 249 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.782811 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 77.975904 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 24713467 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24713467 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24713467 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24713467 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050893 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.050893 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289946 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.289946 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052806 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052806 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000061 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000061 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.149774 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.149774 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.149774 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.149774 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13651.653971 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13651.653971 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44736.245086 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 44736.245086 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13575.670286 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13575.670286 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15400 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15400 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 38542.757206 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 38542.757206 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 38542.757206 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 38542.757206 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 32274 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 26462 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2637 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 287 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.238908 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 92.202091 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 607758 # number of writebacks -system.cpu.dcache.writebacks::total 607758 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 350427 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 350427 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714248 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2714248 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1344 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1344 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3064675 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3064675 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3064675 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3064675 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385729 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 385729 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249001 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 249001 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12195 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12195 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 17 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 17 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 634730 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 634730 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 634730 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 634730 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4803158500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4803158500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8205851415 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8205851415 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 142277500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 142277500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 223000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 223000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13009009915 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13009009915 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13009009915 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13009009915 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182395749000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182395749000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 36727240405 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 36727240405 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 219122989405 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 219122989405 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026611 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026611 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024358 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024358 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047552 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047552 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000069 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000069 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025679 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025679 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025679 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025679 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12452.158121 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12452.158121 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32955.094216 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32955.094216 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11666.871669 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11666.871669 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13117.647059 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13117.647059 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20495.344343 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20495.344343 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20495.344343 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20495.344343 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 607669 # number of writebacks +system.cpu.dcache.writebacks::total 607669 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351798 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 351798 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2715004 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2715004 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1354 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1354 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3066802 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3066802 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3066802 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3066802 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385700 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385700 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248938 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 248938 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12185 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12185 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 15 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 15 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 634638 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634638 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634638 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634638 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4965601859 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4965601859 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10500826931 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10500826931 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 144262002 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 144262002 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 201000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 201000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15466428790 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 15466428790 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15466428790 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15466428790 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182333907000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182333907000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 35770060494 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 35770060494 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 218103967494 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 218103967494 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026616 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026616 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024352 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024352 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047525 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047525 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000061 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000061 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025680 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025680 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025680 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025680 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12874.259422 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12874.259422 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42182.498980 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42182.498980 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11839.310792 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11839.310792 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13400 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13400 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24370.473861 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24370.473861 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24370.473861 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24370.473861 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1058,16 +1573,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229569916889 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1229569916889 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229569916889 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1229569916889 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1488848485257 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1488848485257 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1488848485257 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1488848485257 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83043 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 83044 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index 7f7ee8a99..edfc62ccf 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -1,175 +1,163 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.401343 # Number of seconds simulated -sim_ticks 2401342505500 # Number of ticks simulated -final_tick 2401342505500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.401127 # Number of seconds simulated +sim_ticks 2401127269500 # Number of ticks simulated +final_tick 2401127269500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 199955 # Simulator instruction rate (inst/s) -host_op_rate 256803 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7959007704 # Simulator tick rate (ticks/s) -host_mem_usage 399904 # Number of bytes of host memory used -host_seconds 301.71 # Real time elapsed on the host -sim_insts 60329298 # Number of instructions simulated -sim_ops 77481139 # Number of ops (including micro ops) simulated -system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 142330 # Simulator instruction rate (inst/s) +host_op_rate 182788 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5664980832 # Simulator tick rate (ticks/s) +host_mem_usage 401540 # Number of bytes of host memory used +host_seconds 423.85 # Real time elapsed on the host +sim_insts 60327009 # Number of instructions simulated +sim_ops 77475387 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 502112 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 7093136 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 511520 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 7145552 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 84928 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 676160 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 78912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 687680 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.dtb.walker 384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 175680 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1309048 # Number of bytes read from this memory -system.physmem.bytes_read::total 124660776 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 502112 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 84928 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 175680 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 762720 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3745536 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1490604 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 199456 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2.data 1325756 # Number of bytes written to this memory -system.physmem.bytes_written::total 6761352 # Number of bytes written to this memory +system.physmem.bytes_read::cpu2.inst 173184 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1243936 # Number of bytes read from this memory +system.physmem.bytes_read::total 124660496 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 511520 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 78912 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 173184 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 763616 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3744064 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1523456 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 157860 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2.data 1334500 # Number of bytes written to this memory +system.physmem.bytes_written::total 6759880 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14352384 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 14048 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 110864 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 14195 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 111683 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1327 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10565 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1233 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10745 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.dtb.walker 6 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 2745 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 20467 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14512410 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 58524 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 372651 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 49864 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2.data 331439 # Number of write requests responded to by this memory -system.physmem.num_writes::total 812478 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47814534 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu2.inst 2706 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 19444 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14512400 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 58501 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 380864 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 39465 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2.data 333625 # Number of write requests responded to by this memory +system.physmem.num_writes::total 812455 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47818820 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 53 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 209096 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 2953821 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 213033 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 2975916 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 35367 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 281576 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 32865 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 286399 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu2.dtb.walker 160 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 73159 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 545132 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51912951 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 209096 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 35367 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 73159 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 317622 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1559768 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 620738 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 83060 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2.data 552090 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2815655 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1559768 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47814534 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 72126 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 518063 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51917488 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 213033 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 32865 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 72126 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 318024 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1559294 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 634475 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 65744 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2.data 555781 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2815294 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1559294 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47818820 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 53 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 209096 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3574559 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 213033 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3610391 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 35367 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 364636 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 32865 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 352143 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu2.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 73159 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1097221 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54728606 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 12618023 # Total number of read requests seen -system.physmem.writeReqs 398732 # Total number of write requests seen -system.physmem.cpureqs 54886 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 807553472 # Total number of bytes read from memory -system.physmem.bytesWritten 25518848 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 102909560 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 2640668 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 2360 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 789126 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 788779 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 788883 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 789203 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 789028 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 788746 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 788896 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 788935 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 788618 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 788026 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 788041 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 788281 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 788275 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 788125 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 788319 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 788742 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 24962 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 24831 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 24770 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 25056 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 24828 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 24649 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 24736 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 24783 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 25151 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 24834 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 24774 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 24883 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 25404 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 24880 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 24969 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 25222 # Track writes on a per bank basis +system.physmem.bw_total::cpu2.inst 72126 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1073844 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54732782 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 12420439 # Total number of read requests seen +system.physmem.writeReqs 390212 # Total number of write requests seen +system.physmem.cpureqs 53603 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 794908096 # Total number of bytes read from memory +system.physmem.bytesWritten 24973568 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 101274592 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 2588168 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 1 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 2354 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 776339 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 775940 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 776092 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 776425 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 777292 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 776809 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 775620 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 775424 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 775584 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 776041 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 775688 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 776201 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 777483 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 777433 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 776149 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 775918 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 25457 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 25320 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 25407 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 25903 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 26305 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 26088 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 25428 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 23374 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 23183 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 23262 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 21306 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 21574 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 24629 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 24259 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 23496 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 25221 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 14347 # Number of times wr buffer was full causing retry -system.physmem.totGap 2400307282000 # Total gap between requests +system.physmem.numWrRetry 14413 # Number of times wr buffer was full causing retry +system.physmem.totGap 2400092064000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 14 # Categorize read packet sizes -system.physmem.readPktSize::3 12582912 # Categorize read packet sizes +system.physmem.readPktSize::2 8 # Categorize read packet sizes +system.physmem.readPktSize::3 12386304 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 35097 # Categorize read packet sizes +system.physmem.readPktSize::6 34127 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 381303 # Categorize write packet sizes +system.physmem.writePktSize::2 373090 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 17429 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 815886 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 792065 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 797737 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2998161 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2260870 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2261150 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2249588 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 49294 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 49195 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 91403 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 133606 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 91397 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 6927 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 6919 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 6911 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 6910 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 4 # What read queue length does an incoming req see +system.physmem.writePktSize::6 17122 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 803531 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 778993 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 809862 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3060255 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2298083 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2298065 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2262695 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 12148 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 12111 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 22591 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 33065 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 22584 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1615 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1614 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1614 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1612 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -185,326 +173,482 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2988 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2993 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2994 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3016 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3014 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3013 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3009 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3005 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3000 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 17346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 17336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 17334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 17330 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 17321 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 17317 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 17314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 17308 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 17306 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17301 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 14401 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 14393 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 14385 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 14359 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 14357 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 14355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 14353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 14351 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 14349 # What write queue length does an incoming req see -system.physmem.totQLat 277119182500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 352940243750 # Sum of mem lat for all requests -system.physmem.totBusLat 63090115000 # Total cycles spent in databus access -system.physmem.totBankLat 12730946250 # Total cycles spent in bank access -system.physmem.avgQLat 21962.17 # Average queueing delay per request -system.physmem.avgBankLat 1008.95 # Average bank access latency per request +system.physmem.wrQLenPdf::0 2522 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2527 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2534 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2548 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2548 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2547 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 2548 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 2547 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 2548 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 16974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 16970 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 16964 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 16959 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 16952 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 16947 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 16944 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 16942 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 16938 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 16934 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 16933 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 16925 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 16922 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 16920 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 14497 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 14485 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 14475 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 14454 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 14452 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 14449 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 14443 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 14437 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 14427 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 20861 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 39302.074493 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 6009.687839 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 33098.413312 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-95 3004 14.40% 14.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-159 1328 6.37% 20.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-223 811 3.89% 24.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-287 565 2.71% 27.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-351 381 1.83% 29.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-415 362 1.74% 30.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-479 265 1.27% 32.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-543 238 1.14% 33.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-607 172 0.82% 34.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-671 151 0.72% 34.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-735 130 0.62% 35.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-799 127 0.61% 36.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-863 66 0.32% 36.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-927 86 0.41% 36.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-991 45 0.22% 37.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1055 78 0.37% 37.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1119 36 0.17% 37.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1183 26 0.12% 37.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1247 22 0.11% 37.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1311 43 0.21% 38.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1375 28 0.13% 38.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1439 87 0.42% 38.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1503 101 0.48% 39.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1567 96 0.46% 39.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1631 23 0.11% 39.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1695 38 0.18% 39.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1759 20 0.10% 39.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1823 38 0.18% 40.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1887 12 0.06% 40.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1951 22 0.11% 40.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-2015 8 0.04% 40.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2079 17 0.08% 40.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2143 10 0.05% 40.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2207 9 0.04% 40.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2271 4 0.02% 40.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2335 3 0.01% 40.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2399 5 0.02% 40.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2463 9 0.04% 40.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2527 4 0.02% 40.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2591 4 0.02% 40.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2655 2 0.01% 40.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2719 2 0.01% 40.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2783 6 0.03% 40.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2847 3 0.01% 40.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2911 7 0.03% 40.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2975 1 0.00% 40.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3039 2 0.01% 40.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3103 4 0.02% 40.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3167 1 0.00% 40.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3231 3 0.01% 40.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3295 3 0.01% 40.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3359 8 0.04% 40.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3423 2 0.01% 40.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3487 3 0.01% 40.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3551 1 0.00% 40.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3615 3 0.01% 40.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3679 2 0.01% 40.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3743 2 0.01% 40.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3807 2 0.01% 40.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3871 1 0.00% 40.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3999 1 0.00% 40.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4063 1 0.00% 40.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4127 6 0.03% 40.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4191 2 0.01% 40.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4383 3 0.01% 40.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4703 1 0.00% 40.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4767 2 0.01% 40.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4831 2 0.01% 40.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4959 1 0.00% 40.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-5023 1 0.00% 41.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5151 1 0.00% 41.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5471 1 0.00% 41.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5535 1 0.00% 41.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6559 1 0.00% 41.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6815 4 0.02% 41.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6943 1 0.00% 41.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7071 2 0.01% 41.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7135 1 0.00% 41.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7391 2 0.01% 41.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7455 1 0.00% 41.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7711 2 0.01% 41.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7903 3 0.01% 41.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8031 1 0.00% 41.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8095 1 0.00% 41.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8223 2 0.01% 41.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11136-11167 1 0.00% 41.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11807 1 0.00% 41.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12319 1 0.00% 41.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15199 1 0.00% 41.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18463 1 0.00% 41.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19487 1 0.00% 41.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-31007 1 0.00% 41.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33567 2 0.01% 41.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33823 1 0.00% 41.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65536-65567 12093 57.97% 99.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::127424-127455 1 0.00% 99.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::131072-131103 181 0.87% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 20861 # Bytes accessed per row activation +system.physmem.totQLat 241895050750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 315493767000 # Sum of mem lat for all requests +system.physmem.totBusLat 62102190000 # Total cycles spent in databus access +system.physmem.totBankLat 11496526250 # Total cycles spent in bank access +system.physmem.avgQLat 19475.57 # Average queueing delay per request +system.physmem.avgBankLat 925.61 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 27971.12 # Average memory access latency -system.physmem.avgRdBW 336.29 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 10.63 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 42.86 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 1.10 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 25401.18 # Average memory access latency +system.physmem.avgRdBW 331.06 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 10.40 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 42.18 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 1.08 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 2.71 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.15 # Average read queue length over time -system.physmem.avgWrQLen 0.39 # Average write queue length over time -system.physmem.readRowHits 12563435 # Number of row buffer hits during reads -system.physmem.writeRowHits 392399 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.57 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 98.41 # Row buffer hit rate for writes -system.physmem.avgGap 184401.36 # Average gap between requests -system.l2c.replacements 63248 # number of replacements -system.l2c.tagsinuse 50357.471102 # Cycle average of tags in use -system.l2c.total_refs 1749120 # Total number of references to valid blocks. -system.l2c.sampled_refs 128641 # Sample count of references to valid blocks. -system.l2c.avg_refs 13.596909 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2374433885500 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 36827.136068 # Average occupied blocks per requestor +system.physmem.busUtil 2.67 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.13 # Average read queue length over time +system.physmem.avgWrQLen 0.40 # Average write queue length over time +system.physmem.readRowHits 12404411 # Number of row buffer hits during reads +system.physmem.writeRowHits 385376 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.87 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 98.76 # Row buffer hit rate for writes +system.physmem.avgGap 187351.30 # Average gap between requests +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 55731119 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 12759502 # Transaction distribution +system.membus.trans_dist::ReadResp 12759502 # Transaction distribution +system.membus.trans_dist::WriteReq 375940 # Transaction distribution +system.membus.trans_dist::WriteResp 375940 # Transaction distribution +system.membus.trans_dist::Writeback 17122 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2354 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2354 # Transaction distribution +system.membus.trans_dist::ReadExReq 26440 # Transaction distribution +system.membus.trans_dist::ReadExResp 26440 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 736482 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 836280 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 224 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1572986 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 24772608 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 24772608 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.bridge.slave 736482 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 25608888 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.realview.gic.pio 224 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 26345594 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 740439 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 4772328 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 448 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 5513215 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 99090432 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 99090432 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.bridge.slave 740439 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 103862760 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.realview.gic.pio 448 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 104603647 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 133817510 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 420513000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 13413227250 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.6 # Layer utilization (%) +system.membus.reqLayer3.occupancy 209500 # Layer occupancy (ticks) +system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 1495675396 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) +system.membus.respLayer2.occupancy 27962648500 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 1.2 # Layer utilization (%) +system.l2c.replacements 63244 # number of replacements +system.l2c.tagsinuse 50337.430960 # Cycle average of tags in use +system.l2c.total_refs 1749337 # Total number of references to valid blocks. +system.l2c.sampled_refs 128639 # Sample count of references to valid blocks. +system.l2c.avg_refs 13.598808 # Average number of references to valid blocks. +system.l2c.warmup_cycle 2374950539000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 36831.801957 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.dtb.walker 0.000018 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.itb.walker 0.000124 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 5149.319270 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 3787.835363 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 0.993318 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 800.097709 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 742.779862 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.dtb.walker 5.892734 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.inst 1445.756642 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.data 1597.659994 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.561938 # Average percentage of cache occupancy +system.l2c.occ_blocks::cpu0.inst 5222.807479 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 3773.258681 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 0.993312 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 729.926692 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 767.531716 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.dtb.walker 5.853930 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.inst 1434.252547 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.data 1571.004504 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.562009 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.078572 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.057798 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.079694 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.057575 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.012209 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.011334 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.dtb.walker 0.000090 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.inst 0.022060 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.data 0.024378 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.768394 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 8872 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3222 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 463074 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 169165 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 2536 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1092 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 132302 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 65381 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 18053 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 4139 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 283993 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 138836 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1290665 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 597754 # number of Writeback hits -system.l2c.Writeback_hits::total 597754 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 13 # number of UpgradeReq hits +system.l2c.occ_percent::cpu1.inst 0.011138 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.011712 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.dtb.walker 0.000089 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.inst 0.021885 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.data 0.023972 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.768088 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 9056 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 3360 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 461135 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 166289 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 2625 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 1208 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 135286 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 65788 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 18369 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 4267 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 282351 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 141179 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1290913 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 597640 # number of Writeback hits +system.l2c.Writeback_hits::total 597640 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 14 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 4 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu2.data 13 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 30 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu2.data 4 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 4 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 60607 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 19371 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 33591 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 113569 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 8872 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3222 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 463074 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 229772 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 2536 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 1092 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 132302 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 84752 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 18053 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 4139 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 283993 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 172427 # number of demand (read+write) hits -system.l2c.demand_hits::total 1404234 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 8872 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 3222 # number of overall hits -system.l2c.overall_hits::cpu0.inst 463074 # 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average ReadReq mshr uncacheable latency @@ -654,438 +801,631 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. +system.toL2Bus.throughput 58868329 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 1038711 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 1038710 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 375940 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 375940 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 275281 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 1501 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1503 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 80190 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 80190 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 843862 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 2343005 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma 15512 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma 51160 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count 3253539 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 26980864 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 38469375 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma 21900 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma 84004 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size 65556143 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 141250094 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 100256 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 2175069728 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 1900577406 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 1863798035 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 10055959 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 30318675 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.throughput 48814240 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 12751762 # Transaction distribution +system.iobus.trans_dist::ReadResp 12751762 # Transaction distribution +system.iobus.trans_dist::WriteReq 2783 # Transaction distribution +system.iobus.trans_dist::WriteResp 2783 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 11428 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 3102 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 18 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 262 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 721384 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 736482 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 24772608 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 24772608 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart.pio 11428 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.realview_io.pio 3102 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.timer0.pio 18 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.timer1.pio 262 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.clcd.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.kmi0.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.kmi1.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.cf_ctrl.pio 721384 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.sp810_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.iocache.cpu_side 24772608 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 25509090 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 15392 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 6204 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 36 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 524 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 717707 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 740439 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 99090432 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::total 99090432 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart.pio 15392 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.realview_io.pio 6204 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.timer0.pio 36 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.timer1.pio 524 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.clcd.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.kmi0.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.kmi1.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 717707 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.sp810_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.iocache.cpu_side 99090432 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 99830871 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 117209202 # Total data (bytes) +system.iobus.reqLayer0.occupancy 7987000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 1551000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 18000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 131000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer4.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer5.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer6.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer7.occupancy 361193000 # Layer occupancy (ticks) +system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 12386304000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%) +system.iobus.respLayer0.occupancy 733699000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer1.occupancy 24772608000 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 1.0 # Layer utilization (%) system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 8064741 # DTB read hits -system.cpu0.dtb.read_misses 6215 # DTB read misses -system.cpu0.dtb.write_hits 6627061 # DTB write hits -system.cpu0.dtb.write_misses 2040 # DTB write misses +system.cpu0.dtb.read_hits 8064428 # DTB read hits +system.cpu0.dtb.read_misses 6238 # DTB read misses +system.cpu0.dtb.write_hits 6663212 # DTB write hits +system.cpu0.dtb.write_misses 2045 # DTB write misses system.cpu0.dtb.flush_tlb 279 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 690 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 678 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5695 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 5690 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 121 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 114 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 212 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 8070956 # DTB read accesses -system.cpu0.dtb.write_accesses 6629101 # DTB write accesses +system.cpu0.dtb.read_accesses 8070666 # DTB read accesses +system.cpu0.dtb.write_accesses 6665257 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14691802 # DTB hits -system.cpu0.dtb.misses 8255 # DTB misses -system.cpu0.dtb.accesses 14700057 # DTB accesses -system.cpu0.itb.inst_hits 32689341 # ITB inst hits -system.cpu0.itb.inst_misses 3490 # ITB inst misses +system.cpu0.dtb.hits 14727640 # DTB hits +system.cpu0.dtb.misses 8283 # DTB misses +system.cpu0.dtb.accesses 14735923 # DTB accesses +system.cpu0.itb.inst_hits 32885888 # ITB inst hits +system.cpu0.itb.inst_misses 3493 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 279 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 690 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 678 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2596 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2597 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 32692831 # ITB inst accesses -system.cpu0.itb.hits 32689341 # DTB hits -system.cpu0.itb.misses 3490 # DTB misses -system.cpu0.itb.accesses 32692831 # DTB accesses -system.cpu0.numCycles 114004049 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 32889381 # ITB inst accesses +system.cpu0.itb.hits 32885888 # DTB hits +system.cpu0.itb.misses 3493 # DTB misses +system.cpu0.itb.accesses 32889381 # DTB accesses +system.cpu0.numCycles 114194187 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 32197863 # Number of instructions committed -system.cpu0.committedOps 42390807 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 37541776 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5152 # Number of float alu accesses -system.cpu0.num_func_calls 1189364 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4237827 # number of instructions that are conditional controls -system.cpu0.num_int_insts 37541776 # number of integer instructions -system.cpu0.num_fp_insts 5152 # number of float instructions -system.cpu0.num_int_register_reads 191249726 # number of times the integer registers were read -system.cpu0.num_int_register_writes 39627279 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3662 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1492 # number of times the floating registers were written -system.cpu0.num_mem_refs 15356244 # number of memory refs -system.cpu0.num_load_insts 8432602 # Number of load instructions -system.cpu0.num_store_insts 6923642 # Number of store instructions -system.cpu0.num_idle_cycles 13418877123.276752 # Number of idle cycles -system.cpu0.num_busy_cycles -13304873074.276752 # Number of busy cycles -system.cpu0.not_idle_fraction -116.705268 # Percentage of non-idle cycles -system.cpu0.idle_fraction 117.705268 # Percentage of idle cycles +system.cpu0.committedInsts 32400694 # Number of instructions committed +system.cpu0.committedOps 42604041 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 37748945 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5021 # Number of float alu accesses +system.cpu0.num_func_calls 1185552 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4241024 # number of instructions that are conditional controls +system.cpu0.num_int_insts 37748945 # number of integer instructions +system.cpu0.num_fp_insts 5021 # number of float instructions +system.cpu0.num_int_register_reads 192241357 # number of times the integer registers were read +system.cpu0.num_int_register_writes 39867524 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3591 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1432 # number of times the floating registers were written +system.cpu0.num_mem_refs 15390684 # number of memory refs +system.cpu0.num_load_insts 8430090 # Number of load instructions +system.cpu0.num_store_insts 6960594 # Number of store instructions +system.cpu0.num_idle_cycles 13437222906.022394 # Number of idle cycles +system.cpu0.num_busy_cycles -13323028719.022394 # Number of busy cycles +system.cpu0.not_idle_fraction -116.669938 # Percentage of non-idle cycles +system.cpu0.idle_fraction 117.669938 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 82893 # number of quiesce instructions executed -system.cpu0.icache.replacements 891776 # number of replacements -system.cpu0.icache.tagsinuse 511.602850 # Cycle average of tags in use -system.cpu0.icache.total_refs 44220417 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 892288 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 49.558458 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 8123363500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 478.597837 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 17.659572 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu2.inst 15.345442 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.934761 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu1.inst 0.034491 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu2.inst 0.029972 # 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average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11873.390437 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11783.243056 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11595.064888 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11873.390437 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11783.243056 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 629954 # number of replacements +system.cpu0.dcache.replacements 629902 # number of replacements system.cpu0.dcache.tagsinuse 511.997116 # Cycle average of tags in use -system.cpu0.dcache.total_refs 23213851 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 630466 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 36.820147 # Average number of references to valid blocks. +system.cpu0.dcache.total_refs 23235714 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 630414 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 36.857865 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 21763000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 495.756165 # Average occupied blocks per requestor -system.cpu0.dcache.occ_blocks::cpu1.data 9.709007 # Average occupied blocks per requestor -system.cpu0.dcache.occ_blocks::cpu2.data 6.531944 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.968274 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::cpu1.data 0.018963 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::cpu2.data 0.012758 # Average percentage of cache occupancy +system.cpu0.dcache.occ_blocks::cpu0.data 495.218177 # Average occupied blocks per requestor +system.cpu0.dcache.occ_blocks::cpu1.data 10.352055 # Average occupied blocks per requestor +system.cpu0.dcache.occ_blocks::cpu2.data 6.426883 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.967223 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::cpu1.data 0.020219 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::cpu2.data 0.012553 # Average percentage of cache occupancy system.cpu0.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6946152 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 1881152 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 4479308 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13306612 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5948925 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 1341191 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 2128617 # 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number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6375 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 1725 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 3870 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 11970 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu2.data 4 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 4 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 336449 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 94377 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 885315 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1316141 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 336449 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 94377 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 885315 # number of overall misses -system.cpu0.dcache.overall_misses::total 1316141 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 903782500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 4105019000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5008801500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 727658500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 18527388398 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 19255046898 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 22582000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 52040000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 74622000 # 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number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 35737 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 73917 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 247397 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13231526 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 3316720 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 7493240 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 24041486 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13231526 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 3316720 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 7493240 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 24041486 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.023777 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033321 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.059720 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.037505 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027349 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.021547 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.220126 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.078074 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.046282 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.048269 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.050510 # 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miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.216832 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.076367 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.045966 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.049609 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.049996 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.047733 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000027 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000008 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025239 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.028508 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.116659 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.054034 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.025239 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.028508 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.116659 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.054034 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14248.784565 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14514.852880 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 9829.250955 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 30634.922499 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 35581.599196 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 27719.242590 # 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average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 28616.656810 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 20571.757912 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 10003 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 3430 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 1178 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 49 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8.491511 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 70 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 597754 # number of writebacks -system.cpu0.dcache.writebacks::total 597754 # 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number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 71978923634 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033321 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.028970 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014672 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021547 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019429 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008082 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.048269 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.044950 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020668 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000054 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000016 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028455 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.025495 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.011872 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028455 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.025495 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.011872 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11938.226767 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13012.144312 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12668.859595 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22637.159303 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 27034.857496 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25461.720983 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11091.014493 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11689.459930 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11489.746566 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 597640 # number of writebacks +system.cpu0.dcache.writebacks::total 597640 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 147191 # 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number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 5130878455 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27438525500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 28895903000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 56334428500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1439019500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 13930302419 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 15369321919 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28877545000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 42826205419 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 71703750419 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033512 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.029420 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014862 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021489 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019306 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007991 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.049609 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.044631 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020906 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000027 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000008 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028508 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.025777 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.011943 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028508 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.025777 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.011943 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12248.784565 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12932.789238 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12715.795501 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28634.922499 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32101.463845 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30835.831035 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11121.992166 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11498.407590 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11370.013934 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 15286.425718 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16904.712140 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16369.598173 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 15286.425718 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16904.712140 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16369.598173 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 17389.405214 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18103.197085 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17867.042013 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17389.405214 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 18103.197085 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17867.042013 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1098,219 +1438,219 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 2161402 # DTB read hits -system.cpu1.dtb.read_misses 2114 # DTB read misses -system.cpu1.dtb.write_hits 1457218 # DTB write hits -system.cpu1.dtb.write_misses 386 # DTB write misses +system.cpu1.dtb.read_hits 2160353 # DTB read hits +system.cpu1.dtb.read_misses 2072 # DTB read misses +system.cpu1.dtb.write_hits 1463428 # DTB write hits +system.cpu1.dtb.write_misses 375 # DTB write misses system.cpu1.dtb.flush_tlb 277 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 237 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 240 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1711 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1741 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.dtb.prefetch_faults 41 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 79 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 2163516 # DTB read accesses -system.cpu1.dtb.write_accesses 1457604 # DTB write accesses +system.cpu1.dtb.perms_faults 78 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 2162425 # DTB read accesses +system.cpu1.dtb.write_accesses 1463803 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 3618620 # DTB hits -system.cpu1.dtb.misses 2500 # DTB misses -system.cpu1.dtb.accesses 3621120 # DTB accesses -system.cpu1.itb.inst_hits 8380082 # ITB inst hits -system.cpu1.itb.inst_misses 1132 # ITB inst misses +system.cpu1.dtb.hits 3623781 # DTB hits +system.cpu1.dtb.misses 2447 # DTB misses +system.cpu1.dtb.accesses 3626228 # DTB accesses +system.cpu1.itb.inst_hits 8343384 # ITB inst hits +system.cpu1.itb.inst_misses 1170 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 277 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 237 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 240 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 830 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 867 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8381214 # ITB inst accesses -system.cpu1.itb.hits 8380082 # DTB hits -system.cpu1.itb.misses 1132 # DTB misses -system.cpu1.itb.accesses 8381214 # DTB accesses -system.cpu1.numCycles 574618954 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 8344554 # ITB inst accesses +system.cpu1.itb.hits 8343384 # DTB hits +system.cpu1.itb.misses 1170 # DTB misses +system.cpu1.itb.accesses 8344554 # DTB accesses +system.cpu1.numCycles 576594127 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 8175033 # Number of instructions committed -system.cpu1.committedOps 10410069 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 9322021 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 1998 # Number of float alu accesses -system.cpu1.num_func_calls 315375 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1140852 # number of instructions that are conditional controls -system.cpu1.num_int_insts 9322021 # number of integer instructions -system.cpu1.num_fp_insts 1998 # number of float instructions -system.cpu1.num_int_register_reads 53738545 # number of times the integer registers were read -system.cpu1.num_int_register_writes 10097471 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 1549 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 450 # number of times the floating registers were written -system.cpu1.num_mem_refs 3791152 # number of memory refs -system.cpu1.num_load_insts 2256757 # Number of load instructions -system.cpu1.num_store_insts 1534395 # Number of store instructions -system.cpu1.num_idle_cycles 532868716.793879 # Number of idle cycles -system.cpu1.num_busy_cycles 41750237.206121 # Number of busy cycles -system.cpu1.not_idle_fraction 0.072657 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.927343 # Percentage of idle cycles +system.cpu1.committedInsts 8139213 # Number of instructions committed +system.cpu1.committedOps 10387341 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 9296011 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 2143 # Number of float alu accesses +system.cpu1.num_func_calls 319457 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1149983 # number of instructions that are conditional controls +system.cpu1.num_int_insts 9296011 # number of integer instructions +system.cpu1.num_fp_insts 2143 # number of float instructions +system.cpu1.num_int_register_reads 53626328 # number of times the integer registers were read +system.cpu1.num_int_register_writes 10059981 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 1630 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 514 # number of times the floating registers were written +system.cpu1.num_mem_refs 3800206 # number of memory refs +system.cpu1.num_load_insts 2257531 # Number of load instructions +system.cpu1.num_store_insts 1542675 # Number of store instructions +system.cpu1.num_idle_cycles 550949024.070645 # Number of idle cycles +system.cpu1.num_busy_cycles 25645102.929355 # Number of busy cycles +system.cpu1.not_idle_fraction 0.044477 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.955523 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 4722397 # Number of BP lookups -system.cpu2.branchPred.condPredicted 3838487 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 221435 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 2952816 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 2527233 # Number of BTB hits +system.cpu2.branchPred.lookups 4706679 # Number of BP lookups +system.cpu2.branchPred.condPredicted 3828645 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 220746 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 3114772 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 2519361 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 85.587216 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 411089 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 21408 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 80.884283 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 411150 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 21524 # Number of incorrect RAS predictions. system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 10881575 # DTB read hits -system.cpu2.dtb.read_misses 22640 # DTB read misses -system.cpu2.dtb.write_hits 3277177 # DTB write hits -system.cpu2.dtb.write_misses 5849 # DTB write misses +system.cpu2.dtb.read_hits 10881090 # DTB read hits +system.cpu2.dtb.read_misses 22334 # DTB read misses +system.cpu2.dtb.write_hits 3233578 # DTB write hits +system.cpu2.dtb.write_misses 5962 # DTB write misses system.cpu2.dtb.flush_tlb 276 # Number of times complete TLB was flushed system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.dtb.flush_tlb_mva_asid 512 # Number of times TLB was flushed by MVA & ASID +system.cpu2.dtb.flush_tlb_mva_asid 521 # Number of times TLB was flushed by MVA & ASID system.cpu2.dtb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 2319 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 814 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 160 # Number of TLB faults due to prefetch +system.cpu2.dtb.flush_entries 2292 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 695 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 165 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 478 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 10904215 # DTB read accesses -system.cpu2.dtb.write_accesses 3283026 # DTB write accesses +system.cpu2.dtb.perms_faults 471 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 10903424 # DTB read accesses +system.cpu2.dtb.write_accesses 3239540 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 14158752 # DTB hits -system.cpu2.dtb.misses 28489 # DTB misses -system.cpu2.dtb.accesses 14187241 # DTB accesses -system.cpu2.itb.inst_hits 4065885 # ITB inst hits -system.cpu2.itb.inst_misses 4502 # ITB inst misses +system.cpu2.dtb.hits 14114668 # DTB hits +system.cpu2.dtb.misses 28296 # DTB misses +system.cpu2.dtb.accesses 14142964 # DTB accesses +system.cpu2.itb.inst_hits 3988029 # ITB inst hits +system.cpu2.itb.inst_misses 4597 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses system.cpu2.itb.flush_tlb 276 # Number of times complete TLB was flushed system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.itb.flush_tlb_mva_asid 512 # Number of times TLB was flushed by MVA & ASID +system.cpu2.itb.flush_tlb_mva_asid 521 # Number of times TLB was flushed by MVA & ASID system.cpu2.itb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 1576 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_entries 1713 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 1005 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 994 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 4070387 # ITB inst accesses -system.cpu2.itb.hits 4065885 # DTB hits -system.cpu2.itb.misses 4502 # DTB misses -system.cpu2.itb.accesses 4070387 # DTB accesses -system.cpu2.numCycles 88259873 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 3992626 # ITB inst accesses +system.cpu2.itb.hits 3988029 # DTB hits +system.cpu2.itb.misses 4597 # DTB misses +system.cpu2.itb.accesses 3992626 # DTB accesses +system.cpu2.numCycles 88357796 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9453176 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 32426467 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 4722397 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 2938322 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 6835194 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 1814499 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 51467 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.BlockedCycles 18689225 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 182 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 953 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 32914 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 708494 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 306 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 4064555 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 309850 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 1926 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 37018169 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.050897 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.436881 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9310481 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 32575007 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 4706679 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 2930511 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 6844695 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 1834626 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 50535 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.BlockedCycles 18792292 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 211 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 834 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 32689 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 721380 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 412 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 3986556 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 271694 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 2030 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 37012176 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.054575 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.442886 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 30188064 81.55% 81.55% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 383346 1.04% 82.58% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 510640 1.38% 83.96% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 813031 2.20% 86.16% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 657801 1.78% 87.94% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 343878 0.93% 88.87% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1012409 2.73% 91.60% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 238466 0.64% 92.25% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 2870534 7.75% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 30172484 81.52% 81.52% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 383589 1.04% 82.56% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 509700 1.38% 83.93% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 816595 2.21% 86.14% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 649845 1.76% 87.90% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 340688 0.92% 88.82% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1002283 2.71% 91.52% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 233105 0.63% 92.15% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 2903887 7.85% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 37018169 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.053506 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.367398 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 10067654 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 19275483 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 6184949 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 295259 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1193811 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 613325 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 53657 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 36756215 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 182103 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 1193811 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 10642239 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 6572797 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 11156885 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 5885889 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 1565553 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 34514239 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 2456 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 419835 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 882809 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.FullRegisterEvents 92 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 37003284 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 157776579 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 157748805 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 27774 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 25809996 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 11193287 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 230807 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 207161 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3357083 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6535673 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3850744 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 536963 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 792176 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 31747463 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 511528 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 34289699 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 55083 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 7395646 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 19879544 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 155324 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 37018169 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 0.926294 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.580927 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 37012176 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.053268 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.368672 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 9923582 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 19398911 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 6192413 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 289708 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1206624 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 608704 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 53227 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 36668894 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 179672 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 1206624 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 10457732 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 6796532 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 11090349 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 5929465 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 1530564 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 34717207 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 2441 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 375073 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 892617 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.FullRegisterEvents 118 # Number of times there has been no free registers +system.cpu2.rename.RenamedOperands 37295857 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 158754403 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 158727276 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 27127 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 25598469 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 11697387 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 231672 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 208131 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3300393 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6518889 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3789656 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 530954 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 691805 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 31588093 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 511099 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 34136489 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 54725 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 7434189 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 19599124 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 154239 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 37012176 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 0.922304 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.578312 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 24442328 66.03% 66.03% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 3909913 10.56% 76.59% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 2354045 6.36% 82.95% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 1974122 5.33% 88.28% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 2799200 7.56% 95.84% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 884316 2.39% 98.23% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 484064 1.31% 99.54% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 134882 0.36% 99.90% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 35299 0.10% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 24481195 66.14% 66.14% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 3912173 10.57% 76.71% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 2318887 6.27% 82.98% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 2014061 5.44% 88.42% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 2743513 7.41% 95.83% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 884212 2.39% 98.22% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 492586 1.33% 99.55% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 130661 0.35% 99.91% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 34888 0.09% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 37018169 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 37012176 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 18550 1.21% 1.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 1.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 18493 1.21% 1.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 1 0.00% 1.21% # attempts to use FU when none available system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.21% # attempts to use FU when none available system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.21% # attempts to use FU when none available system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.21% # attempts to use FU when none available @@ -1338,148 +1678,148 @@ system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.21% # at system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.21% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.21% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 1408407 91.61% 92.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 110486 7.19% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 1405660 91.60% 92.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 110389 7.19% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 61448 0.18% 0.18% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 19376629 56.51% 56.69% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 26012 0.08% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 8 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 8 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 381 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 11380471 33.19% 89.95% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3444734 10.05% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 61311 0.18% 0.18% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 19306288 56.56% 56.74% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 26277 0.08% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 7 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 1 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 6 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 369 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 11344167 33.23% 90.05% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3398057 9.95% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 34289699 # Type of FU issued -system.cpu2.iq.rate 0.388508 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 1537443 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.044837 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 107211457 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 39659859 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 27420215 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 6989 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 3825 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 3150 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 35761973 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 3721 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 208327 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 34136489 # Type of FU issued +system.cpu2.iq.rate 0.386344 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 1534543 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.044953 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 106895526 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 39538518 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 27366143 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 7075 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 3717 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 3145 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 35605938 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 3783 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 206498 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1579914 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1893 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 9373 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 582518 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1561517 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1841 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 9166 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 566678 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 5363105 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 352533 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 5349938 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 380447 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1193811 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 4877812 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 91796 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 32340028 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 60265 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6535673 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3850744 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 369403 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 31610 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 2472 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 9373 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 105135 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 88586 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 193721 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 33297921 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 11093060 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 991778 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 1206624 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 5097630 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 92333 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 32182024 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 61203 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6518889 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3789656 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 368677 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 31621 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 2335 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 9166 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 105355 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 88176 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 193531 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 33238932 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 11092763 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 897557 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 81037 # number of nop insts executed -system.cpu2.iew.exec_refs 14504508 # number of memory reference insts executed -system.cpu2.iew.exec_branches 3695173 # Number of branches executed -system.cpu2.iew.exec_stores 3411448 # Number of stores executed -system.cpu2.iew.exec_rate 0.377271 # Inst execution rate -system.cpu2.iew.wb_sent 32878469 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 27423365 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 15687848 # num instructions producing a value -system.cpu2.iew.wb_consumers 28539684 # num instructions consuming a value +system.cpu2.iew.exec_nop 82832 # number of nop insts executed +system.cpu2.iew.exec_refs 14457569 # number of memory reference insts executed +system.cpu2.iew.exec_branches 3671446 # Number of branches executed +system.cpu2.iew.exec_stores 3364806 # Number of stores executed +system.cpu2.iew.exec_rate 0.376186 # Inst execution rate +system.cpu2.iew.wb_sent 32811396 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 27369288 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 15602510 # num instructions producing a value +system.cpu2.iew.wb_consumers 28268763 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.310712 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.549685 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.309755 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.551935 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 7335381 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 356204 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 168508 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 35824220 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 0.690433 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.719118 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 7374898 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 356860 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 168297 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 35805367 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 0.685358 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.714033 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 27176930 75.86% 75.86% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4185525 11.68% 87.55% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1261410 3.52% 91.07% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 649563 1.81% 92.88% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 571804 1.60% 94.48% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 316250 0.88% 95.36% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 400543 1.12% 96.48% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 292091 0.82% 97.29% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 970104 2.71% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 27231349 76.05% 76.05% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4142496 11.57% 87.62% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1257531 3.51% 91.14% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 645964 1.80% 92.94% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 562986 1.57% 94.51% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 317406 0.89% 95.40% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 386660 1.08% 96.48% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 302677 0.85% 97.32% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 958298 2.68% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 35824220 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 20010366 # Number of instructions committed -system.cpu2.commit.committedOps 24734227 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 35805367 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 19842604 # Number of instructions committed +system.cpu2.commit.committedOps 24539507 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8223985 # Number of memory references committed -system.cpu2.commit.loads 4955759 # Number of loads committed -system.cpu2.commit.membars 94186 # Number of memory barriers committed -system.cpu2.commit.branches 3169280 # Number of branches committed -system.cpu2.commit.fp_insts 3103 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 21954082 # Number of committed integer instructions. -system.cpu2.commit.function_calls 294910 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 970104 # number cycles where commit BW limit reached +system.cpu2.commit.refs 8180350 # Number of memory references committed +system.cpu2.commit.loads 4957372 # Number of loads committed +system.cpu2.commit.membars 94561 # Number of memory barriers committed +system.cpu2.commit.branches 3152552 # Number of branches committed +system.cpu2.commit.fp_insts 3091 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 21772655 # Number of committed integer instructions. +system.cpu2.commit.function_calls 294654 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 958298 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 66398809 # The number of ROB reads -system.cpu2.rob.rob_writes 65374131 # The number of ROB writes -system.cpu2.timesIdled 360148 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 51241704 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 3567295976 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 19956402 # Number of Instructions Simulated -system.cpu2.committedOps 24680263 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 19956402 # Number of Instructions Simulated -system.cpu2.cpi 4.422635 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 4.422635 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.226110 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.226110 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 153855471 # number of integer regfile reads -system.cpu2.int_regfile_writes 29258344 # number of integer regfile writes -system.cpu2.fp_regfile_reads 22383 # number of floating regfile reads -system.cpu2.fp_regfile_writes 20838 # number of floating regfile writes -system.cpu2.misc_regfile_reads 9035132 # number of misc regfile reads -system.cpu2.misc_regfile_writes 240694 # number of misc regfile writes +system.cpu2.rob.rob_reads 66237138 # The number of ROB reads +system.cpu2.rob.rob_writes 65080734 # The number of ROB writes +system.cpu2.timesIdled 362582 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 51345620 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 3559271384 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 19787102 # Number of Instructions Simulated +system.cpu2.committedOps 24484005 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 19787102 # Number of Instructions Simulated +system.cpu2.cpi 4.465424 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 4.465424 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.223943 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.223943 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 153570043 # number of integer regfile reads +system.cpu2.int_regfile_writes 29228694 # number of integer regfile writes +system.cpu2.fp_regfile_reads 22407 # number of floating regfile reads +system.cpu2.fp_regfile_writes 20832 # number of floating regfile writes +system.cpu2.misc_regfile_reads 8993137 # number of misc regfile reads +system.cpu2.misc_regfile_writes 241651 # number of misc regfile writes system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. @@ -1494,10 +1834,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 981038235668 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 981038235668 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 981038235668 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 981038235668 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1181598504500 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1181598504500 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1181598504500 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1181598504500 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index 8bb759cd2..1abf69682 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -1,163 +1,151 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.543311 # Number of seconds simulated -sim_ticks 2543310963000 # Number of ticks simulated -final_tick 2543310963000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.548434 # Number of seconds simulated +sim_ticks 2548433543500 # Number of ticks simulated +final_tick 2548433543500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 64896 # Simulator instruction rate (inst/s) -host_op_rate 83503 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2736674491 # Simulator tick rate (ticks/s) -host_mem_usage 401948 # Number of bytes of host memory used -host_seconds 929.34 # Real time elapsed on the host -sim_insts 60310426 # Number of instructions simulated -sim_ops 77602848 # Number of ops (including micro ops) simulated -system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 62524 # Simulator instruction rate (inst/s) +host_op_rate 80452 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2641694597 # Simulator tick rate (ticks/s) +host_mem_usage 403600 # Number of bytes of host memory used +host_seconds 964.70 # Real time elapsed on the host +sim_insts 60316814 # Number of instructions simulated +sim_ops 77611972 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 2112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 1152 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 505600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4226512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 293504 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4868124 # Number of bytes read from this memory -system.physmem.bytes_read::total 131007148 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 505600 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 293504 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 799104 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3786304 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1344512 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1671600 # Number of bytes written to this memory -system.physmem.bytes_written::total 6802416 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 441408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4859600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 1408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 357888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4231256 # Number of bytes read from this memory +system.physmem.bytes_read::total 131003368 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 441408 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 357888 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 799296 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3783552 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1678512 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1337588 # Number of bytes written to this memory +system.physmem.bytes_written::total 6799652 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 33 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 18 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 7900 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 66073 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 10 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 4586 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 76071 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15293491 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59161 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 336128 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 417900 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813189 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47619237 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 830 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu0.inst 6897 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 75965 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 22 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 5592 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 66119 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15293431 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59118 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 419628 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 334397 # Number of write requests responded to by this memory +system.physmem.num_writes::total 813143 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47523518 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 452 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 198796 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1661815 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 252 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 115402 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1914089 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51510472 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 198796 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 115402 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314198 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1488730 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 528646 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 657253 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2674630 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1488730 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47619237 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 830 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 173208 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1906897 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 552 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 140435 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1660336 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51405448 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 173208 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 140435 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 313642 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1484658 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 658645 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 524867 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2668169 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1484658 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47523518 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 452 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 198796 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2190461 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 252 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 115402 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2571343 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54185102 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15293491 # Total number of read requests seen -system.physmem.writeReqs 813189 # Total number of write requests seen -system.physmem.cpureqs 218466 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 978783424 # Total number of bytes read from memory -system.physmem.bytesWritten 52044096 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 131007148 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6802416 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 14 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4673 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 956233 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 955732 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 955671 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 956488 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 956264 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 955447 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 955562 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 956165 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 956089 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 955603 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 955529 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 955926 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 956033 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 955432 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 955318 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 955985 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50834 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 50412 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50437 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51163 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50909 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50191 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50279 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50860 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51365 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 50901 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50804 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51194 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51250 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 50730 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 50631 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51229 # Track writes on a per bank basis +system.physmem.bw_total::cpu0.inst 173208 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2565541 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 552 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 140435 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2185203 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54073617 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15293431 # Total number of read requests seen +system.physmem.writeReqs 813143 # Total number of write requests seen +system.physmem.cpureqs 218375 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 978779584 # Total number of bytes read from memory +system.physmem.bytesWritten 52041152 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 131003368 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6799652 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 11 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4684 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 955869 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 955530 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 955690 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 955877 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 955758 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 955993 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 955879 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 955787 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 956236 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 955946 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 955507 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 955113 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 956214 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 955973 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 956070 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 955978 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 49130 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 48908 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50977 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51082 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 51006 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 51266 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 51260 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51202 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51317 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51099 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50759 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 50417 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51356 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 50974 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51268 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51122 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 32475 # Number of times wr buffer was full causing retry -system.physmem.totGap 2543309787500 # Total gap between requests +system.physmem.numWrRetry 32387 # Number of times wr buffer was full causing retry +system.physmem.totGap 2548432371500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 43 # Categorize read packet sizes +system.physmem.readPktSize::2 42 # Categorize read packet sizes system.physmem.readPktSize::3 15138816 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154632 # Categorize read packet sizes +system.physmem.readPktSize::6 154573 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 754028 # Categorize write packet sizes +system.physmem.writePktSize::2 754025 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 59161 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1054822 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 991773 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 961430 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3605165 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2718295 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2722207 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2700301 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 59966 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 59368 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 110015 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 160547 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 109964 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 9981 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 9914 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 10593 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 9111 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59118 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1060830 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 986831 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 991569 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3738549 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2806537 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2806300 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2762834 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 15152 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 14911 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 27618 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 40328 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 27612 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 3599 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 3593 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 4293 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 2835 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -168,282 +156,517 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2745 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2838 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2865 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2928 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2923 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2925 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2921 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2923 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 2918 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35379 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35368 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35348 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35332 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35299 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2773 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2880 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2926 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2970 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2958 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 2959 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 2966 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 2975 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35380 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35359 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35346 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35321 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35310 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35292 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 35285 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35274 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32651 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32612 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32534 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 32507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 32498 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 32487 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 32480 # What write queue length does an incoming req see -system.physmem.totQLat 346644691750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 439813624250 # Sum of mem lat for all requests -system.physmem.totBusLat 76467385000 # Total cycles spent in databus access -system.physmem.totBankLat 16701547500 # Total cycles spent in bank access -system.physmem.avgQLat 22666.18 # Average queueing delay per request -system.physmem.avgBankLat 1092.07 # Average bank access latency per request +system.physmem.wrQLenPdf::17 35276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35253 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35225 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32740 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32609 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32551 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32489 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32481 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32471 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 32457 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 32434 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 32415 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 40040 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 25744.741658 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 2072.132686 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 32880.697508 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-95 6923 17.29% 17.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-159 3475 8.68% 25.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-223 2293 5.73% 31.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-287 1778 4.44% 36.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-351 1271 3.17% 39.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-415 1070 2.67% 41.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-479 793 1.98% 43.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-543 869 2.17% 46.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-607 551 1.38% 47.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-671 489 1.22% 48.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-735 420 1.05% 49.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-799 393 0.98% 50.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-863 261 0.65% 51.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-927 255 0.64% 52.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-991 183 0.46% 52.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1055 282 0.70% 53.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1119 123 0.31% 53.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1183 156 0.39% 53.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1247 102 0.25% 54.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1311 126 0.31% 54.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1375 80 0.20% 54.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1439 383 0.96% 55.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1503 613 1.53% 57.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1567 451 1.13% 58.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1631 81 0.20% 58.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1695 160 0.40% 58.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1759 53 0.13% 59.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1823 109 0.27% 59.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1887 41 0.10% 59.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1951 74 0.18% 59.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-2015 31 0.08% 59.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2079 65 0.16% 59.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2143 23 0.06% 59.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2207 42 0.10% 59.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2271 15 0.04% 60.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2335 29 0.07% 60.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2399 18 0.04% 60.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2463 27 0.07% 60.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2527 12 0.03% 60.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2591 20 0.05% 60.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2655 7 0.02% 60.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2719 22 0.05% 60.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2783 8 0.02% 60.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2847 11 0.03% 60.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2911 11 0.03% 60.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2975 16 0.04% 60.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3039 6 0.01% 60.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3103 19 0.05% 60.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3167 8 0.02% 60.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3231 9 0.02% 60.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3295 8 0.02% 60.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3359 9 0.02% 60.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3423 6 0.01% 60.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3487 6 0.01% 60.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3551 4 0.01% 60.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3615 9 0.02% 60.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3679 4 0.01% 60.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3743 9 0.02% 60.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3807 6 0.01% 60.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3871 4 0.01% 60.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3935 3 0.01% 60.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3999 10 0.02% 60.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4063 5 0.01% 60.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4127 40 0.10% 60.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4191 3 0.01% 60.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4255 5 0.01% 60.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4319 4 0.01% 60.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4383 4 0.01% 60.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4447 3 0.01% 60.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4511 2 0.00% 60.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4575 3 0.01% 60.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4639 3 0.01% 60.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4703 2 0.00% 60.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4767 5 0.01% 60.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4831 1 0.00% 60.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4895 2 0.00% 60.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4959 4 0.01% 60.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-5023 3 0.01% 61.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5087 2 0.00% 61.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5151 5 0.01% 61.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5279 6 0.01% 61.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5343 1 0.00% 61.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5407 2 0.00% 61.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5471 5 0.01% 61.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5535 7 0.02% 61.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5791 1 0.00% 61.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5855 1 0.00% 61.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5919 3 0.01% 61.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6047 2 0.00% 61.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6111 1 0.00% 61.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6175 6 0.01% 61.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6239 1 0.00% 61.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6303 2 0.00% 61.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6367 1 0.00% 61.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6431 3 0.01% 61.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6495 1 0.00% 61.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6559 5 0.01% 61.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6623 2 0.00% 61.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6687 2 0.00% 61.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6751 2 0.00% 61.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6815 20 0.05% 61.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6879 2 0.00% 61.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6943 1 0.00% 61.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7071 2 0.00% 61.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7135 3 0.01% 61.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7199 2 0.00% 61.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7391 1 0.00% 61.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7455 9 0.02% 61.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7519 1 0.00% 61.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7583 4 0.01% 61.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7711 7 0.02% 61.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7839 3 0.01% 61.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7903 3 0.01% 61.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7967 4 0.01% 61.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8031 1 0.00% 61.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8095 7 0.02% 61.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8159 2 0.00% 61.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8223 309 0.77% 62.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9247 1 0.00% 62.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9664-9695 1 0.00% 62.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10271 17 0.04% 62.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12319 1 0.00% 62.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12831 1 0.00% 62.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14239 1 0.00% 62.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16896-16927 1 0.00% 62.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18944-18975 1 0.00% 62.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21312-21343 1 0.00% 62.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24607 1 0.00% 62.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26399 1 0.00% 62.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27679 1 0.00% 62.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-29983 1 0.00% 62.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30239 1 0.00% 62.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30592-30623 1 0.00% 62.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32031 1 0.00% 62.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32287 1 0.00% 62.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32799 2 0.00% 62.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33311 1 0.00% 62.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33567 1 0.00% 62.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33823 6 0.01% 62.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35328-35359 1 0.00% 62.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42944-42975 1 0.00% 62.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45632-45663 1 0.00% 62.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::53248-53279 1 0.00% 62.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::58112-58143 1 0.00% 62.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::58624-58655 1 0.00% 62.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::61120-61151 1 0.00% 62.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65536-65567 14762 36.87% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::123712-123743 1 0.00% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::130048-130079 1 0.00% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::130944-130975 1 0.00% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::131072-131103 346 0.86% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::131200-131231 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::132096-132127 4 0.01% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::136576-136607 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::161280-161311 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::168384-168415 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::187392-187423 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::196608-196639 4 0.01% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 40040 # Bytes accessed per row activation +system.physmem.totQLat 308881805250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 400754322750 # Sum of mem lat for all requests +system.physmem.totBusLat 76467100000 # Total cycles spent in databus access +system.physmem.totBankLat 15405417500 # Total cycles spent in bank access +system.physmem.avgQLat 20197.04 # Average queueing delay per request +system.physmem.avgBankLat 1007.32 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 28758.25 # Average memory access latency -system.physmem.avgRdBW 384.85 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 20.46 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 51.51 # Average consumed read bandwidth in MB/s +system.physmem.avgMemAccLat 26204.36 # Average memory access latency +system.physmem.avgRdBW 384.07 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 20.42 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 51.41 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 2.67 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.17 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.17 # Average read queue length over time -system.physmem.avgWrQLen 1.13 # Average write queue length over time -system.physmem.readRowHits 15218324 # Number of row buffer hits during reads -system.physmem.writeRowHits 794497 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.51 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 97.70 # Row buffer hit rate for writes -system.physmem.avgGap 157904.04 # Average gap between requests -system.l2c.replacements 64400 # number of replacements -system.l2c.tagsinuse 51409.834545 # Cycle average of tags in use -system.l2c.total_refs 1903586 # Total number of references to valid blocks. -system.l2c.sampled_refs 129789 # Sample count of references to valid blocks. -system.l2c.avg_refs 14.666775 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2531435998500 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 36958.443874 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 20.878124 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.000349 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 5181.005742 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 3269.589268 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 7.697989 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 3013.641151 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 2958.578047 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.563941 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000319 # Average percentage of cache occupancy +system.physmem.busUtil 3.16 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.16 # Average read queue length over time +system.physmem.avgWrQLen 1.10 # Average write queue length over time +system.physmem.readRowHits 15267875 # Number of row buffer hits during reads +system.physmem.writeRowHits 798648 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.83 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 98.22 # Row buffer hit rate for writes +system.physmem.avgGap 158223.12 # Average gap between requests +system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 55014580 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16346067 # Transaction distribution +system.membus.trans_dist::ReadResp 16346070 # Transaction distribution +system.membus.trans_dist::WriteReq 763348 # Transaction distribution +system.membus.trans_dist::WriteResp 763348 # Transaction distribution +system.membus.trans_dist::Writeback 59118 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4682 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4684 # Transaction distribution +system.membus.trans_dist::ReadExReq 131411 # Transaction distribution +system.membus.trans_dist::ReadExResp 131411 # Transaction distribution +system.membus.trans_dist::LoadLockedReq 3 # Transaction distribution +system.membus.trans_dist::StoreCondReq 3 # Transaction distribution +system.membus.trans_dist::StoreCondResp 3 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382958 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1885766 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3790 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4272518 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.bridge.slave 2382958 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 32163398 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.realview.gic.pio 3790 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 34550150 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390333 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16692492 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7580 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 19090473 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.bridge.slave 2390333 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 137803020 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.realview.gic.pio 7580 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 140201001 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 140201001 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 1492522500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 17540815750 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.7 # Layer utilization (%) +system.membus.reqLayer3.occupancy 3583500 # Layer occupancy (ticks) +system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer5.occupancy 1500 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 4705924038 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.respLayer2.occupancy 34177393245 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 1.3 # Layer utilization (%) +system.l2c.replacements 64346 # number of replacements +system.l2c.tagsinuse 51424.069961 # Cycle average of tags in use +system.l2c.total_refs 1905385 # Total number of references to valid blocks. +system.l2c.sampled_refs 129735 # Sample count of references to valid blocks. +system.l2c.avg_refs 14.686746 # Average number of references to valid blocks. +system.l2c.warmup_cycle 2511358439500 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 36974.185132 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 11.366489 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 0.000367 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4621.370879 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 3355.179290 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 15.725461 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 3578.652286 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 2867.590058 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.564181 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.dtb.walker 0.000173 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # 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average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10003.573439 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 39988.226573 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 37119.935476 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 38432.465895 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 62932.787879 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 46625.500000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 43001.703766 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40475.095470 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 44757.096380 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 37683.798886 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 39359.547770 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 62932.787879 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 46625.500000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 43001.703766 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40475.095470 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 44757.096380 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 37683.798886 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 39359.547770 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56143.257661 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 55885.895105 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 56022.680137 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 84486.111111 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 61959.893837 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 56582.283589 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 74375 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60868.919886 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 56352.841447 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 56876.555548 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 84486.111111 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 61959.893837 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 56582.283589 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 74375 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60868.919886 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 56352.841447 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 56876.555548 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -634,680 +861,876 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 7600384 # Number of BP lookups -system.cpu0.branchPred.condPredicted 6061207 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 379102 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 4941026 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 4041960 # Number of BTB hits +system.toL2Bus.throughput 58505331 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2677704 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2677706 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 763348 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 763348 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 608398 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2950 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 10 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2960 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 246173 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 246173 # Transaction distribution +system.toL2Bus.trans_dist::LoadLockedReq 3 # Transaction distribution +system.toL2Bus.trans_dist::StoreCondReq 3 # Transaction distribution +system.toL2Bus.trans_dist::StoreCondResp 3 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 1969441 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 5798176 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma 37507 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma 149666 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count 7954790 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 62986112 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 85598825 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma 54648 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma 253968 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size 148893553 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 148893553 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 203396 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4965063678 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 4434793437 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 4469014832 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 23886909 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 86662497 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.throughput 48461480 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16322135 # Transaction distribution +system.iobus.trans_dist::ReadResp 16322135 # Transaction distribution +system.iobus.trans_dist::WriteReq 8160 # Transaction distribution +system.iobus.trans_dist::WriteResp 8160 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7940 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 522 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1030 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382958 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.realview_io.pio 7940 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.timer0.pio 522 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.timer1.pio 1030 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 32660590 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15880 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1044 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2060 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390333 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.realview_io.pio 15880 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.timer0.pio 1044 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.timer1.pio 2060 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 123500861 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 123500861 # Total data (bytes) +system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 3975000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 522000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 521000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) +system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) +system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks) +system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) +system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) +system.iobus.respLayer0.occupancy 2374798000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) +system.iobus.respLayer1.occupancy 30277632000 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 1.2 # Layer utilization (%) +system.cpu0.branchPred.lookups 7472736 # Number of BP lookups +system.cpu0.branchPred.condPredicted 5963732 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 379354 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 4914816 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 4037140 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 81.804063 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 728879 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 39033 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 82.142241 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 698266 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 38240 # Number of incorrect RAS predictions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 26040938 # DTB read hits -system.cpu0.dtb.read_misses 40555 # DTB read misses -system.cpu0.dtb.write_hits 5901951 # DTB write hits -system.cpu0.dtb.write_misses 9434 # DTB write misses -system.cpu0.dtb.flush_tlb 257 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 25723416 # DTB read hits +system.cpu0.dtb.read_misses 39440 # DTB read misses +system.cpu0.dtb.write_hits 6006462 # DTB write hits +system.cpu0.dtb.write_misses 9528 # DTB write misses +system.cpu0.dtb.flush_tlb 258 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 769 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5623 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1361 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 276 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 791 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 5597 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1333 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 268 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 633 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 26081493 # DTB read accesses -system.cpu0.dtb.write_accesses 5911385 # DTB write accesses +system.cpu0.dtb.perms_faults 680 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 25762856 # DTB read accesses +system.cpu0.dtb.write_accesses 6015990 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 31942889 # DTB hits -system.cpu0.dtb.misses 49989 # DTB misses -system.cpu0.dtb.accesses 31992878 # DTB accesses -system.cpu0.itb.inst_hits 6096045 # ITB inst hits -system.cpu0.itb.inst_misses 7428 # ITB inst misses +system.cpu0.dtb.hits 31729878 # DTB hits +system.cpu0.dtb.misses 48968 # DTB misses +system.cpu0.dtb.accesses 31778846 # DTB accesses +system.cpu0.itb.inst_hits 6261683 # ITB inst hits +system.cpu0.itb.inst_misses 7235 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 257 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 258 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 769 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_tlb_mva_asid 791 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID system.cpu0.itb.flush_entries 2632 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1569 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1762 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 6103473 # ITB inst accesses -system.cpu0.itb.hits 6096045 # DTB hits -system.cpu0.itb.misses 7428 # DTB misses -system.cpu0.itb.accesses 6103473 # DTB accesses -system.cpu0.numCycles 239139269 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 6268918 # ITB inst accesses +system.cpu0.itb.hits 6261683 # DTB hits +system.cpu0.itb.misses 7235 # DTB misses +system.cpu0.itb.accesses 6268918 # DTB accesses +system.cpu0.numCycles 237920120 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 15469651 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 47735703 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 7600384 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 4770839 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 10588915 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2554228 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 92050 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 48266741 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 1619 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 2012 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 51922 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 1409369 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 188 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 6094028 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 397204 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 3100 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 77649364 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.760813 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.117939 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 15748746 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 49352173 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 7472736 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 4735406 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 10833707 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2792544 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 84623 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 47712542 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 1287 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 1922 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 50902 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 1299242 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 340 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 6259599 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 422561 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2976 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 77655749 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.785029 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.152550 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 67068023 86.37% 86.37% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 685973 0.88% 87.26% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 883508 1.14% 88.39% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1225779 1.58% 89.97% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1145464 1.48% 91.45% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 573659 0.74% 92.19% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 1320882 1.70% 93.89% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 397746 0.51% 94.40% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4348330 5.60% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 66829888 86.06% 86.06% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 668416 0.86% 86.92% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 858180 1.11% 88.03% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1304413 1.68% 89.70% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1126910 1.45% 91.16% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 549966 0.71% 91.86% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 1380247 1.78% 93.64% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 376750 0.49% 94.13% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4560979 5.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 77649364 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.031782 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.199615 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 16523555 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 49304070 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 9588345 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 552618 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1678659 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 1021998 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 90748 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 56218321 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 303479 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1678659 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 17458336 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 19025484 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 27018348 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 9133613 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 3332888 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 53403158 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 13481 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 625557 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 2163090 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 470 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 55533202 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 243132036 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 243084049 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 47987 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 40330710 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 15202492 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 427890 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 379964 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 6776397 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 10330089 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6786263 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1056196 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1308824 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 49548242 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1040790 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 63116713 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 95333 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 10484602 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 26435485 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 265976 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 77649364 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.812843 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.518782 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 77655749 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.031409 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.207432 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 16823690 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 48684179 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 9802416 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 509733 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1833567 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 1006000 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 91487 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 57560969 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 307020 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1833567 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 17765952 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 19652864 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 25831801 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 9294758 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3274685 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 54590229 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 7255 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 552363 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 2204905 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 211 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 56896376 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 249980910 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 249932531 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 48379 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 39701074 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 17195302 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 410578 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 363043 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 6638624 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 10379903 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6907552 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1064074 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1362159 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 50052762 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 969661 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 62837234 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 92382 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 11367794 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 29332821 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 250599 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 77655749 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.809177 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.518047 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 54835526 70.62% 70.62% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 7206411 9.28% 79.90% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3684013 4.74% 84.64% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3126457 4.03% 88.67% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 6296301 8.11% 96.78% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1390393 1.79% 98.57% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 812577 1.05% 99.62% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 231214 0.30% 99.91% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 66472 0.09% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 55074638 70.92% 70.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 6993608 9.01% 79.93% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3678555 4.74% 84.66% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 3117743 4.01% 88.68% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 6240678 8.04% 96.72% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1479911 1.91% 98.62% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 787330 1.01% 99.64% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 219248 0.28% 99.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 64038 0.08% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 77649364 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 77655749 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 32527 0.73% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 4 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 4227565 94.61% 95.34% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 208097 4.66% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 30466 0.70% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 2 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 4143838 94.53% 95.23% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 209138 4.77% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 195790 0.31% 0.31% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 29888266 47.35% 47.66% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 47148 0.07% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 10 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 6 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 1209 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 26756071 42.39% 90.13% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6228206 9.87% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 167413 0.27% 0.27% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 29876413 47.55% 47.81% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 48260 0.08% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 15 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 2 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 7 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 946 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 26437550 42.07% 89.96% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 6306621 10.04% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 63116713 # Type of FU issued -system.cpu0.iq.rate 0.263933 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 4468193 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.070793 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 208483702 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 61082486 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 44086612 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 12401 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 6581 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 5541 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 67382548 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 6568 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 320496 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 62837234 # Type of FU issued +system.cpu0.iq.rate 0.264111 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 4383444 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.069759 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 207842642 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 62399132 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 43895220 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 12180 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 6627 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 5522 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 67046851 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 6414 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 320881 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2269255 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3561 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 15997 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 887357 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2431860 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3521 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 16133 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 922699 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 17163539 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 367436 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 16864632 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 486760 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1678659 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 14252559 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 235358 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 50705856 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 106082 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 10330089 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6786263 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 740769 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 57048 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 3493 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 15997 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 185463 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 146727 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 332190 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 61942896 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 26397875 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1173817 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1833567 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 14994749 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 240124 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 51146104 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 107104 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 10379903 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6907552 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 682007 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 55746 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 3189 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 16133 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 183360 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 147814 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 331174 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 61530066 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 26055329 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1307168 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 116824 # number of nop insts executed -system.cpu0.iew.exec_refs 32569629 # number of memory reference insts executed -system.cpu0.iew.exec_branches 6012851 # Number of branches executed -system.cpu0.iew.exec_stores 6171754 # Number of stores executed -system.cpu0.iew.exec_rate 0.259024 # Inst execution rate -system.cpu0.iew.wb_sent 61414090 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 44092153 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 24268667 # num instructions producing a value -system.cpu0.iew.wb_consumers 44593954 # num instructions consuming a value +system.cpu0.iew.exec_nop 123681 # number of nop insts executed +system.cpu0.iew.exec_refs 32305514 # number of memory reference insts executed +system.cpu0.iew.exec_branches 5821167 # Number of branches executed +system.cpu0.iew.exec_stores 6250185 # Number of stores executed +system.cpu0.iew.exec_rate 0.258616 # Inst execution rate +system.cpu0.iew.wb_sent 60920832 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 43900742 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 23943541 # num instructions producing a value +system.cpu0.iew.wb_consumers 43567103 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.184379 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.544214 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.184519 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.549578 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 10328850 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 774814 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 289634 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 75970705 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.524893 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.506232 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 11253313 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 719062 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 289317 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 75822182 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.520093 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.499421 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 61754720 81.29% 81.29% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 6906334 9.09% 90.38% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2042059 2.69% 93.07% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1137631 1.50% 94.56% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1039888 1.37% 95.93% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 547173 0.72% 96.65% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 697067 0.92% 97.57% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 371357 0.49% 98.06% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1474476 1.94% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 61770131 81.47% 81.47% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 6789372 8.95% 90.42% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2077521 2.74% 93.16% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1107875 1.46% 94.62% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1001712 1.32% 95.94% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 557795 0.74% 96.68% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 684831 0.90% 97.58% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 401810 0.53% 98.11% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1431135 1.89% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 75970705 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 31216883 # Number of instructions committed -system.cpu0.commit.committedOps 39876471 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 75822182 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 30629038 # Number of instructions committed +system.cpu0.commit.committedOps 39434598 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13959740 # Number of memory references committed -system.cpu0.commit.loads 8060834 # Number of loads committed -system.cpu0.commit.membars 211745 # Number of memory barriers committed -system.cpu0.commit.branches 5194005 # Number of branches committed -system.cpu0.commit.fp_insts 5497 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 35234084 # Number of committed integer instructions. -system.cpu0.commit.function_calls 512673 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1474476 # number cycles where commit BW limit reached +system.cpu0.commit.refs 13932896 # Number of memory references committed +system.cpu0.commit.loads 7948043 # Number of loads committed +system.cpu0.commit.membars 201908 # Number of memory barriers committed +system.cpu0.commit.branches 4992421 # Number of branches committed +system.cpu0.commit.fp_insts 5469 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 34986832 # Number of committed integer instructions. +system.cpu0.commit.function_calls 490811 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1431135 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 123727475 # The number of ROB reads -system.cpu0.rob.rob_writes 102131366 # The number of ROB writes -system.cpu0.timesIdled 883402 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 161489905 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2289692501 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 31137553 # Number of Instructions Simulated -system.cpu0.committedOps 39797141 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 31137553 # Number of Instructions Simulated -system.cpu0.cpi 7.680092 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 7.680092 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.130207 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.130207 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 280388173 # number of integer regfile reads -system.cpu0.int_regfile_writes 45343219 # number of integer regfile writes -system.cpu0.fp_regfile_reads 22835 # number of floating regfile reads -system.cpu0.fp_regfile_writes 19826 # number of floating regfile writes -system.cpu0.misc_regfile_reads 15490012 # number of misc regfile reads -system.cpu0.misc_regfile_writes 428542 # number of misc regfile writes -system.cpu0.icache.replacements 983837 # number of replacements -system.cpu0.icache.tagsinuse 511.608434 # Cycle average of tags in use -system.cpu0.icache.total_refs 11044105 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 984349 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 11.219705 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 6537508000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 356.557711 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 155.050723 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.696402 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu1.inst 0.302833 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.999235 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 5554519 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 5489586 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 11044105 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5554519 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 5489586 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 11044105 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5554519 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 5489586 # number of overall hits -system.cpu0.icache.overall_hits::total 11044105 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 539384 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 525964 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1065348 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 539384 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 525964 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1065348 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 539384 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 525964 # number of overall misses -system.cpu0.icache.overall_misses::total 1065348 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7306834994 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6986624997 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 14293459991 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 7306834994 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 6986624997 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 14293459991 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 7306834994 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 6986624997 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 14293459991 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 6093903 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 6015550 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 12109453 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 6093903 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 6015550 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 12109453 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 6093903 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 6015550 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 12109453 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.088512 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.087434 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.087977 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.088512 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.087434 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.087977 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.088512 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.087434 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.087977 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13546.629107 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13283.466163 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13416.705143 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13546.629107 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13283.466163 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13416.705143 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13546.629107 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13283.466163 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13416.705143 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 5066 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 940 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 333 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.213213 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 940 # average number of cycles each access was blocked +system.cpu0.rob.rob_reads 124149615 # The number of ROB reads +system.cpu0.rob.rob_writes 103265708 # The number of ROB writes +system.cpu0.timesIdled 892080 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 160264371 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2282472691 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 30545540 # Number of Instructions Simulated +system.cpu0.committedOps 39351100 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 30545540 # Number of Instructions Simulated +system.cpu0.cpi 7.789030 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 7.789030 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.128386 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.128386 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 279175646 # number of integer regfile reads +system.cpu0.int_regfile_writes 45166448 # number of integer regfile writes +system.cpu0.fp_regfile_reads 23007 # number of floating regfile reads +system.cpu0.fp_regfile_writes 19790 # number of floating regfile writes +system.cpu0.misc_regfile_reads 15439802 # number of misc regfile reads +system.cpu0.misc_regfile_writes 404480 # number of misc regfile writes +system.cpu0.icache.replacements 984632 # number of replacements +system.cpu0.icache.tagsinuse 511.564307 # Cycle average of tags in use +system.cpu0.icache.total_refs 10914069 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 985144 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 11.078653 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 6937099000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 153.323923 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu1.inst 358.240384 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.299461 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu1.inst 0.699688 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.999149 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 5710872 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 5203197 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 10914069 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 5710872 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 5203197 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 10914069 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 5710872 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 5203197 # number of overall hits +system.cpu0.icache.overall_hits::total 10914069 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 548607 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 517852 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1066459 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 548607 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 517852 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1066459 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 548607 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 517852 # number of overall misses +system.cpu0.icache.overall_misses::total 1066459 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7528963984 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 7029593986 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 14558557970 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 7528963984 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 7029593986 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 14558557970 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 7528963984 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 7029593986 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 14558557970 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 6259479 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 5721049 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 11980528 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 6259479 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 5721049 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 11980528 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 6259479 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 5721049 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 11980528 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.087644 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.090517 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.089016 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.087644 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.090517 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.089016 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.087644 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.090517 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.089016 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13723.784028 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13574.523196 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13651.305835 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13723.784028 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13574.523196 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13651.305835 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13723.784028 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13574.523196 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13651.305835 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 7371 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 409 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 18.022005 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 41253 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 39724 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 80977 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 41253 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu1.inst 39724 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 80977 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 41253 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu1.inst 39724 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 80977 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 498131 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 486240 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 984371 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 498131 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 486240 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 984371 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 498131 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 486240 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 984371 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5959731494 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5688421497 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 11648152991 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5959731494 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5688421497 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 11648152991 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5959731494 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5688421497 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 11648152991 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7527500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7527500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7527500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 7527500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.081743 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.080831 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.081289 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.081743 # 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Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 48810000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 193.724997 # Average occupied blocks per requestor +system.cpu0.dcache.occ_blocks::cpu1.data 318.267071 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.378369 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::cpu1.data 0.621615 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.999985 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 7114161 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 6663960 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 13778121 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3647393 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 3614436 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 7261829 # 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number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 132212 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 125382 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 257594 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 127473 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 120155 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 247628 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12704051 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 12051070 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 24755121 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12704051 # 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number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 118000 # number of LoadLockedReq MSHR uncacheable cycles -system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 118000 # number of LoadLockedReq MSHR uncacheable cycles -system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 69000 # number of StoreCondReq MSHR uncacheable cycles -system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 69000 # number of StoreCondReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 106860174570 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 109111895021 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 215972069591 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028239 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024754 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026561 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023281 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025434 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024345 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046516 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.048356 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047412 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000039 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000050 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000044 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026222 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025039 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.025646 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026222 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025039 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.025646 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13610.576652 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13541.952208 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13579.782066 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33576.301968 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34401.903281 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34002.691752 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11743.414634 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12210.951674 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11975.517891 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 67000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 134000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8272921091 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7745751501 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 16018672592 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8272921091 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7745751501 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 16018672592 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 90317850501 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 92017839000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182335689501 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 18608772616 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 14303930851 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 32912703467 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 156000 # number of LoadLockedReq MSHR uncacheable cycles +system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 156000 # number of LoadLockedReq MSHR uncacheable cycles +system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 96000 # number of StoreCondReq MSHR uncacheable cycles +system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 96000 # number of StoreCondReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 108926623117 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 106321769851 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 215248392968 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024709 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.028567 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026587 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.024933 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023757 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024356 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.051475 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.043710 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047379 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000043 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000038 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000040 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.024801 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.026572 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.025666 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.024801 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.026572 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.025666 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13896.184228 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13279.234055 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13573.459198 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 43991.095531 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42494.536818 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43275.068377 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12463.001758 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11481.453718 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11985.354775 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 13400 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 12090.909091 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20823.372030 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 22427.821552 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21585.947400 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20823.372030 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22427.821552 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21585.947400 # average overall mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 13400 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 13400 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26341.010256 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24116.618773 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25216.368057 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26341.010256 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24116.618773 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25216.368057 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1322,324 +1745,324 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 7054454 # Number of BP lookups -system.cpu1.branchPred.condPredicted 5657096 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 345347 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 4549622 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 3820237 # Number of BTB hits +system.cpu1.branchPred.lookups 7176614 # Number of BP lookups +system.cpu1.branchPred.condPredicted 5748558 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 346164 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 4712171 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 3815419 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 83.968229 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 674890 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 35092 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 80.969451 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 703194 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 35756 # Number of incorrect RAS predictions. system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 25326740 # DTB read hits -system.cpu1.dtb.read_misses 36422 # DTB read misses -system.cpu1.dtb.write_hits 5812086 # DTB write hits -system.cpu1.dtb.write_misses 9253 # DTB write misses -system.cpu1.dtb.flush_tlb 254 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 25652921 # DTB read hits +system.cpu1.dtb.read_misses 36442 # DTB read misses +system.cpu1.dtb.write_hits 5708219 # DTB write hits +system.cpu1.dtb.write_misses 9483 # DTB write misses +system.cpu1.dtb.flush_tlb 255 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 670 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 5525 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 1356 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 233 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 648 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 5550 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 1291 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 249 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 644 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 25363162 # DTB read accesses -system.cpu1.dtb.write_accesses 5821339 # DTB write accesses +system.cpu1.dtb.perms_faults 574 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 25689363 # DTB read accesses +system.cpu1.dtb.write_accesses 5717702 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 31138826 # DTB hits -system.cpu1.dtb.misses 45675 # DTB misses -system.cpu1.dtb.accesses 31184501 # DTB accesses -system.cpu1.itb.inst_hits 6017589 # ITB inst hits -system.cpu1.itb.inst_misses 6780 # ITB inst misses +system.cpu1.dtb.hits 31361140 # DTB hits +system.cpu1.dtb.misses 45925 # DTB misses +system.cpu1.dtb.accesses 31407065 # DTB accesses +system.cpu1.itb.inst_hits 5722854 # ITB inst hits +system.cpu1.itb.inst_misses 6790 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 254 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 255 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 670 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_tlb_mva_asid 648 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID system.cpu1.itb.flush_entries 2604 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1493 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1206 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 6024369 # ITB inst accesses -system.cpu1.itb.hits 6017589 # DTB hits -system.cpu1.itb.misses 6780 # DTB misses -system.cpu1.itb.accesses 6024369 # DTB accesses -system.cpu1.numCycles 234207757 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 5729644 # ITB inst accesses +system.cpu1.itb.hits 5722854 # DTB hits +system.cpu1.itb.misses 6790 # DTB misses +system.cpu1.itb.accesses 5729644 # DTB accesses +system.cpu1.numCycles 238719781 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 15218240 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 46698589 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 7054454 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 4495127 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 10302624 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 2620130 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 82175 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 46347162 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 1067 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 2022 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 43841 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 1251673 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 166 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 6015552 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 445431 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2871 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 75042047 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.773320 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.138232 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 14663434 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 45610232 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 7176614 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 4518613 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 10115214 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 2414166 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 79241 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 48437095 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 1565 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 1874 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 41135 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 1402245 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 183 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 5721051 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 343472 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3001 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 76398004 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.741963 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.097795 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 64747187 86.28% 86.28% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 625900 0.83% 87.12% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 833929 1.11% 88.23% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1208466 1.61% 89.84% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1046555 1.39% 91.23% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 538335 0.72% 91.95% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1373859 1.83% 93.78% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 351234 0.47% 94.25% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 4316582 5.75% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 66290194 86.77% 86.77% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 639384 0.84% 87.61% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 858446 1.12% 88.73% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1141205 1.49% 90.22% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1054322 1.38% 91.60% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 565766 0.74% 92.34% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1279029 1.67% 94.02% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 372986 0.49% 94.51% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 4196672 5.49% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 75042047 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.030120 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.199390 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 16229024 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 47299345 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 9347740 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 453958 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1709750 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 948283 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 85990 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 54953007 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 286020 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1709750 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 17168291 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 18529773 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 25747808 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 8785346 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 3098929 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 51771461 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 7122 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 486511 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 2115721 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 96 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 53850166 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 237651325 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 237608915 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 42410 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 38062786 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 15787379 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 405266 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 358955 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 6248671 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 9866186 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 6689314 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 887473 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1140418 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 47717114 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 944883 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 60871845 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 81909 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 10575332 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 28005773 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 237169 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 75042047 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.811170 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.521401 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 76398004 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.030063 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.191062 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 15662136 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 49485106 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 9174118 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 502006 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1572389 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 964164 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 86078 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 53732667 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 284993 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1572389 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 16517156 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 19371694 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 27019391 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 8745759 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 3169437 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 51316953 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 13347 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 558580 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 2084092 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 533 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 53384018 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 234291448 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 234248948 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 42500 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 38701877 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 14682140 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 422621 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 375998 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 6399704 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 9755366 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 6540913 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 899316 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1131463 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 47221133 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1016692 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 61223636 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 83704 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 9695690 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 24360360 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 252773 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 76398004 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.801377 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.509980 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 53284770 71.01% 71.01% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 6662382 8.88% 79.88% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 3536622 4.71% 84.60% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 2873956 3.83% 88.43% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 6247532 8.33% 96.75% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1425164 1.90% 98.65% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 742478 0.99% 99.64% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 209609 0.28% 99.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 59534 0.08% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 54279894 71.05% 71.05% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 6964982 9.12% 80.17% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 3572105 4.68% 84.84% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 2997144 3.92% 88.76% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 6191464 8.10% 96.87% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1336331 1.75% 98.62% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 781274 1.02% 99.64% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 210623 0.28% 99.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 64187 0.08% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 75042047 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 76398004 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 26737 0.61% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 1 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4146600 94.82% 95.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 199958 4.57% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 28625 0.64% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 3 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 4232850 94.77% 95.41% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 204916 4.59% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 167876 0.28% 0.28% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 28487291 46.80% 47.07% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 46424 0.08% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 8 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 6 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 902 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 26063934 42.82% 89.97% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 6105398 10.03% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 196253 0.32% 0.32% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 28636645 46.77% 47.09% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 45275 0.07% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 13 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 13 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1166 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 13 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 26314487 42.98% 90.15% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 6029771 9.85% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 60871845 # Type of FU issued -system.cpu1.iq.rate 0.259905 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 4373296 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.071844 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 201275709 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 59245662 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 41829457 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 10720 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 5895 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 4750 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 65071600 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 5665 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 304013 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 61223636 # Type of FU issued +system.cpu1.iq.rate 0.256467 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 4466394 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.072952 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 203430011 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 57942058 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 42278659 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 11099 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 5883 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 4799 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 65487820 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 5957 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 306320 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2271620 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 3204 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 14692 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 855526 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2045827 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 3210 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 14938 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 792022 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 16940305 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 458975 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 17238980 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 391927 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1709750 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 13959970 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 234377 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 48767354 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 97921 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 9866186 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 6689314 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 671038 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 52079 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3815 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 14692 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 167743 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 133124 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 300867 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 59498020 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 25657253 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1373825 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 1572389 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 14646185 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 228906 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 48337037 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 102627 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 9755366 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 6540913 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 729665 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 50173 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3845 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 14938 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 169845 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 132330 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 302175 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 60177661 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 26008514 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1045975 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 105357 # number of nop insts executed -system.cpu1.iew.exec_refs 31711723 # number of memory reference insts executed -system.cpu1.iew.exec_branches 5535621 # Number of branches executed -system.cpu1.iew.exec_stores 6054470 # Number of stores executed -system.cpu1.iew.exec_rate 0.254039 # Inst execution rate -system.cpu1.iew.wb_sent 58916799 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 41834207 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 22806182 # num instructions producing a value -system.cpu1.iew.wb_consumers 41818913 # num instructions consuming a value +system.cpu1.iew.exec_nop 99212 # number of nop insts executed +system.cpu1.iew.exec_refs 31985233 # number of memory reference insts executed +system.cpu1.iew.exec_branches 5705434 # Number of branches executed +system.cpu1.iew.exec_stores 5976719 # Number of stores executed +system.cpu1.iew.exec_rate 0.252085 # Inst execution rate +system.cpu1.iew.wb_sent 59667880 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 42283458 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 23216135 # num instructions producing a value +system.cpu1.iew.wb_consumers 42895102 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.178620 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.545356 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.177126 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.541230 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 10492813 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 707714 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 260708 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 73332297 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.516509 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.496867 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 9567940 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 763919 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 261423 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 74825615 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.512228 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.487191 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 59797837 81.54% 81.54% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 6663272 9.09% 90.63% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1912982 2.61% 93.24% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1016048 1.39% 94.62% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 959954 1.31% 95.93% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 526368 0.72% 96.65% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 702800 0.96% 97.61% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 373366 0.51% 98.12% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1379670 1.88% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 61056295 81.60% 81.60% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 6800068 9.09% 90.69% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1929591 2.58% 93.26% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1057405 1.41% 94.68% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1013455 1.35% 96.03% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 520209 0.70% 96.73% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 685711 0.92% 97.64% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 375889 0.50% 98.15% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1386992 1.85% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 73332297 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 29243924 # Number of instructions committed -system.cpu1.commit.committedOps 37876758 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 74825615 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 29838157 # Number of instructions committed +system.cpu1.commit.committedOps 38327755 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 13428354 # Number of memory references committed -system.cpu1.commit.loads 7594566 # Number of loads committed -system.cpu1.commit.membars 191899 # Number of memory barriers committed -system.cpu1.commit.branches 4767702 # Number of branches committed -system.cpu1.commit.fp_insts 4715 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 33624060 # Number of committed integer instructions. -system.cpu1.commit.function_calls 478655 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1379670 # number cycles where commit BW limit reached +system.cpu1.commit.refs 13458430 # Number of memory references committed +system.cpu1.commit.loads 7709539 # Number of loads committed +system.cpu1.commit.membars 201879 # Number of memory barriers committed +system.cpu1.commit.branches 4970440 # Number of branches committed +system.cpu1.commit.fp_insts 4743 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 33879408 # Number of committed integer instructions. +system.cpu1.commit.function_calls 500692 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1386992 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 119446868 # The number of ROB reads -system.cpu1.rob.rob_writes 98500710 # The number of ROB writes -system.cpu1.timesIdled 873517 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 159165710 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 2285782593 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 29172873 # Number of Instructions Simulated -system.cpu1.committedOps 37805707 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 29172873 # Number of Instructions Simulated -system.cpu1.cpi 8.028272 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 8.028272 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.124560 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.124560 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 269572472 # number of integer regfile reads -system.cpu1.int_regfile_writes 42951903 # number of integer regfile writes -system.cpu1.fp_regfile_reads 22113 # number of floating regfile reads -system.cpu1.fp_regfile_writes 19714 # number of floating regfile writes -system.cpu1.misc_regfile_reads 14815337 # number of misc regfile reads -system.cpu1.misc_regfile_writes 403940 # number of misc regfile writes +system.cpu1.rob.rob_reads 120414089 # The number of ROB reads +system.cpu1.rob.rob_writes 97409741 # The number of ROB writes +system.cpu1.timesIdled 885352 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 162321777 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 2286481516 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 29771274 # Number of Instructions Simulated +system.cpu1.committedOps 38260872 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 29771274 # Number of Instructions Simulated +system.cpu1.cpi 8.018460 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 8.018460 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.124712 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.124712 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 271859015 # number of integer regfile reads +system.cpu1.int_regfile_writes 43450852 # number of integer regfile writes +system.cpu1.fp_regfile_reads 22226 # number of floating regfile reads +system.cpu1.fp_regfile_writes 19958 # number of floating regfile writes +system.cpu1.misc_regfile_reads 14811721 # number of misc regfile reads +system.cpu1.misc_regfile_writes 428358 # number of misc regfile writes system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. @@ -1654,17 +2077,17 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1192618547941 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1192618547941 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1192618547941 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1192618547941 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1456504103755 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1456504103755 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1456504103755 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1456504103755 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 83057 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 83064 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt index a80cc588c..fb76d8786 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt @@ -1,154 +1,142 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.610012 # Number of seconds simulated -sim_ticks 2610011895000 # Number of ticks simulated -final_tick 2610011895000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.627154 # Number of seconds simulated +sim_ticks 2627154206500 # Number of ticks simulated +final_tick 2627154206500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 531747 # Simulator instruction rate (inst/s) -host_op_rate 676644 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 23052454652 # Simulator tick rate (ticks/s) -host_mem_usage 397728 # Number of bytes of host memory used -host_seconds 113.22 # Real time elapsed on the host -sim_insts 60204721 # Number of instructions simulated -sim_ops 76610045 # Number of ops (including micro ops) simulated -system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory +host_inst_rate 361221 # Simulator instruction rate (inst/s) +host_op_rate 459651 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15759970234 # Simulator tick rate (ticks/s) +host_mem_usage 398468 # Number of bytes of host memory used +host_seconds 166.70 # Real time elapsed on the host +sim_insts 60214798 # Number of instructions simulated +sim_ops 76622863 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 356960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4558796 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 347904 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4486256 # Number of bytes read from this memory -system.physmem.bytes_read::total 132433500 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 356960 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 347904 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 704864 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3672640 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1510336 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1505932 # Number of bytes written to this memory -system.physmem.bytes_written::total 6688908 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu0.inst 292384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4914704 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 411968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4151472 # Number of bytes read from this memory +system.physmem.bytes_read::total 134026976 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 292384 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 411968 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 704352 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3695296 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1534856 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1481296 # Number of bytes written to this memory +system.physmem.bytes_written::total 6711448 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 15532032 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 11780 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 71264 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 5436 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 70124 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15494031 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57385 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 377584 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 376483 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811452 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47004917 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 25 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu0.inst 10771 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 76826 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6437 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 64893 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15690962 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57739 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 383714 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 370324 # Number of write requests responded to by this memory +system.physmem.num_writes::total 811777 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47296902 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 136766 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1746657 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 133296 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1718864 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50740573 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 136766 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 133296 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 270062 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1407135 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 578670 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 576983 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2562788 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1407135 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47004917 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 25 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 111293 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1870733 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 24 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 156812 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1580216 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51016029 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 111293 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 156812 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 268105 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1406578 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 584228 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 563841 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2554646 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1406578 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47296902 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 136766 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2325327 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 133296 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2295847 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53303362 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15494031 # Total number of read requests seen -system.physmem.writeReqs 811452 # Total number of write requests seen -system.physmem.cpureqs 213827 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 991617984 # Total number of bytes read from memory -system.physmem.bytesWritten 51932928 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 132433500 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6688908 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 27 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4514 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 974843 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 967897 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 967762 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 968563 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 968385 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 967634 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 967724 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 968241 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 968097 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 967669 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 967710 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 968022 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 968146 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 967643 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 967509 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 968159 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50752 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 50352 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50308 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 50998 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50782 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50138 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50199 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50736 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51142 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 50687 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50724 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51047 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51142 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 50663 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 50585 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51197 # Track writes on a per bank basis +system.physmem.bw_total::cpu0.inst 111293 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2454961 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 24 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 156812 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2144057 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53570675 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15690962 # Total number of read requests seen +system.physmem.writeReqs 811777 # Total number of write requests seen +system.physmem.cpureqs 214505 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1004221568 # Total number of bytes read from memory +system.physmem.bytesWritten 51953728 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 134026976 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6711448 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 26 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4516 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 980549 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 980310 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 980142 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 980447 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 986846 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 980559 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 980589 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 980289 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 980613 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 980424 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 979732 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 979654 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 980193 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 980214 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 980246 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 980129 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 49310 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 49129 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50872 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51113 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 51073 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 51327 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 51427 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51168 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51208 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51034 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50441 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 50412 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 50841 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 50704 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 50889 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 50829 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 2610007487000 # Total gap between requests +system.physmem.totGap 2627149788000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 6679 # Categorize read packet sizes -system.physmem.readPktSize::3 15335424 # Categorize read packet sizes +system.physmem.readPktSize::2 6680 # Categorize read packet sizes +system.physmem.readPktSize::3 15532032 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 151928 # Categorize read packet sizes +system.physmem.readPktSize::6 152250 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 754067 # Categorize write packet sizes +system.physmem.writePktSize::2 754038 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 57385 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1116599 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 960481 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 974945 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3652366 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2754414 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2758656 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2734326 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 61705 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 60367 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 111551 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 162629 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 111438 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 8743 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 8647 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 8559 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 8528 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 50 # What read queue length does an incoming req see +system.physmem.writePktSize::6 57739 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1134037 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 977508 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1022657 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3835405 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2876027 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2874808 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2829459 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 16845 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 15768 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 28680 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 41555 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 28532 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 2442 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 2410 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 2396 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 2375 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 32 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -164,258 +152,521 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 35439 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 35424 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 35400 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 35389 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 35372 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 35363 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 35346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 35341 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 35325 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35306 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35268 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35253 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 35474 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 35454 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 35436 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 35415 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 35397 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 35384 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 35365 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 35351 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 35334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35318 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35306 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35273 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 338127200750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 432998808250 # Sum of mem lat for all requests -system.physmem.totBusLat 77470020000 # Total cycles spent in databus access -system.physmem.totBankLat 17401587500 # Total cycles spent in bank access -system.physmem.avgQLat 21823.10 # Average queueing delay per request -system.physmem.avgBankLat 1123.12 # Average bank access latency per request +system.physmem.bytesPerActivate::samples 38107 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 27715.971974 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 2557.155392 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 33302.761922 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-127 5424 14.23% 14.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-191 3316 8.70% 22.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-255 2198 5.77% 28.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-319 1686 4.42% 33.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-383 1157 3.04% 36.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-447 1029 2.70% 38.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-511 812 2.13% 41.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-575 726 1.91% 42.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-639 578 1.52% 44.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-703 463 1.21% 45.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-767 465 1.22% 46.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-831 413 1.08% 47.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-895 261 0.68% 48.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-959 269 0.71% 49.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-1023 229 0.60% 49.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1087 239 0.63% 50.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1151 133 0.35% 50.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1215 136 0.36% 51.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1279 99 0.26% 51.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1343 99 0.26% 51.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1407 86 0.23% 52.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1471 150 0.39% 52.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1535 761 2.00% 54.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1599 211 0.55% 54.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1663 139 0.36% 55.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1727 123 0.32% 55.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1791 64 0.17% 55.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1855 78 0.20% 56.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1919 56 0.15% 56.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1983 58 0.15% 56.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-2047 48 0.13% 56.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2111 69 0.18% 56.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2175 34 0.09% 56.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2239 27 0.07% 56.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2303 25 0.07% 56.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2367 25 0.07% 56.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2431 9 0.02% 56.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2495 23 0.06% 56.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2559 23 0.06% 57.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2623 14 0.04% 57.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2687 10 0.03% 57.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2751 11 0.03% 57.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2815 14 0.04% 57.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2879 8 0.02% 57.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2943 10 0.03% 57.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-3007 9 0.02% 57.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3071 8 0.02% 57.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3135 19 0.05% 57.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3199 5 0.01% 57.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3263 6 0.02% 57.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3327 10 0.03% 57.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3391 10 0.03% 57.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3455 4 0.01% 57.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3519 8 0.02% 57.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3583 4 0.01% 57.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3647 7 0.02% 57.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3711 11 0.03% 57.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3775 11 0.03% 57.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3839 9 0.02% 57.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3903 3 0.01% 57.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3967 6 0.02% 57.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-4031 10 0.03% 57.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4095 5 0.01% 57.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4159 35 0.09% 57.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4223 2 0.01% 57.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4287 2 0.01% 57.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4351 6 0.02% 57.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4415 4 0.01% 57.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4479 6 0.02% 57.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4543 4 0.01% 57.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4607 3 0.01% 57.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4671 6 0.02% 57.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4735 2 0.01% 57.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4799 1 0.00% 57.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4863 5 0.01% 57.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4927 3 0.01% 57.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4991 1 0.00% 57.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-5055 2 0.01% 57.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5119 3 0.01% 57.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5183 7 0.02% 57.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5311 5 0.01% 57.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5375 2 0.01% 57.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5439 4 0.01% 57.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5503 2 0.01% 57.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5567 4 0.01% 57.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5631 2 0.01% 57.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5695 3 0.01% 57.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5759 2 0.01% 57.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5887 1 0.00% 57.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5951 2 0.01% 57.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6079 1 0.00% 57.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6143 1 0.00% 57.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6207 23 0.06% 57.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6271 4 0.01% 58.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6335 3 0.01% 58.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6527 2 0.01% 58.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6591 2 0.01% 58.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6719 2 0.01% 58.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6783 1 0.00% 58.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6847 18 0.05% 58.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6975 1 0.00% 58.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-7039 1 0.00% 58.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7103 3 0.01% 58.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7231 5 0.01% 58.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7295 1 0.00% 58.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7423 3 0.01% 58.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7487 4 0.01% 58.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7551 2 0.01% 58.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7615 5 0.01% 58.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7679 4 0.01% 58.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7743 6 0.02% 58.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7807 6 0.02% 58.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7871 4 0.01% 58.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7935 6 0.02% 58.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7999 2 0.01% 58.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8063 3 0.01% 58.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8127 6 0.02% 58.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8191 5 0.01% 58.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8255 310 0.81% 59.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9279 1 0.00% 59.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9408-9471 1 0.00% 59.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9791 1 0.00% 59.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9792-9855 1 0.00% 59.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-10047 1 0.00% 59.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10303 17 0.04% 59.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10559 1 0.00% 59.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11327 2 0.01% 59.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12095 2 0.01% 59.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12351 1 0.00% 59.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13119 1 0.00% 59.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13375 2 0.01% 59.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14143 1 0.00% 59.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14655 1 0.00% 59.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14911 1 0.00% 59.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17471 2 0.01% 59.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18688-18751 2 0.01% 59.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19712-19775 1 0.00% 59.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19968-20031 1 0.00% 59.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20736-20799 1 0.00% 59.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21567 3 0.01% 59.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22016-22079 1 0.00% 59.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22784-22847 1 0.00% 59.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23615 1 0.00% 59.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24639 3 0.01% 59.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24832-24895 1 0.00% 59.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25663 1 0.00% 59.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25920-25983 1 0.00% 59.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26687 1 0.00% 59.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27455 2 0.01% 59.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28479 1 0.00% 59.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28735 3 0.01% 59.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28991 1 0.00% 59.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-30015 1 0.00% 59.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30271 1 0.00% 59.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30527 1 0.00% 59.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31040-31103 2 0.01% 59.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32063 1 0.00% 59.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32575 1 0.00% 59.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33087 1 0.00% 59.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33472-33535 2 0.01% 59.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33599 19 0.05% 59.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35328-35391 1 0.00% 59.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36927 2 0.01% 59.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38207 1 0.00% 59.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-41023 1 0.00% 59.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-42047 1 0.00% 59.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43071 1 0.00% 59.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44095 2 0.01% 59.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48191 1 0.00% 59.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48447 1 0.00% 59.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49215 1 0.00% 59.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50688-50751 1 0.00% 59.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51456-51519 1 0.00% 59.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::52480-52543 1 0.00% 59.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::54272-54335 1 0.00% 59.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::56128-56191 1 0.00% 59.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::58624-58687 1 0.00% 59.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::60032-60095 1 0.00% 59.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::60672-60735 1 0.00% 59.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::63488-63551 1 0.00% 59.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65536-65599 15122 39.68% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::71808-71871 1 0.00% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::82176-82239 1 0.00% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::88064-88127 1 0.00% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::99712-99775 1 0.00% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::129856-129919 1 0.00% 99.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::130176-130239 1 0.00% 99.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::131072-131135 356 0.93% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::131200-131263 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::132096-132159 3 0.01% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::136576-136639 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::420352-420415 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 38107 # Bytes accessed per row activation +system.physmem.totQLat 304254816750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 398977768000 # Sum of mem lat for all requests +system.physmem.totBusLat 78454680000 # Total cycles spent in databus access +system.physmem.totBankLat 16268271250 # Total cycles spent in bank access +system.physmem.avgQLat 19390.48 # Average queueing delay per request +system.physmem.avgBankLat 1036.79 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 27946.22 # Average memory access latency -system.physmem.avgRdBW 379.93 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 19.90 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 50.74 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 2.56 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 25427.28 # Average memory access latency +system.physmem.avgRdBW 382.25 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 19.78 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 51.02 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 2.55 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.12 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.17 # Average read queue length over time -system.physmem.avgWrQLen 1.25 # Average write queue length over time -system.physmem.readRowHits 15419474 # Number of row buffer hits during reads -system.physmem.writeRowHits 794097 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 97.86 # Row buffer hit rate for writes -system.physmem.avgGap 160069.31 # Average gap between requests -system.l2c.replacements 61815 # number of replacements -system.l2c.tagsinuse 50922.556971 # Cycle average of tags in use -system.l2c.total_refs 1697645 # Total number of references to valid blocks. -system.l2c.sampled_refs 127200 # Sample count of references to valid blocks. -system.l2c.avg_refs 13.346266 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2558113998500 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 37911.407860 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 0.000184 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.000643 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 3494.638706 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 3026.772488 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 3500.625095 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 2989.111995 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.578482 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy +system.physmem.busUtil 3.14 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.15 # Average read queue length over time +system.physmem.avgWrQLen 1.26 # Average write queue length over time +system.physmem.readRowHits 15666209 # Number of row buffer hits during reads +system.physmem.writeRowHits 798397 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.84 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 98.35 # Row buffer hit rate for writes +system.physmem.avgGap 159194.77 # Average gap between requests +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 54483503 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16743616 # Transaction distribution +system.membus.trans_dist::ReadResp 16743616 # Transaction distribution +system.membus.trans_dist::WriteReq 763392 # Transaction distribution +system.membus.trans_dist::WriteResp 763392 # Transaction distribution +system.membus.trans_dist::Writeback 57739 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4516 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4516 # Transaction distribution +system.membus.trans_dist::ReadExReq 131423 # Transaction distribution +system.membus.trans_dist::ReadExResp 131423 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382990 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1892707 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3860 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4279569 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 31064064 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 31064064 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.bridge.slave 2382990 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 32956771 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.realview.gic.pio 3860 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 35343633 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390397 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16482168 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7720 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 18880309 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 124256256 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 124256256 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.bridge.slave 2390397 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 140738424 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.realview.gic.pio 7720 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 143136565 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 143136565 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 1225633000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 18165198500 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.7 # Layer utilization (%) +system.membus.reqLayer3.occupancy 3755000 # Layer occupancy (ticks) +system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer5.occupancy 1000 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 4987617364 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.respLayer2.occupancy 35065696500 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 1.3 # 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average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58186.810626 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 51880.433734 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 52339.077136 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -556,10 +803,6 @@ system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency::cpu1.data inf # average LoadLockedReq mshr uncacheable latency -system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency::total inf # average LoadLockedReq mshr uncacheable latency -system.l2c.StoreCondReq_avg_mshr_uncacheable_latency::cpu1.data inf # average StoreCondReq mshr uncacheable latency -system.l2c.StoreCondReq_avg_mshr_uncacheable_latency::total inf # average StoreCondReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency @@ -571,137 +814,329 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. +system.toL2Bus.throughput 52848676 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2471696 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2471696 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 763392 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 763392 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 596576 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2907 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2907 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 247542 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 247542 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 1725238 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 5754024 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma 19969 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma 50318 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count 7549549 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 54758516 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 83805889 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma 28400 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma 79212 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size 138672017 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 138672017 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 169604 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4809056500 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 3862257000 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 4394586000 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 12869000 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 30515000 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.throughput 48206783 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16715360 # Transaction distribution +system.iobus.trans_dist::ReadResp 16715360 # Transaction distribution +system.iobus.trans_dist::WriteReq 8167 # Transaction distribution +system.iobus.trans_dist::WriteResp 8167 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7946 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 536 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382990 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 31064064 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 31064064 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.realview_io.pio 7946 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.timer0.pio 536 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.iocache.cpu_side 31064064 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 33447054 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15892 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1072 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390397 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 124256256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::total 124256256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.realview_io.pio 15892 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.timer0.pio 1072 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.iocache.cpu_side 124256256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 126646653 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 126646653 # Total data (bytes) +system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 3978000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 536000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 527000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) +system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) +system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks) +system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) +system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 15532032000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) +system.iobus.respLayer0.occupancy 2374823000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) +system.iobus.respLayer1.occupancy 31064064000 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 1.2 # Layer utilization (%) system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7403435 # DTB read hits -system.cpu0.dtb.read_misses 6873 # DTB read misses -system.cpu0.dtb.write_hits 5501198 # DTB write hits -system.cpu0.dtb.write_misses 1842 # DTB write misses -system.cpu0.dtb.flush_tlb 1277 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 7331530 # DTB read hits +system.cpu0.dtb.read_misses 6749 # DTB read misses +system.cpu0.dtb.write_hits 5629181 # DTB write hits +system.cpu0.dtb.write_misses 1838 # DTB write misses +system.cpu0.dtb.flush_tlb 1246 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 727 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_tlb_mva_asid 712 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID system.cpu0.dtb.flush_entries 6355 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 141 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 135 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 225 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7410308 # DTB read accesses -system.cpu0.dtb.write_accesses 5503040 # DTB write accesses +system.cpu0.dtb.perms_faults 224 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 7338279 # DTB read accesses +system.cpu0.dtb.write_accesses 5631019 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 12904633 # DTB hits -system.cpu0.dtb.misses 8715 # DTB misses -system.cpu0.dtb.accesses 12913348 # DTB accesses -system.cpu0.itb.inst_hits 30303054 # ITB inst hits -system.cpu0.itb.inst_misses 3598 # ITB inst misses +system.cpu0.dtb.hits 12960711 # DTB hits +system.cpu0.dtb.misses 8587 # DTB misses +system.cpu0.dtb.accesses 12969298 # DTB accesses +system.cpu0.itb.inst_hits 29905877 # ITB inst hits +system.cpu0.itb.inst_misses 3541 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 1277 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 1246 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 727 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2696 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 712 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 2713 # 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number of times the floating registers were written -system.cpu0.num_mem_refs 13487423 # number of memory refs -system.cpu0.num_load_insts 7732203 # Number of load instructions -system.cpu0.num_store_insts 5755220 # Number of store instructions -system.cpu0.num_idle_cycles -6063478143.749568 # Number of idle cycles -system.cpu0.num_busy_cycles 8731821098.749567 # Number of busy cycles -system.cpu0.not_idle_fraction 3.272376 # Percentage of non-idle cycles -system.cpu0.idle_fraction -2.272376 # Percentage of idle cycles +system.cpu0.committedInsts 29354437 # Number of instructions committed +system.cpu0.committedOps 37594269 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 33819709 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 4399 # Number of float alu accesses +system.cpu0.num_func_calls 1050996 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 3901744 # number of instructions that are conditional controls +system.cpu0.num_int_insts 33819709 # number of integer instructions +system.cpu0.num_fp_insts 4399 # number of float instructions +system.cpu0.num_int_register_reads 193860060 # number of times the integer registers were read +system.cpu0.num_int_register_writes 36222671 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 2980 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1422 # number of times the floating registers were written +system.cpu0.num_mem_refs 13528220 # number of memory refs +system.cpu0.num_load_insts 7652095 # Number of load instructions +system.cpu0.num_store_insts 5876125 # Number of store instructions +system.cpu0.num_idle_cycles 3959269974.685009 # Number of idle cycles +system.cpu0.num_busy_cycles -1333655320.685009 # Number of busy cycles +system.cpu0.not_idle_fraction -0.507940 # Percentage of non-idle cycles +system.cpu0.idle_fraction 1.507940 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 83014 # 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Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 70.788428 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 19951126000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 211.269662 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu1.inst 299.611865 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.412636 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu1.inst 0.585179 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.997815 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 29481581 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 31170510 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 60652091 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 29481581 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 31170510 # 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average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13599.977374 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13926.334992 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13764.720918 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -710,158 +1145,158 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 413545 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 442640 # 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number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5158283000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 10080107000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4921824000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5158283000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 10080107000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 429084500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 429084500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 429084500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 429084500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014188 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013686 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013930 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014188 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.013686 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.013930 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014188 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.013686 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.013930 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11599.977374 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11926.334992 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11764.720918 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11599.977374 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11926.334992 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11764.720918 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11599.977374 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11926.334992 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11764.720918 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # 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Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::cpu1.data 0.725538 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.999830 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6510445 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 6686708 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13197153 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4886816 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 5087431 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 9974247 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 106752 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 129570 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 236322 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 112519 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 135213 # 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average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13593.111910 # average LoadLockedReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 21535.839197 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 21430.620811 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 21483.311702 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 21535.839197 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 21430.620811 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 21483.311702 # average overall miss latency +system.cpu0.dcache.replacements 627777 # number of replacements +system.cpu0.dcache.tagsinuse 511.879644 # Cycle average of tags in use +system.cpu0.dcache.total_refs 23662359 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 628289 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 37.661584 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 650252000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 250.372579 # Average occupied blocks per requestor +system.cpu0.dcache.occ_blocks::cpu1.data 261.507065 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.489009 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::cpu1.data 0.510756 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.999765 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6433193 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 6766702 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 13199895 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4991648 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 4983805 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 9975453 # 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miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.044973 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.046412 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026382 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.025713 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.026043 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026382 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.025713 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.026043 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14804.377653 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14618.131709 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14708.568272 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43235.379455 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 40410.705667 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 41880.049431 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13481.052275 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14456.887299 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13955.351709 # average LoadLockedReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26769.008256 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 24612.661591 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 25689.890188 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26769.008256 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 24612.661591 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 25689.890188 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -870,159 +1305,151 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 596298 # number of writebacks -system.cpu0.dcache.writebacks::total 596298 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 186239 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 182677 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 368916 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 123980 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 126580 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 250560 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 5767 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5644 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 11411 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 310219 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 309257 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 619476 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 310219 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 309257 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 619476 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2283659500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2226518000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4510177500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3776729000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 3782537500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7559266500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 68521500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 63767500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 132289000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6060388500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 6009055500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 12069444000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6060388500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 6009055500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 12069444000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91364168500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90730673500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182094842000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 9290730500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 9409303000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 18700033500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 117500 # number of LoadLockedReq MSHR uncacheable cycles -system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 117500 # number of LoadLockedReq MSHR uncacheable cycles -system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 69000 # number of StoreCondReq MSHR uncacheable cycles -system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 69000 # number of StoreCondReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 100654899000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 100139976500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 200794875500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027811 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026593 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.027194 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.024743 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.024277 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024505 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.051254 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.041741 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046062 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026498 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025594 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.026038 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026498 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025594 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.026038 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12261.983258 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12188.277670 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12225.486290 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30462.405227 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29882.584137 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30169.486351 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11881.654240 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11298.281361 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11593.111910 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19535.839197 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 19430.620811 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19483.311702 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19535.839197 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 19430.620811 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19483.311702 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 596576 # number of writebacks +system.cpu0.dcache.writebacks::total 596576 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 179297 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 189949 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 369246 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130279 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 120170 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 250449 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 5911 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5590 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 11501 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 309576 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 310119 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 619695 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 309576 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 310119 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 619695 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2295786500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2396801500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4692588000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5372104000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 4615814500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9987918500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 67864500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 69634000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 137498500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7667890500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7012616000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 14680506500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7667890500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7012616000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 14680506500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91527278500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90544684500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182071963000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13203337000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 13032051000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26235388000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 104730615500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103576735500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 208307351000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027115 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027305 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.027212 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025436 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023544 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024492 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.047860 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.044973 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046412 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026382 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025713 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.026043 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026382 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025713 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.026043 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12804.377653 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12618.131709 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12708.568272 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41235.379455 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38410.705667 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39880.049431 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11481.052275 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12456.887299 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11955.351709 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24769.008256 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 22612.661591 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23689.890188 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24769.008256 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22612.661591 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23689.890188 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_uncacheable_latency::cpu1.data inf # average LoadLockedReq mshr uncacheable latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_uncacheable_latency::total inf # average LoadLockedReq mshr uncacheable latency -system.cpu0.dcache.StoreCondReq_avg_mshr_uncacheable_latency::cpu1.data inf # average StoreCondReq mshr uncacheable latency -system.cpu0.dcache.StoreCondReq_avg_mshr_uncacheable_latency::total inf # average StoreCondReq mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 7594461 # DTB read hits -system.cpu1.dtb.read_misses 6935 # DTB read misses -system.cpu1.dtb.write_hits 5731015 # DTB write hits -system.cpu1.dtb.write_misses 1760 # DTB write misses -system.cpu1.dtb.flush_tlb 1276 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 7669515 # DTB read hits +system.cpu1.dtb.read_misses 7262 # DTB read misses +system.cpu1.dtb.write_hits 5604176 # DTB write hits +system.cpu1.dtb.write_misses 1826 # DTB write misses +system.cpu1.dtb.flush_tlb 1246 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 712 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 6410 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 727 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 6595 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 138 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 144 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 227 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 7601396 # DTB read accesses -system.cpu1.dtb.write_accesses 5732775 # DTB write accesses +system.cpu1.dtb.perms_faults 228 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 7676777 # DTB read accesses +system.cpu1.dtb.write_accesses 5606002 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 13325476 # DTB hits -system.cpu1.dtb.misses 8695 # DTB misses -system.cpu1.dtb.accesses 13334171 # DTB accesses -system.cpu1.itb.inst_hits 31195731 # ITB inst hits -system.cpu1.itb.inst_misses 3619 # ITB inst misses +system.cpu1.dtb.hits 13273691 # DTB hits +system.cpu1.dtb.misses 9088 # DTB misses +system.cpu1.dtb.accesses 13282779 # DTB accesses +system.cpu1.itb.inst_hits 31603022 # ITB inst hits +system.cpu1.itb.inst_misses 3724 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 1276 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 1246 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 712 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2687 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 727 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 2827 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 31199350 # ITB inst accesses -system.cpu1.itb.hits 31195731 # DTB hits -system.cpu1.itb.misses 3619 # DTB misses -system.cpu1.itb.accesses 31199350 # DTB accesses -system.cpu1.numCycles 2551680835 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 31606746 # ITB inst accesses +system.cpu1.itb.hits 31603022 # DTB hits +system.cpu1.itb.misses 3724 # DTB misses +system.cpu1.itb.accesses 31606746 # DTB accesses +system.cpu1.numCycles 2628693759 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 30572055 # Number of instructions committed -system.cpu1.committedOps 38927185 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 34988619 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 5077 # Number of float alu accesses -system.cpu1.num_func_calls 1115365 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 4021820 # number of instructions that are conditional controls -system.cpu1.num_int_insts 34988619 # number of integer instructions -system.cpu1.num_fp_insts 5077 # number of float instructions -system.cpu1.num_int_register_reads 200559291 # number of times the integer registers were read -system.cpu1.num_int_register_writes 37663256 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 3651 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1428 # number of times the floating registers were written -system.cpu1.num_mem_refs 13910241 # number of memory refs -system.cpu1.num_load_insts 7929873 # Number of load instructions -system.cpu1.num_store_insts 5980368 # Number of store instructions -system.cpu1.num_idle_cycles 10585260303.338047 # Number of idle cycles -system.cpu1.num_busy_cycles -8033579468.338046 # Number of busy cycles -system.cpu1.not_idle_fraction -3.148348 # Percentage of non-idle cycles -system.cpu1.idle_fraction 4.148348 # Percentage of idle cycles +system.cpu1.committedInsts 30860361 # Number of instructions committed +system.cpu1.committedOps 39028594 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 35068610 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 5870 # Number of float alu accesses +system.cpu1.num_func_calls 1089512 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 4048013 # number of instructions that are conditional controls +system.cpu1.num_int_insts 35068610 # number of integer instructions +system.cpu1.num_fp_insts 5870 # number of float instructions +system.cpu1.num_int_register_reads 201015882 # number of times the integer registers were read +system.cpu1.num_int_register_writes 37978161 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 4513 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1358 # number of times the floating registers were written +system.cpu1.num_mem_refs 13873832 # number of memory refs +system.cpu1.num_load_insts 8013211 # Number of load instructions +system.cpu1.num_store_insts 5860621 # Number of store instructions +system.cpu1.num_idle_cycles 952679619.816103 # Number of idle cycles +system.cpu1.num_busy_cycles 1676014139.183897 # Number of busy cycles +system.cpu1.not_idle_fraction 0.637584 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.362416 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.iocache.replacements 0 # number of replacements @@ -1039,10 +1466,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1195947261004 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1195947261004 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1195947261004 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1195947261004 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1482619780500 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1482619780500 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1482619780500 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1482619780500 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 8f4e7d03c..369e97796 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,134 +1,134 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.140938 # Number of seconds simulated -sim_ticks 5140937585000 # Number of ticks simulated -final_tick 5140937585000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.125717 # Number of seconds simulated +sim_ticks 5125716951000 # Number of ticks simulated +final_tick 5125716951000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 121697 # Simulator instruction rate (inst/s) -host_op_rate 240559 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1534230705 # Simulator tick rate (ticks/s) -host_mem_usage 773616 # Number of bytes of host memory used -host_seconds 3350.82 # Real time elapsed on the host -sim_insts 407786881 # Number of instructions simulated -sim_ops 806071515 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2479872 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3712 # Number of bytes read from this memory +host_inst_rate 203249 # Simulator instruction rate (inst/s) +host_op_rate 401765 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2555120499 # Simulator tick rate (ticks/s) +host_mem_usage 728844 # Number of bytes of host memory used +host_seconds 2006.06 # Real time elapsed on the host +sim_insts 407728401 # Number of instructions simulated +sim_ops 805963181 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2441920 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3904 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1026240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10765120 # Number of bytes read from this memory -system.physmem.bytes_read::total 14275328 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1026240 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1026240 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9536256 # Number of bytes written to this memory -system.physmem.bytes_written::total 9536256 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 38748 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 58 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu.inst 1027200 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10734912 # Number of bytes read from this memory +system.physmem.bytes_read::total 14208320 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1027200 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1027200 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9480000 # Number of bytes written to this memory +system.physmem.bytes_written::total 9480000 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 38155 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 61 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16035 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 168205 # Number of read requests responded to by this memory -system.physmem.num_reads::total 223052 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 149004 # Number of write requests responded to by this memory -system.physmem.num_writes::total 149004 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 482377 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 722 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu.inst 16050 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 167733 # Number of read requests responded to by this memory +system.physmem.num_reads::total 222005 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 148125 # Number of write requests responded to by this memory +system.physmem.num_writes::total 148125 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 476406 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 762 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 199621 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2093999 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2776795 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 199621 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 199621 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1854964 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1854964 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1854964 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 482377 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 722 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 200401 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2094324 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2771967 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 200401 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 200401 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1849497 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1849497 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1849497 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 476406 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 762 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 199621 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2093999 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4631759 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 223052 # Total number of read requests seen -system.physmem.writeReqs 149004 # Total number of write requests seen -system.physmem.cpureqs 373790 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 14275328 # Total number of bytes read from memory -system.physmem.bytesWritten 9536256 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 14275328 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 9536256 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 71 # Number of read reqs serviced by write Q +system.physmem.bw_total::cpu.inst 200401 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2094324 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4621465 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 222005 # Total number of read requests seen +system.physmem.writeReqs 148125 # Total number of write requests seen +system.physmem.cpureqs 371863 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 14208320 # Total number of bytes read from memory +system.physmem.bytesWritten 9480000 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 14208320 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 9480000 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 92 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 1726 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 13636 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 12914 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 13124 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 16345 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 13470 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 13111 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 13382 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 16266 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 13519 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 13235 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 13394 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 15885 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 13088 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 12601 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 13202 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 15809 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 8837 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 8387 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 8583 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 11810 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 8818 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 8522 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 8723 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 11661 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 8790 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 8601 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 8761 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 11230 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 8431 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 8093 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 8583 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 11174 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 13839 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 13931 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 14596 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 13757 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 13936 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 13652 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 13421 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 14010 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 13333 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 13233 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 13920 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 13971 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 14973 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 14183 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 13896 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 13262 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 9305 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 9392 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 9725 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 9208 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 9406 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 9142 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 8981 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 9409 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 8580 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 8586 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 9440 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 9338 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 10150 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 9429 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 9215 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 8819 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 8 # Number of times wr buffer was full causing retry -system.physmem.totGap 5140937531500 # Total gap between requests +system.physmem.numWrRetry 7 # Number of times wr buffer was full causing retry +system.physmem.totGap 5125716897500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 223052 # Categorize read packet sizes +system.physmem.readPktSize::6 222005 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 149004 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 172997 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 18175 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 7573 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3487 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3011 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2422 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1913 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1861 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1763 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1672 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1114 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1019 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 962 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 902 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 823 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 817 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 907 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 865 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 412 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 253 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 31 # What read queue length does an incoming req see +system.physmem.writePktSize::6 148125 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 174153 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 21252 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 7390 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2984 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2510 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2064 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1242 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1118 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1035 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 974 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 917 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 901 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 864 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 913 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 954 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 933 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 750 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 519 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 246 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 155 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 33 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see @@ -136,92 +136,347 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 5326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5675 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 6279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 6374 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 6421 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 6454 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 6466 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 6470 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 6471 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 6479 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 6478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 6478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 6478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 6478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 6478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 804 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 5396 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5689 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 6383 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 6417 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 6424 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 6425 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 6430 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 6431 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 6433 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 6440 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 6440 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 6440 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 6440 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 6440 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 6440 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6440 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6440 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6440 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6440 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6440 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6440 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6440 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6440 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 752 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 10 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8 # What write queue length does an incoming req see -system.physmem.totQLat 4794975750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 9301923250 # Sum of mem lat for all requests -system.physmem.totBusLat 1114905000 # Total cycles spent in databus access -system.physmem.totBankLat 3392042500 # Total cycles spent in bank access -system.physmem.avgQLat 21503.97 # Average queueing delay per request -system.physmem.avgBankLat 15212.25 # Average bank access latency per request +system.physmem.wrQLenPdf::31 7 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 62409 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 379.447836 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 154.150732 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1279.689060 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 27741 44.45% 44.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 9677 15.51% 59.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 5899 9.45% 69.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 3942 6.32% 75.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 2509 4.02% 79.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 2016 3.23% 82.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 1522 2.44% 85.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 1230 1.97% 87.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 938 1.50% 88.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 940 1.51% 90.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 553 0.89% 91.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 567 0.91% 92.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 409 0.66% 92.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 381 0.61% 93.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 350 0.56% 94.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 427 0.68% 94.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 299 0.48% 95.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 221 0.35% 95.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 157 0.25% 95.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 165 0.26% 96.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 170 0.27% 96.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 190 0.30% 96.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 458 0.73% 97.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 188 0.30% 97.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 102 0.16% 97.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 75 0.12% 97.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 65 0.10% 98.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 60 0.10% 98.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 37 0.06% 98.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 23 0.04% 98.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 21 0.03% 98.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 32 0.05% 98.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 22 0.04% 98.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 13 0.02% 98.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2243 10 0.02% 98.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 21 0.03% 98.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2371 16 0.03% 98.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 12 0.02% 98.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 13 0.02% 98.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2563 12 0.02% 98.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 9 0.01% 98.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 5 0.01% 98.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2755 7 0.01% 98.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 5 0.01% 98.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 4 0.01% 98.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2947 10 0.02% 98.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3011 4 0.01% 98.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 9 0.01% 98.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3139 9 0.01% 98.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3203 1 0.00% 98.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3267 6 0.01% 98.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3331 6 0.01% 98.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3395 2 0.00% 98.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3459 9 0.01% 98.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3523 3 0.00% 98.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3587 2 0.00% 98.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3651 3 0.00% 98.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3715 5 0.01% 98.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3779 13 0.02% 98.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3843 3 0.00% 98.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3907 5 0.01% 98.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3971 4 0.01% 98.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4035 3 0.00% 98.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4099 22 0.04% 98.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4163 5 0.01% 98.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4227 1 0.00% 98.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4291 2 0.00% 98.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4355 3 0.00% 98.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4419 3 0.00% 98.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4483 5 0.01% 98.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4547 2 0.00% 98.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4675 2 0.00% 98.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4739 1 0.00% 98.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4867 3 0.00% 98.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4931 2 0.00% 98.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4995 1 0.00% 98.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5059 2 0.00% 98.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5123 3 0.00% 98.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5187 6 0.01% 98.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5251 5 0.01% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5379 2 0.00% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5443 1 0.00% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5763 1 0.00% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5891 1 0.00% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6019 3 0.00% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6083 1 0.00% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6147 2 0.00% 98.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6211 1 0.00% 98.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6403 2 0.00% 98.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6467 3 0.00% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6531 1 0.00% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6659 1 0.00% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6723 7 0.01% 98.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6787 4 0.01% 98.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6851 4 0.01% 98.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6915 3 0.00% 98.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6979 4 0.01% 98.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7043 4 0.01% 98.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7107 1 0.00% 98.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7171 5 0.01% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7235 1 0.00% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7363 2 0.00% 98.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7427 1 0.00% 98.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7555 2 0.00% 98.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7619 1 0.00% 98.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7683 1 0.00% 98.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7875 2 0.00% 98.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7939 3 0.00% 98.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8003 1 0.00% 98.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8067 2 0.00% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8195 337 0.54% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8320-8323 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8384-8387 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8576-8579 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8963 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9024-9027 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9088-9091 2 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9219 2 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9344-9347 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9536-9539 7 0.01% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9600-9603 2 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9664-9667 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9731 3 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9856-9859 2 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9920-9923 2 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9987 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10048-10051 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10112-10115 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10304-10307 1 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10368-10371 1 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10432-10435 2 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10499 1 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10560-10563 3 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10624-10627 2 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10688-10691 1 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10755 2 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10816-10819 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10880-10883 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11392-11395 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11712-11715 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11779 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12160-12163 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12291 1 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12480-12483 2 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12672-12675 1 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12736-12739 1 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12864-12867 2 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12992-12995 2 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13440-13443 1 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13504-13507 1 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13571 2 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13827 1 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13952-13955 1 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14083 1 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14144-14147 2 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14211 1 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14339 1 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14400-14403 1 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14464-14467 1 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14656-14659 1 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14720-14723 2 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14915 34 0.05% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14979 14 0.02% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15040-15043 8 0.01% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15107 9 0.01% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15171 4 0.01% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15235 3 0.00% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15296-15299 6 0.01% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 4 0.01% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15424-15427 4 0.01% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15488-15491 5 0.01% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15552-15555 5 0.01% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15619 3 0.00% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15680-15683 5 0.01% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15744-15747 2 0.00% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15808-15811 7 0.01% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15875 5 0.01% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15936-15939 5 0.01% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16000-16003 7 0.01% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16064-16067 6 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16131 6 0.01% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16192-16195 6 0.01% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16256-16259 11 0.02% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16320-16323 13 0.02% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16387 65 0.10% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16448-16451 4 0.01% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16512-16515 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16576-16579 3 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16643 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16896-16899 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17088-17091 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17216-17219 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17344-17347 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17728-17731 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 62409 # Bytes accessed per row activation +system.physmem.totQLat 4001177249 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 8265005999 # Sum of mem lat for all requests +system.physmem.totBusLat 1109565000 # Total cycles spent in databus access +system.physmem.totBankLat 3154263750 # Total cycles spent in bank access +system.physmem.avgQLat 18030.39 # Average queueing delay per request +system.physmem.avgBankLat 14213.97 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 41716.21 # Average memory access latency -system.physmem.avgRdBW 2.78 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 37244.35 # Average memory access latency +system.physmem.avgRdBW 2.77 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 1.85 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 2.78 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 2.77 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 1.85 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 15.58 # Average write queue length over time -system.physmem.readRowHits 191257 # Number of row buffer hits during reads -system.physmem.writeRowHits 105612 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.77 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 70.88 # Row buffer hit rate for writes -system.physmem.avgGap 13817644.47 # Average gap between requests -system.iocache.replacements 47576 # number of replacements -system.iocache.tagsinuse 0.128763 # Cycle average of tags in use +system.physmem.avgWrQLen 11.40 # Average write queue length over time +system.physmem.readRowHits 198637 # Number of row buffer hits during reads +system.physmem.writeRowHits 108987 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.51 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.58 # Row buffer hit rate for writes +system.physmem.avgGap 13848423.25 # Average gap between requests +system.membus.throughput 5098961 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 662131 # Transaction distribution +system.membus.trans_dist::ReadResp 662131 # Transaction distribution +system.membus.trans_dist::WriteReq 13694 # Transaction distribution +system.membus.trans_dist::WriteResp 13694 # Transaction distribution +system.membus.trans_dist::Writeback 148125 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2235 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1745 # Transaction distribution +system.membus.trans_dist::ReadExReq 179249 # Transaction distribution +system.membus.trans_dist::ReadExResp 179246 # Transaction distribution +system.membus.trans_dist::MessageReq 1640 # Transaction distribution +system.membus.trans_dist::MessageResp 1640 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3280 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3280 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 473788 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 470782 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775064 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1719634 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 132454 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 132454 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 606242 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.bridge.slave 470782 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.cpu.interrupts.pio 775064 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.cpu.interrupts.int_slave 3280 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1855368 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6560 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::total 6560 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18259712 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241674 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550125 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 20051511 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5428608 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 5428608 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 23688320 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.bridge.slave 241674 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.cpu.interrupts.pio 1550125 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.cpu.interrupts.int_slave 6560 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 25486679 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 25486679 # Total data (bytes) +system.membus.snoop_data_through_bus 649152 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 1603689497 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 250319000 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 583198000 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer3.occupancy 3280000 # Layer occupancy (ticks) +system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.membus.respLayer0.occupancy 1640000 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 3152452403 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.1 # Layer utilization (%) +system.membus.respLayer4.occupancy 429424246 # Layer occupancy (ticks) +system.membus.respLayer4.utilization 0.0 # Layer utilization (%) +system.iocache.replacements 47577 # number of replacements +system.iocache.tagsinuse 0.079131 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47592 # Sample count of references to valid blocks. +system.iocache.sampled_refs 47593 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 4991974997000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.128763 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.008048 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.008048 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 911 # number of ReadReq misses -system.iocache.ReadReq_misses::total 911 # number of ReadReq misses +system.iocache.warmup_cycle 4992752531000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::pc.south_bridge.ide 0.079131 # Average occupied blocks per requestor +system.iocache.occ_percent::pc.south_bridge.ide 0.004946 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.004946 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 912 # number of ReadReq misses +system.iocache.ReadReq_misses::total 912 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47631 # number of demand (read+write) misses -system.iocache.demand_misses::total 47631 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47631 # number of overall misses -system.iocache.overall_misses::total 47631 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 147497397 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 147497397 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10072244306 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10072244306 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 10219741703 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10219741703 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 10219741703 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10219741703 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 911 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 911 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47632 # number of demand (read+write) misses +system.iocache.demand_misses::total 47632 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47632 # number of overall misses +system.iocache.overall_misses::total 47632 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 152414185 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 152414185 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10346136346 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10346136346 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 10498550531 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10498550531 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 10498550531 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10498550531 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 912 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 912 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47631 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47631 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47631 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47631 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47632 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47632 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47632 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47632 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -230,40 +485,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 161907.131723 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 161907.131723 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 215587.420933 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 215587.420933 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 214560.721022 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 214560.721022 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 214560.721022 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 214560.721022 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 139153 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167120.816886 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 167120.816886 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 221449.836173 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 221449.836173 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 220409.609737 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 220409.609737 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 220409.609737 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 220409.609737 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 148997 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 12645 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 13662 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 11.004587 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.905943 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 911 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 911 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 912 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 912 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 47631 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 47631 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 47631 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 47631 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 100104427 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 100104427 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7641446543 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 7641446543 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7741550970 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 7741550970 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7741550970 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 7741550970 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 47632 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 47632 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 47632 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 47632 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 104973685 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 104973685 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7915976600 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 7915976600 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8020950285 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8020950285 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8020950285 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8020950285 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -272,14 +527,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 109884.113063 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 109884.113063 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 163558.359225 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 163558.359225 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 162531.774895 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 162531.774895 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 162531.774895 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 162531.774895 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115102.724781 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 115102.724781 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 169434.430651 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 169434.430651 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 168394.152775 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 168394.152775 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 168394.152775 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 168394.152775 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -293,144 +548,286 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.branchPred.lookups 85620726 # Number of BP lookups -system.cpu.branchPred.condPredicted 85620726 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 882198 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 79268619 # Number of BTB lookups -system.cpu.branchPred.BTBHits 77534559 # Number of BTB hits +system.iobus.throughput 639145 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 225496 # Transaction distribution +system.iobus.trans_dist::ReadResp 225496 # Transaction distribution +system.iobus.trans_dist::WriteReq 57527 # Transaction distribution +system.iobus.trans_dist::WriteResp 57527 # Transaction distribution +system.iobus.trans_dist::MessageReq 1640 # Transaction distribution +system.iobus.trans_dist::MessageResp 1640 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 427356 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 26980 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 470782 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95264 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95264 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3280 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3280 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.apicbridge.slave 3280 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.south_bridge.speaker.pio 427356 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.com_1.pio 26980 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.iocache.cpu_side 95264 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 569326 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 213678 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 13490 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 241674 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027840 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027840 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6560 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6560 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.apicbridge.slave 6560 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.south_bridge.speaker.pio 213678 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.com_1.pio 13490 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.iocache.cpu_side 3027840 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 3276074 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 3276074 # Total data (bytes) +system.iobus.reqLayer0.occupancy 3909656 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 8851000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) +system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks) +system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer6.occupancy 70000 # Layer occupancy (ticks) +system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks) +system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks) +system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer9.occupancy 213679000 # Layer occupancy (ticks) +system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks) +system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks) +system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 20182000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer18.occupancy 424474531 # Layer occupancy (ticks) +system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks) +system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 459975000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer1.occupancy 52352000 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer2.occupancy 1640000 # Layer occupancy (ticks) +system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) +system.cpu.branchPred.lookups 85601186 # Number of BP lookups +system.cpu.branchPred.condPredicted 85601186 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 878782 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 79197718 # Number of BTB lookups +system.cpu.branchPred.BTBHits 77534768 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.812426 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1442315 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 180251 # Number of incorrect RAS predictions. -system.cpu.numCycles 447791761 # number of cpu cycles simulated +system.cpu.branchPred.BTBHitPct 97.900255 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1440711 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 178764 # Number of incorrect RAS predictions. +system.cpu.numCycles 453375451 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 25559948 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 422856490 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85620726 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 78976874 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 162677741 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4000997 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 98298 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 65919320 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 43594 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 86507 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 459 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8492083 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 383635 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 2345 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 257461374 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.243647 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.415529 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 25513858 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 422800544 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85601186 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 78975479 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 162663365 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3996734 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 101966 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 70853615 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 42658 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 89309 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 281 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8479708 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 381834 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 2341 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 262338796 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.182647 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.411668 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 95198026 36.98% 36.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1534816 0.60% 37.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 71825104 27.90% 65.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 895357 0.35% 65.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1570607 0.61% 66.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2391332 0.93% 67.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1020158 0.40% 67.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1325162 0.51% 68.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 81700812 31.73% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 100089762 38.15% 38.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1543248 0.59% 38.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 71824716 27.38% 66.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 898472 0.34% 66.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1568808 0.60% 67.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2394853 0.91% 67.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1014354 0.39% 68.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1328708 0.51% 68.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 81675875 31.13% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 257461374 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.191207 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.944315 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 29461192 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 63064302 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 158550724 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3309649 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3075507 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 832761340 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 863 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3075507 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 32153278 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 38465118 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 12079112 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 158824437 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 12863922 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 829829025 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 19879 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 6055166 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4924546 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 11525 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 991492877 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1800847756 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1800847292 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 464 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 963999366 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27493506 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 456551 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 462682 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 29304477 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 16752339 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 9837983 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1099709 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 928773 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 825036488 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1186686 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 821069910 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 146070 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 19309743 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 29357166 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 131932 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 257461374 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 3.189099 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.383585 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 262338796 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.188809 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.932562 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 29417456 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 68001358 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 158506679 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3339559 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3073744 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 832592947 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 926 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3073744 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 32109829 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 42827309 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 12461023 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 158801746 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 13065145 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 829696742 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 21430 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 6044181 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 5137835 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 10653 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 991365298 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1800497636 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1800497180 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 456 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 963871300 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 27493996 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 453983 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 458205 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 29510312 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 16729516 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 9820056 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1138043 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 956999 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 824928716 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1184630 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 820966425 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 150849 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 19304203 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 29360127 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 130755 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 262338796 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 3.129413 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.399539 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 71259249 27.68% 27.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 15575755 6.05% 33.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 10479111 4.07% 37.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7383615 2.87% 40.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 75752504 29.42% 70.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3772068 1.47% 71.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72307575 28.08% 99.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 782694 0.30% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 148803 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 75996420 28.97% 28.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 15740261 6.00% 34.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 10531012 4.01% 38.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7367834 2.81% 41.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 75736075 28.87% 70.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3750663 1.43% 72.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72297854 27.56% 99.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 773517 0.29% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 145160 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 257461374 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 262338796 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 356313 33.63% 33.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 241 0.02% 33.66% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 2452 0.23% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 547502 51.68% 85.57% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 152922 14.43% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 351269 33.33% 33.33% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 200 0.02% 33.35% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 1810 0.17% 33.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 33.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 33.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 33.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.52% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 547247 51.93% 85.45% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 153387 14.55% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 308526 0.04% 0.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 793557907 96.65% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 150412 0.02% 96.71% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 124298 0.02% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 304863 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 793498796 96.65% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 149830 0.02% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 124227 0.02% 96.72% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.72% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.72% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.72% # Type of FU issued @@ -457,246 +854,280 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.72% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.72% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.72% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 17694567 2.16% 98.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9234200 1.12% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 17669358 2.15% 98.88% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9219351 1.12% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 821069910 # Type of FU issued -system.cpu.iq.rate 1.833598 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1059430 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001290 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1900915279 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 845543458 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 817157785 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 194 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 212 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 52 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 821820724 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 90 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1686147 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 820966425 # Type of FU issued +system.cpu.iq.rate 1.810787 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1053913 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001284 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1905583532 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 845427964 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 817056658 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 193 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 210 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 50 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 821715388 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 87 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1694689 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2748440 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 17101 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11930 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1411969 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2746767 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 18051 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 12083 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1403061 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1931504 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 11624 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1931249 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 12313 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3075507 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 26873503 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2150322 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 826223174 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 241070 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 16752339 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 9837983 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 692103 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1621529 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 12267 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11930 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 498132 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 506603 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1004735 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 819660888 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 17391685 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1409021 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3073744 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 30976434 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2152665 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 826113346 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 242094 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 16729516 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 9820056 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 689859 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1619870 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 14784 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 12083 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 494405 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 508019 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1002424 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 819559028 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 17368747 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1407396 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 26440023 # number of memory reference insts executed -system.cpu.iew.exec_branches 83107253 # Number of branches executed -system.cpu.iew.exec_stores 9048338 # Number of stores executed -system.cpu.iew.exec_rate 1.830451 # Inst execution rate -system.cpu.iew.wb_sent 819258374 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 817157837 # cumulative count of insts written-back -system.cpu.iew.wb_producers 638799704 # num instructions producing a value -system.cpu.iew.wb_consumers 1044337102 # num instructions consuming a value +system.cpu.iew.exec_refs 26403485 # number of memory reference insts executed +system.cpu.iew.exec_branches 83095032 # Number of branches executed +system.cpu.iew.exec_stores 9034738 # Number of stores executed +system.cpu.iew.exec_rate 1.807683 # Inst execution rate +system.cpu.iew.wb_sent 819157526 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 817056708 # cumulative count of insts written-back +system.cpu.iew.wb_producers 638600685 # num instructions producing a value +system.cpu.iew.wb_consumers 1043925557 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.824861 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.611680 # average fanout of values written-back +system.cpu.iew.wb_rate 1.802164 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.611730 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 20042352 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1054753 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 891546 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 254385866 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 3.168696 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.858566 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 20041054 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1053875 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 888667 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 259265052 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 3.108646 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.863485 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 82972146 32.62% 32.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11724447 4.61% 37.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3813249 1.50% 38.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 74747378 29.38% 68.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2384925 0.94% 69.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1476326 0.58% 69.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 865615 0.34% 69.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 70850824 27.85% 97.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5550956 2.18% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 87759364 33.85% 33.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11842879 4.57% 38.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3826328 1.48% 39.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74742270 28.83% 68.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2381968 0.92% 69.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1473831 0.57% 70.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 858574 0.33% 70.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 70846339 27.33% 97.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5533499 2.13% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 254385866 # Number of insts commited each cycle -system.cpu.commit.committedInsts 407786881 # Number of instructions committed -system.cpu.commit.committedOps 806071515 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 259265052 # Number of insts commited each cycle +system.cpu.commit.committedInsts 407728401 # Number of instructions committed +system.cpu.commit.committedOps 805963181 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22429911 # Number of memory references committed -system.cpu.commit.loads 14003897 # Number of loads committed -system.cpu.commit.membars 474463 # Number of memory barriers committed -system.cpu.commit.branches 82163817 # Number of branches committed +system.cpu.commit.refs 22399743 # Number of memory references committed +system.cpu.commit.loads 13982748 # Number of loads committed +system.cpu.commit.membars 474399 # Number of memory barriers committed +system.cpu.commit.branches 82153759 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 735061477 # Number of committed integer instructions. -system.cpu.commit.function_calls 1156045 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5550956 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 734952654 # Number of committed integer instructions. +system.cpu.commit.function_calls 1154691 # Number of function calls committed. +system.cpu.commit.bw_lim_events 5533499 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1074870508 # The number of ROB reads -system.cpu.rob.rob_writes 1655318425 # The number of ROB writes -system.cpu.timesIdled 1256763 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 190330387 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9834088814 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 407786881 # Number of Instructions Simulated -system.cpu.committedOps 806071515 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 407786881 # Number of Instructions Simulated -system.cpu.cpi 1.098102 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.098102 # CPI: Total CPI of All Threads -system.cpu.ipc 0.910662 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.910662 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1504614065 # number of integer regfile reads -system.cpu.int_regfile_writes 975429838 # number of integer regfile writes -system.cpu.fp_regfile_reads 52 # number of floating regfile reads -system.cpu.misc_regfile_reads 264130300 # number of misc regfile reads -system.cpu.misc_regfile_writes 403010 # number of misc regfile writes -system.cpu.icache.replacements 955437 # number of replacements -system.cpu.icache.tagsinuse 509.903328 # Cycle average of tags in use -system.cpu.icache.total_refs 7482159 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 955949 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.826944 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 146514700000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 509.903328 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.995905 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.995905 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 7482159 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7482159 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7482159 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7482159 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7482159 # number of overall hits -system.cpu.icache.overall_hits::total 7482159 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1009922 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1009922 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1009922 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1009922 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1009922 # number of overall misses -system.cpu.icache.overall_misses::total 1009922 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13938284992 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13938284992 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13938284992 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13938284992 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13938284992 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13938284992 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8492081 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8492081 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8492081 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8492081 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8492081 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8492081 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.118925 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.118925 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.118925 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.118925 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.118925 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.118925 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13801.348017 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13801.348017 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13801.348017 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13801.348017 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13801.348017 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13801.348017 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 8199 # number of cycles access was blocked +system.cpu.rob.rob_reads 1079657633 # The number of ROB reads +system.cpu.rob.rob_writes 1655096826 # The number of ROB writes +system.cpu.timesIdled 1258785 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 191036655 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9798064041 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 407728401 # Number of Instructions Simulated +system.cpu.committedOps 805963181 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 407728401 # Number of Instructions Simulated +system.cpu.cpi 1.111955 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.111955 # CPI: Total CPI of All Threads +system.cpu.ipc 0.899317 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.899317 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1504349061 # number of integer regfile reads +system.cpu.int_regfile_writes 975319683 # number of integer regfile writes +system.cpu.fp_regfile_reads 50 # number of floating regfile reads +system.cpu.misc_regfile_reads 264080509 # number of misc regfile reads +system.cpu.misc_regfile_writes 401987 # number of misc regfile writes +system.cpu.toL2Bus.throughput 53625221 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 3010668 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3010129 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 13694 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 13694 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1578360 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2289 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2289 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 334262 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 287551 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1907708 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 6121795 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side 17377 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side 150658 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 8197538 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 61043136 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 207549047 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side 553408 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side 5256448 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 274402039 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 274377591 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 490112 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 4031070918 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.snoopLayer0.occupancy 573000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1431698822 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 3102593965 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer2.occupancy 13102485 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer3.occupancy 102839393 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.cpu.icache.replacements 953322 # number of replacements +system.cpu.icache.tagsinuse 510.127378 # Cycle average of tags in use +system.cpu.icache.total_refs 7473092 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 953834 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.834793 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 147390294000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 510.127378 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.996343 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.996343 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 7473092 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7473092 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7473092 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7473092 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7473092 # number of overall hits +system.cpu.icache.overall_hits::total 7473092 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1006614 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1006614 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1006614 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1006614 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1006614 # number of overall misses +system.cpu.icache.overall_misses::total 1006614 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14222924496 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14222924496 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14222924496 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14222924496 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14222924496 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14222924496 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 8479706 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8479706 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 8479706 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 8479706 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 8479706 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 8479706 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.118709 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.118709 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.118709 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.118709 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.118709 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.118709 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14129.472167 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14129.472167 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14129.472167 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14129.472167 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14129.472167 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14129.472167 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 8172 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 203 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 189 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 40.389163 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 43.238095 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 53908 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 53908 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 53908 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 53908 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 53908 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 53908 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 956014 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 956014 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 956014 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 956014 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 956014 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 956014 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11502740492 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11502740492 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11502740492 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11502740492 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11502740492 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11502740492 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.112577 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.112577 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.112577 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.112577 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.112577 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.112577 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12031.979126 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12031.979126 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12031.979126 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12031.979126 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12031.979126 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12031.979126 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 52705 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 52705 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 52705 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 52705 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 52705 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 52705 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 953909 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 953909 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 953909 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 953909 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 953909 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 953909 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11745970674 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11745970674 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11745970674 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11745970674 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11745970674 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11745970674 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.112493 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.112493 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.112493 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.112493 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.112493 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.112493 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12313.512792 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12313.512792 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12313.512792 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12313.512792 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12313.512792 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12313.512792 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 7960 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 6.326712 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 20386 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 7973 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 2.556879 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5107329698000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.326712 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.395420 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.395420 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 20403 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 20403 # number of ReadReq hits +system.cpu.itb_walker_cache.replacements 7857 # number of replacements +system.cpu.itb_walker_cache.tagsinuse 6.317656 # Cycle average of tags in use +system.cpu.itb_walker_cache.total_refs 21864 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.sampled_refs 7868 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.avg_refs 2.778851 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.warmup_cycle 5104284128000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.317656 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.394853 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_percent::total 0.394853 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 21875 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 21875 # 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number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 96821500 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 96821500 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 96821500 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 96821500 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 96821500 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 96821500 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 29246 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 29246 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 21877 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 21877 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 21877 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 21877 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 8730 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 8730 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 8730 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 8730 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 8730 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 8730 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 99800500 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 99800500 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 99800500 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 99800500 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 99800500 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 99800500 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 30605 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 30605 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 29248 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 29248 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 29248 # 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average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10948.942667 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10948.942667 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10948.942667 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 30607 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 30607 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 30607 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 30607 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.285248 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.285248 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.285229 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.285229 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.285229 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.285229 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11431.901489 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11431.901489 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11431.901489 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11431.901489 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11431.901489 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11431.901489 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -705,78 +1136,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 1394 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 1394 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 8843 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 8843 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 8843 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 8843 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 8843 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 8843 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 79135500 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 79135500 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 79135500 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 79135500 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 79135500 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 79135500 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.302366 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.302366 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.302345 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.302345 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.302345 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.302345 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8948.942667 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8948.942667 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8948.942667 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8948.942667 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8948.942667 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8948.942667 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 1569 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 1569 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 8730 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 8730 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 8730 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 8730 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 8730 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 8730 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 82333015 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 82333015 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 82333015 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 82333015 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 82333015 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 82333015 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.285248 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.285248 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.285229 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.285229 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.285229 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.285229 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9431.044101 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9431.044101 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9431.044101 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9431.044101 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9431.044101 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9431.044101 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 67560 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 14.837353 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 92239 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 67575 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.364987 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5100574572500 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 14.837353 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.927335 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.927335 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 92240 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 92240 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 92240 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 92240 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 92240 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 92240 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 68644 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 68644 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 68644 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 68644 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 68644 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 68644 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 852599000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 852599000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 852599000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 852599000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 852599000 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 852599000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 160884 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 160884 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 160884 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 160884 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 160884 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 160884 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.426668 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.426668 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.426668 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.426668 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.426668 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.426668 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12420.590292 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12420.590292 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12420.590292 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12420.590292 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12420.590292 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12420.590292 # average overall miss latency +system.cpu.dtb_walker_cache.replacements 67431 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 14.830291 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 90986 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 67447 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.349000 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 4994048518000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 14.830291 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.926893 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.926893 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 90986 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 90986 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 90986 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 90986 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 90986 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 90986 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 68526 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 68526 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 68526 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 68526 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 68526 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 68526 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 854232500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 854232500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 854232500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 854232500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 854232500 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 854232500 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 159512 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 159512 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 159512 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 159512 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 159512 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 159512 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.429598 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.429598 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.429598 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.429598 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.429598 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.429598 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12465.815895 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12465.815895 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12465.815895 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12465.815895 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12465.815895 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12465.815895 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -785,146 +1216,146 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 19876 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 19876 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 68644 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 68644 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 68644 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 68644 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 68644 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 68644 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 715311000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 715311000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 715311000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 715311000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 715311000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 715311000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.426668 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.426668 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.426668 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.426668 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.426668 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.426668 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10420.590292 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10420.590292 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10420.590292 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10420.590292 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10420.590292 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10420.590292 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 18479 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 18479 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 68526 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 68526 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 68526 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 68526 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 68526 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 68526 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 717130107 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 717130107 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 717130107 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 717130107 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 717130107 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 717130107 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.429598 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.429598 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.429598 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.429598 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.429598 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.429598 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10465.080510 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10465.080510 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10465.080510 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10465.080510 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10465.080510 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10465.080510 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1655094 # number of replacements -system.cpu.dcache.tagsinuse 511.995445 # Cycle average of tags in use -system.cpu.dcache.total_refs 19021390 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1655606 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11.489080 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 27980000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.995445 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999991 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999991 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 10917270 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 10917270 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8101435 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8101435 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 19018705 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 19018705 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 19018705 # number of overall hits -system.cpu.dcache.overall_hits::total 19018705 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2239579 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2239579 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 315092 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 315092 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2554671 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2554671 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2554671 # number of overall misses -system.cpu.dcache.overall_misses::total 2554671 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 31946998000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 31946998000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9622210995 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9622210995 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 41569208995 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 41569208995 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 41569208995 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 41569208995 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13156849 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13156849 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8416527 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8416527 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21573376 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21573376 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21573376 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21573376 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.170222 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.170222 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037437 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037437 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.118418 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.118418 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.118418 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.118418 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14264.733684 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14264.733684 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30537.782600 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30537.782600 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16271.844396 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16271.844396 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16271.844396 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16271.844396 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 387071 # number of cycles access was blocked +system.cpu.dcache.replacements 1656381 # number of replacements +system.cpu.dcache.tagsinuse 511.996762 # Cycle average of tags in use +system.cpu.dcache.total_refs 18981789 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1656893 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 11.456255 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 37864000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.996762 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 10887156 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 10887156 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8091896 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8091896 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 18979052 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 18979052 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 18979052 # number of overall hits +system.cpu.dcache.overall_hits::total 18979052 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2237799 # 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number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 45129599996 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 45129599996 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 45129599996 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13124955 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13124955 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8407521 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8407521 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21532476 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21532476 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21532476 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21532476 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.170500 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.170500 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037541 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037541 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.118585 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.118585 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.118585 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.118585 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14795.104922 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14795.104922 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38086.745334 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38086.745334 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 17674.150472 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 17674.150472 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 17674.150472 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 17674.150472 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 405217 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 42390 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 42719 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.131187 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.485639 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1557214 # number of writebacks -system.cpu.dcache.writebacks::total 1557214 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 870911 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 870911 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 25892 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 25892 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 896803 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 896803 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 896803 # 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number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8794383495 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8794383495 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26195542495 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26195542495 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26195542495 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26195542495 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97349101500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97349101500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2522345500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2522345500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99871447000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 99871447000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.104027 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.104027 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034361 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034361 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076848 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.076848 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076848 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.076848 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12713.937200 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12713.937200 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30409.348185 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30409.348185 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15800.740768 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 15800.740768 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15800.740768 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 15800.740768 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1558312 # number of writebacks +system.cpu.dcache.writebacks::total 1558312 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 868331 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 868331 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 25900 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 25900 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 894231 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 894231 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 894231 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 894231 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1369468 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1369468 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289725 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 289725 # 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number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 29072561031 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97349104500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97349104500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2521383000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2521383000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99870487500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 99870487500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.104341 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.104341 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034460 # 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mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021823 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.824355 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.824355 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.463382 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.463382 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000920 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000898 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016775 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102205 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.069106 # 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average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 51667.666667 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56320.783037 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43321.480878 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44455.084460 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_misses::cpu.inst 16050 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 168662 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 184779 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 5260750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 430000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1193323263 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2545977303 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3744991316 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 15894959 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 15894959 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7671814321 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7671814321 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 5260750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 430000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1193323263 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10217791624 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 11416805637 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 5260750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 430000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1193323263 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10217791624 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 11416805637 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89236814500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89236814500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2356578000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2356578000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91593392500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91593392500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000958 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000848 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016827 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026209 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021724 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.823791 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.823791 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.461819 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.461819 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000958 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000848 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016827 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.101833 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.068927 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000958 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000848 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016827 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.101833 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.068927 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 86241.803279 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 71666.666667 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 74350.359065 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70971.965071 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 72032.916253 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10725.343455 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10725.343455 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57774.471688 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57774.471688 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 86241.803279 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 71666.666667 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74350.359065 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60581.468404 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61786.272450 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 86241.803279 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 71666.666667 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74350.359065 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60581.468404 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61786.272450 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt index f3136422c..11c0ff3fa 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt @@ -1,121 +1,121 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 5.205149 # Number of seconds simulated -sim_ticks 5205148879000 # Number of ticks simulated -final_tick 5205148879000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 5205149326500 # Number of ticks simulated +final_tick 5205149326500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 131600 # Simulator instruction rate (inst/s) -host_op_rate 252290 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6421585329 # Simulator tick rate (ticks/s) -host_mem_usage 872300 # Number of bytes of host memory used -host_seconds 810.57 # Real time elapsed on the host -sim_insts 106671342 # Number of instructions simulated -sim_ops 204498751 # Number of ops (including micro ops) simulated +host_inst_rate 156279 # Simulator instruction rate (inst/s) +host_op_rate 299599 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7625516175 # Simulator tick rate (ticks/s) +host_mem_usage 825184 # Number of bytes of host memory used +host_seconds 682.60 # Real time elapsed on the host +sim_insts 106675228 # Number of instructions simulated +sim_ops 204505420 # Number of ops (including micro ops) simulated system.physmem.bytes_read::pc.south_bridge.ide 35240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 160344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 160408 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 75328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 562944184 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 41978278 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 62896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 563007384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 41989554 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 62960 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 30152 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 448071240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 51341424 # Number of bytes read from this memory -system.physmem.bytes_read::total 1104699086 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 562944184 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 448071240 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1011015424 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu1.inst 448053480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 51339228 # Number of bytes read from this memory +system.physmem.bytes_read::total 1104753734 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 563007384 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 448053480 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1011060864 # Number of instructions bytes read from this memory system.physmem.bytes_written::pc.south_bridge.ide 2991104 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.itb.walker 16 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 33612947 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 34199698 # Number of bytes written to this memory -system.physmem.bytes_written::total 70803765 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 33620576 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 34199208 # Number of bytes written to this memory +system.physmem.bytes_written::total 70810904 # Number of bytes written to this memory system.physmem.num_reads::pc.south_bridge.ide 821 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 20043 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 20051 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 9416 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 70368023 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 6999506 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 7862 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 70375923 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 7001118 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 7870 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 3769 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 56008905 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 8662168 # Number of read requests responded to by this memory -system.physmem.num_reads::total 142080513 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 56006685 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 8661478 # Number of read requests responded to by this memory +system.physmem.num_reads::total 142087131 # Number of read requests responded to by this memory system.physmem.num_writes::pc.south_bridge.ide 46736 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.itb.walker 2 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 5025316 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 4781707 # Number of write requests responded to by this memory -system.physmem.num_writes::total 9853761 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 5026389 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 4781632 # Number of write requests responded to by this memory +system.physmem.num_writes::total 9854759 # Number of write requests responded to by this memory system.physmem.bw_read::pc.south_bridge.ide 6770 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 30805 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 30817 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 14472 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 108151409 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 8064760 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 12083 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 108163541 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 8066926 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 12096 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 5793 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 86082310 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 9863584 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 212231986 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 108151409 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 86082310 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 194233719 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 86078891 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 9863161 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 212242467 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 108163541 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 86078891 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 194242432 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::pc.south_bridge.ide 574643 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.itb.walker 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6457634 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 6570359 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 13602640 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 581414 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 30805 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6459099 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 6570265 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 13604010 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 581413 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 30817 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 14475 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 108151409 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 14522394 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 12083 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 108163541 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 14526025 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 12096 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 5793 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 86082310 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 16433943 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 225834626 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 86078891 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 16433426 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 225846477 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 821 # Total number of read requests seen system.physmem.writeReqs 46736 # Total number of write requests seen -system.physmem.cpureqs 47279 # Reqs generatd by CPU via cache - shady +system.physmem.cpureqs 47259 # Reqs generatd by CPU via cache - shady system.physmem.bytesRead 52544 # Total number of bytes read from memory system.physmem.bytesWritten 2991104 # Total number of bytes written to memory system.physmem.bytesConsumedRd 35240 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 2991104 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 32 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 48 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 64 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 309 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 32 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 64 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 64 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 48 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 80 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 48 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 16 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 16 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 32 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 48 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 48 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 32 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 32 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 48 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 32 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 16 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 16 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 32 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 80 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 325 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 16 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 2992 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 2832 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 3024 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 2944 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 2992 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 2960 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 2968 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 2992 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 2856 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 2864 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 2896 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 2800 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 2864 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 2864 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 2960 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 2928 # Track writes on a per bank basis +system.physmem.perBankWrReqs::0 2816 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 2864 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 2640 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 2768 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 2768 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 3064 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 2648 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 2816 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 3232 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 3312 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 3248 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 3024 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 2976 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 2672 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 2880 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 3008 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 31 # Number of times wr buffer was full causing retry -system.physmem.totGap 64277169000 # Total gap between requests +system.physmem.numWrRetry 11 # Number of times wr buffer was full causing retry +system.physmem.totGap 64277565999 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -162,15 +162,15 @@ system.physmem.rdQLenPdf::28 2 # Wh system.physmem.rdQLenPdf::29 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 2 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1965 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1995 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1997 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1997 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1997 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1997 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1998 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1999 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2010 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 2020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 2021 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 2021 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 2032 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 2032 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 2032 # What write queue length does an incoming req see @@ -185,23 +185,66 @@ system.physmem.wrQLenPdf::19 2032 # Wh system.physmem.wrQLenPdf::20 2032 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 2032 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 2032 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 33 # What write queue length does an incoming req see -system.physmem.totQLat 41690522 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 53523022 # Sum of mem lat for all requests +system.physmem.wrQLenPdf::23 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 11 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 539 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 5552.207792 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 3362.695639 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 3316.858883 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 30 5.57% 5.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 2 0.37% 5.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 6 1.11% 7.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 9 1.67% 8.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 2 0.37% 9.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 3 0.56% 9.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 1 0.19% 9.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 1 0.19% 10.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 1 0.19% 10.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 2 0.37% 10.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 2 0.37% 10.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 1 0.19% 11.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 2 0.37% 11.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 1 0.19% 11.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 2 0.37% 12.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 69 12.80% 24.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 1 0.19% 25.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 3 0.56% 25.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 2 0.37% 25.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 2 0.37% 26.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 1 0.19% 26.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 1 0.19% 26.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 1 0.19% 26.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 11 2.04% 28.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 1 0.19% 29.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 9 1.67% 30.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 1 0.19% 30.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 1 0.19% 31.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 1 0.19% 31.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 41 7.61% 38.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 6 1.11% 40.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 1 0.19% 40.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 4 0.74% 41.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 1 0.19% 41.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 5 0.93% 42.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 1 0.19% 42.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7809 1 0.19% 42.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 310 57.51% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 539 # Bytes accessed per row activation +system.physmem.totQLat 47710768 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 58058268 # Sum of mem lat for all requests system.physmem.totBusLat 4105000 # Total cycles spent in databus access -system.physmem.totBankLat 7727500 # Total cycles spent in bank access -system.physmem.avgQLat 50780.17 # Average queueing delay per request -system.physmem.avgBankLat 9412.30 # Average bank access latency per request +system.physmem.totBankLat 6242500 # Total cycles spent in bank access +system.physmem.avgQLat 58112.99 # Average queueing delay per request +system.physmem.avgBankLat 7603.53 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 65192.48 # Average memory access latency +system.physmem.avgMemAccLat 70716.53 # Average memory access latency system.physmem.avgRdBW 0.01 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.57 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 0.01 # Average consumed read bandwidth in MB/s @@ -210,11 +253,207 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.00 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.15 # Average write queue length over time -system.physmem.readRowHits 704 # Number of row buffer hits during reads -system.physmem.writeRowHits 45223 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.75 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 96.76 # Row buffer hit rate for writes -system.physmem.avgGap 1351581.66 # Average gap between requests +system.physmem.readRowHits 756 # Number of row buffer hits during reads +system.physmem.writeRowHits 46262 # Number of row buffer hits during writes +system.physmem.readRowHitRate 92.08 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 98.99 # Row buffer hit rate for writes +system.physmem.avgGap 1351590.01 # Average gap between requests +system.piobus.throughput 974238 # Throughput (bytes/s) +system.piobus.trans_dist::ReadReq 863748 # Transaction distribution +system.piobus.trans_dist::ReadResp 863748 # Transaction distribution +system.piobus.trans_dist::WriteReq 83560 # Transaction distribution +system.piobus.trans_dist::WriteResp 83560 # Transaction distribution +system.piobus.trans_dist::MessageReq 1915 # Transaction distribution +system.piobus.trans_dist::MessageResp 1915 # Transaction distribution +system.piobus.pkt_count_system.pc.south_bridge.ide.dma::system.physmem.port 95114 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.pc.south_bridge.ide.dma::total 95114 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.cpu0.interrupts.int_slave 1680 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.cpu1.interrupts.int_slave 1624 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3304 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.cmos.pio 36 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.ide.pio 6496 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.ide-pciconf 88 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.keyboard.pio 732 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.pic1.pio 90 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.pic2.pio 42 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.speaker.pio 938970 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.io_apic.pio 1000 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.i_dont_exist.pio 90 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.com_1.pio 15614 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.cpu0.interrupts.pio 748796 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.pciconfig.pio 2126 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::total 1714112 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.cmos.pio 16 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.ide.pio 4730 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.ide-pciconf 92 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.keyboard.pio 632 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.pic1.pio 4 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.pic2.pio 12 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.pit.pio 31770 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.io_apic.pio 328 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.i_dont_exist.pio 31858 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.com_1.pio 10796 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.cpu1.interrupts.pio 5100 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::total 85390 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.cpu0.interrupts.int_master::system.cpu1.interrupts.int_slave 330 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.cpu0.interrupts.int_master::total 330 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.cpu1.interrupts.int_master::system.cpu0.interrupts.int_slave 196 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.cpu1.interrupts.int_master::total 196 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count::system.physmem.port 95114 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count::system.pc.south_bridge.cmos.pio 52 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count::system.pc.south_bridge.ide.pio 11226 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count::system.pc.south_bridge.pic1.pio 94 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count::system.pc.south_bridge.pit.pio 31800 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count::system.pc.south_bridge.speaker.pio 938970 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count::system.pc.south_bridge.io_apic.pio 1328 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count::system.pc.i_dont_exist.pio 31948 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count::system.pc.com_1.pio 26410 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count::system.cpu0.interrupts.pio 748796 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count::system.cpu0.interrupts.int_slave 1876 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count::system.cpu1.interrupts.pio 5100 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count::system.cpu1.interrupts.int_slave 1954 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count::system.pc.pciconfig.pio 2126 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count::total 1898446 # Packet count per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.physmem.port 3026344 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3026344 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.cpu0.interrupts.int_slave 3360 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.cpu1.interrupts.int_slave 3248 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6608 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.ide.pio 3698 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.ide-pciconf 149 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.keyboard.pio 366 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.pic1.pio 45 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.pic2.pio 21 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.speaker.pio 469485 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.io_apic.pio 2000 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.i_dont_exist.pio 45 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.com_1.pio 7807 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.cpu0.interrupts.pio 1497586 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.pciconfig.pio 4252 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::total 1985488 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.cmos.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.ide.pio 3066 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.ide-pciconf 72 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.keyboard.pio 316 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.pic1.pio 2 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.pic2.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.pit.pio 15885 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.io_apic.pio 656 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.i_dont_exist.pio 15929 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.com_1.pio 5398 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.cpu1.interrupts.pio 10197 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::total 51561 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.cpu0.interrupts.int_master::system.cpu1.interrupts.int_slave 660 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.cpu0.interrupts.int_master::total 660 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.cpu1.interrupts.int_master::system.cpu0.interrupts.int_slave 392 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.cpu1.interrupts.int_master::total 392 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size::system.physmem.port 3026344 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size::system.pc.south_bridge.cmos.pio 26 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size::system.pc.south_bridge.ide.pio 6764 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size::system.pc.south_bridge.pic1.pio 47 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size::system.pc.south_bridge.pit.pio 15900 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size::system.pc.south_bridge.speaker.pio 469485 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size::system.pc.south_bridge.io_apic.pio 2656 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size::system.pc.i_dont_exist.pio 15974 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size::system.pc.com_1.pio 13205 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size::system.cpu0.interrupts.pio 1497586 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size::system.cpu0.interrupts.int_slave 3752 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size::system.cpu1.interrupts.pio 10197 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size::system.cpu1.interrupts.int_slave 3908 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size::system.pc.pciconfig.pio 4252 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size::total 5071053 # Cumulative packet size per connected master and slave (bytes) +system.piobus.data_through_bus 5071053 # Total data (bytes) +system.piobus.reqLayer0.occupancy 421750668 # Layer occupancy (ticks) +system.piobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.piobus.reqLayer1.occupancy 46000 # Layer occupancy (ticks) +system.piobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.piobus.reqLayer2.occupancy 6500 # Layer occupancy (ticks) +system.piobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.piobus.reqLayer3.occupancy 10348000 # Layer occupancy (ticks) +system.piobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.piobus.reqLayer4.occupancy 140500 # Layer occupancy (ticks) +system.piobus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.piobus.reqLayer5.occupancy 1063000 # Layer occupancy (ticks) +system.piobus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.piobus.reqLayer6.occupancy 95500 # Layer occupancy (ticks) +system.piobus.reqLayer6.utilization 0.0 # Layer utilization (%) +system.piobus.reqLayer7.occupancy 56000 # Layer occupancy (ticks) +system.piobus.reqLayer7.utilization 0.0 # Layer utilization (%) +system.piobus.reqLayer8.occupancy 21210500 # Layer occupancy (ticks) +system.piobus.reqLayer8.utilization 0.0 # Layer utilization (%) +system.piobus.reqLayer9.occupancy 586857500 # Layer occupancy (ticks) +system.piobus.reqLayer9.utilization 0.0 # Layer utilization (%) +system.piobus.reqLayer10.occupancy 1290500 # Layer occupancy (ticks) +system.piobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.piobus.reqLayer11.occupancy 39914000 # Layer occupancy (ticks) +system.piobus.reqLayer11.utilization 0.0 # Layer utilization (%) +system.piobus.reqLayer12.occupancy 2500 # Layer occupancy (ticks) +system.piobus.reqLayer12.utilization 0.0 # Layer utilization (%) +system.piobus.reqLayer13.occupancy 23057500 # Layer occupancy (ticks) +system.piobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.piobus.reqLayer14.occupancy 10500 # Layer occupancy (ticks) +system.piobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.piobus.reqLayer15.occupancy 10500 # Layer occupancy (ticks) +system.piobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.piobus.reqLayer16.occupancy 10500 # Layer occupancy (ticks) +system.piobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.piobus.reqLayer17.occupancy 12000 # Layer occupancy (ticks) +system.piobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.piobus.reqLayer18.occupancy 470748000 # Layer occupancy (ticks) +system.piobus.reqLayer18.utilization 0.0 # Layer utilization (%) +system.piobus.reqLayer19.occupancy 2244320 # Layer occupancy (ticks) +system.piobus.reqLayer19.utilization 0.0 # Layer utilization (%) +system.piobus.reqLayer20.occupancy 5358000 # Layer occupancy (ticks) +system.piobus.reqLayer20.utilization 0.0 # Layer utilization (%) +system.piobus.reqLayer21.occupancy 2333580 # Layer occupancy (ticks) +system.piobus.reqLayer21.utilization 0.0 # Layer utilization (%) +system.piobus.reqLayer22.occupancy 1074500 # Layer occupancy (ticks) +system.piobus.reqLayer22.utilization 0.0 # Layer utilization (%) +system.piobus.respLayer0.occupancy 52258179 # Layer occupancy (ticks) +system.piobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.piobus.respLayer1.occupancy 2331400 # Layer occupancy (ticks) +system.piobus.respLayer1.utilization 0.0 # Layer utilization (%) +system.piobus.respLayer2.occupancy 1919239500 # Layer occupancy (ticks) +system.piobus.respLayer2.utilization 0.0 # Layer utilization (%) +system.piobus.respLayer3.occupancy 68175500 # Layer occupancy (ticks) +system.piobus.respLayer3.utilization 0.0 # Layer utilization (%) +system.piobus.respLayer4.occupancy 210500 # Layer occupancy (ticks) +system.piobus.respLayer4.utilization 0.0 # Layer utilization (%) +system.piobus.respLayer5.occupancy 121000 # Layer occupancy (ticks) +system.piobus.respLayer5.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 32768 # Number of bytes transfered via DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_txs 30 # Number of DMA read transactions (not PRD). @@ -227,12 +466,12 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.ruby.l1_cntrl0.L1Dcache.demand_hits 11503621 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 550662 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 12054283 # Number of cache demand accesses -system.ruby.l1_cntrl0.L1Icache.demand_hits 70015833 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Icache.demand_misses 352190 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Icache.demand_accesses 70368023 # Number of cache demand accesses +system.ruby.l1_cntrl0.L1Dcache.demand_hits 11506236 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Dcache.demand_misses 550740 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Dcache.demand_accesses 12056976 # Number of cache demand accesses +system.ruby.l1_cntrl0.L1Icache.demand_hits 70023521 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Icache.demand_misses 352402 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Icache.demand_accesses 70375923 # Number of cache demand accesses system.ruby.l1_cntrl0.prefetcher.miss_observed 0 # number of misses observed system.ruby.l1_cntrl0.prefetcher.allocated_streams 0 # number of streams allocated for prefetching system.ruby.l1_cntrl0.prefetcher.prefetches_requested 0 # number of prefetch requests made @@ -242,12 +481,12 @@ system.ruby.l1_cntrl0.prefetcher.hits 0 # nu system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.l1_cntrl1.L1Dcache.demand_hits 12163827 # Number of cache demand hits -system.ruby.l1_cntrl1.L1Dcache.demand_misses 1291679 # Number of cache demand misses -system.ruby.l1_cntrl1.L1Dcache.demand_accesses 13455506 # Number of cache demand accesses -system.ruby.l1_cntrl1.L1Icache.demand_hits 55549058 # Number of cache demand hits -system.ruby.l1_cntrl1.L1Icache.demand_misses 459847 # Number of cache demand misses -system.ruby.l1_cntrl1.L1Icache.demand_accesses 56008905 # Number of cache demand accesses +system.ruby.l1_cntrl1.L1Dcache.demand_hits 12162992 # Number of cache demand hits +system.ruby.l1_cntrl1.L1Dcache.demand_misses 1291757 # Number of cache demand misses +system.ruby.l1_cntrl1.L1Dcache.demand_accesses 13454749 # Number of cache demand accesses +system.ruby.l1_cntrl1.L1Icache.demand_hits 55546818 # Number of cache demand hits +system.ruby.l1_cntrl1.L1Icache.demand_misses 459867 # Number of cache demand misses +system.ruby.l1_cntrl1.L1Icache.demand_accesses 56006685 # Number of cache demand accesses system.ruby.l1_cntrl1.prefetcher.miss_observed 0 # number of misses observed system.ruby.l1_cntrl1.prefetcher.allocated_streams 0 # number of streams allocated for prefetching system.ruby.l1_cntrl1.prefetcher.prefetches_requested 0 # number of prefetch requests made @@ -257,55 +496,55 @@ system.ruby.l1_cntrl1.prefetcher.hits 0 # nu system.ruby.l1_cntrl1.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl1.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl1.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.l2_cntrl0.L2cache.demand_hits 2426575 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 227803 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 2654378 # Number of cache demand accesses -system.cpu0.numCycles 10410297758 # number of cpu cycles simulated +system.ruby.l2_cntrl0.L2cache.demand_hits 2426890 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 227876 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 2654766 # Number of cache demand accesses +system.cpu0.numCycles 10410298653 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 60288276 # Number of instructions committed -system.cpu0.committedOps 115773079 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 108731496 # Number of integer alu accesses +system.cpu0.committedInsts 60294243 # Number of instructions committed +system.cpu0.committedOps 115784968 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 108743289 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 1065656 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 10277696 # number of instructions that are conditional controls -system.cpu0.num_int_insts 108731496 # number of integer instructions +system.cpu0.num_func_calls 1066196 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 10278204 # number of instructions that are conditional controls +system.cpu0.num_int_insts 108743289 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 267473663 # number of times the integer registers were read -system.cpu0.num_int_register_writes 137108635 # number of times the integer registers were written +system.cpu0.num_int_register_reads 267504308 # number of times the integer registers were read +system.cpu0.num_int_register_writes 137121782 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_mem_refs 12880520 # number of memory refs -system.cpu0.num_load_insts 7843945 # Number of load instructions -system.cpu0.num_store_insts 5036575 # Number of store instructions -system.cpu0.num_idle_cycles 9879714305.974102 # Number of idle cycles -system.cpu0.num_busy_cycles 530583452.025898 # Number of busy cycles -system.cpu0.not_idle_fraction 0.050967 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.949033 # Percentage of idle cycles +system.cpu0.num_mem_refs 12883291 # number of memory refs +system.cpu0.num_load_insts 7845612 # Number of load instructions +system.cpu0.num_store_insts 5037679 # Number of store instructions +system.cpu0.num_idle_cycles 9879654975.894102 # Number of idle cycles +system.cpu0.num_busy_cycles 530643677.105898 # Number of busy cycles +system.cpu0.not_idle_fraction 0.050973 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.949027 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.numCycles 10407399002 # number of cpu cycles simulated +system.cpu1.numCycles 10407399919 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 46383066 # Number of instructions committed -system.cpu1.committedOps 88725672 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 85218419 # Number of integer alu accesses +system.cpu1.committedInsts 46380985 # Number of instructions committed +system.cpu1.committedOps 88720452 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 85213748 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 1670749 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 7955161 # number of instructions that are conditional controls -system.cpu1.num_int_insts 85218419 # number of integer instructions +system.cpu1.num_func_calls 1670555 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 7954622 # number of instructions that are conditional controls +system.cpu1.num_int_insts 85213748 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 213998429 # number of times the integer registers were read -system.cpu1.num_int_register_writes 102139748 # number of times the integer registers were written +system.cpu1.num_int_register_reads 213988355 # number of times the integer registers were read +system.cpu1.num_int_register_writes 102135039 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_mem_refs 13480502 # number of memory refs -system.cpu1.num_load_insts 8673583 # Number of load instructions -system.cpu1.num_store_insts 4806919 # Number of store instructions -system.cpu1.num_idle_cycles 10081113907.619320 # Number of idle cycles -system.cpu1.num_busy_cycles 326285094.380681 # Number of busy cycles -system.cpu1.not_idle_fraction 0.031351 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.968649 # Percentage of idle cycles +system.cpu1.num_mem_refs 13479662 # number of memory refs +system.cpu1.num_load_insts 8672840 # Number of load instructions +system.cpu1.num_store_insts 4806822 # Number of store instructions +system.cpu1.num_idle_cycles 10081140022.903200 # Number of idle cycles +system.cpu1.num_busy_cycles 326259896.096799 # Number of busy cycles +system.cpu1.not_idle_fraction 0.031349 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.968651 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt index a3f0789f4..88911e3ab 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt @@ -1,150 +1,150 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.139557 # Number of seconds simulated -sim_ticks 5139557121500 # Number of ticks simulated -final_tick 5139557121500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.143601 # Number of seconds simulated +sim_ticks 5143601047500 # Number of ticks simulated +final_tick 5143601047500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 183644 # Simulator instruction rate (inst/s) -host_op_rate 364835 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3871369364 # Simulator tick rate (ticks/s) -host_mem_usage 967408 # Number of bytes of host memory used -host_seconds 1327.58 # Real time elapsed on the host -sim_insts 243802016 # Number of instructions simulated -sim_ops 484348047 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2455296 # Number of bytes read from this memory +host_inst_rate 337830 # Simulator instruction rate (inst/s) +host_op_rate 671266 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7140786618 # Simulator tick rate (ticks/s) +host_mem_usage 909440 # Number of bytes of host memory used +host_seconds 720.31 # Real time elapsed on the host +sim_insts 243343656 # Number of instructions simulated +sim_ops 483521256 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2435392 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 466944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5828928 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 127616 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1842944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 1536 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 356032 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2734144 # Number of bytes read from this memory -system.physmem.bytes_read::total 13813760 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 466944 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 127616 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 356032 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 950592 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9154048 # Number of bytes written to this memory -system.physmem.bytes_written::total 9154048 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 38364 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu0.inst 488448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 6105280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 134592 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1637632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 1280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 319296 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2611264 # Number of bytes read from this memory +system.physmem.bytes_read::total 13733504 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 488448 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 134592 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 319296 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 942336 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9060160 # Number of bytes written to this memory +system.physmem.bytes_written::total 9060160 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 38053 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 7296 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 91077 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1994 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 28796 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 24 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 5563 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 42721 # Number of read requests responded to by this memory -system.physmem.num_reads::total 215840 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 143032 # Number of write requests responded to by this memory -system.physmem.num_writes::total 143032 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 477725 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu0.inst 7632 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 95395 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2103 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 25588 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 20 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 4989 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 40801 # Number of read requests responded to by this memory +system.physmem.num_reads::total 214586 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 141565 # Number of write requests responded to by this memory +system.physmem.num_writes::total 141565 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 473480 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 90853 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1134130 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 24830 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 358580 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 299 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 69273 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 531980 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2687734 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 90853 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 24830 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 69273 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 184956 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1781097 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1781097 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1781097 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 477725 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 94962 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1186966 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 26167 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 318382 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 249 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 62076 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 507672 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2670017 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 94962 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 26167 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 62076 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 183205 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1761443 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1761443 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1761443 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 473480 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 90853 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1134130 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 24830 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 358580 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 299 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 69273 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 531980 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4468830 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 99105 # Total number of read requests seen -system.physmem.writeReqs 78746 # Total number of write requests seen -system.physmem.cpureqs 178569 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 6342720 # Total number of bytes read from memory -system.physmem.bytesWritten 5039744 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 6342720 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 5039744 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 11 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 712 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 6100 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 5671 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 5539 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 6946 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 5876 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 5654 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 5883 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 7012 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 6334 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 6064 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 5868 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 7100 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 5762 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 5656 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 6255 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 7374 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 4754 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 4366 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 4230 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 5859 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 4494 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 4387 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 4605 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 5921 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 5001 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 4809 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 4668 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 5984 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 4422 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 4352 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 4757 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 6137 # Track writes on a per bank basis +system.physmem.bw_total::cpu0.inst 94962 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1186966 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 26167 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 318382 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 249 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 62076 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 507672 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4431460 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 90446 # Total number of read requests seen +system.physmem.writeReqs 70433 # Total number of write requests seen +system.physmem.cpureqs 161351 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 5788544 # Total number of bytes read from memory +system.physmem.bytesWritten 4507712 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 5788544 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 4507712 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 26 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 472 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 5853 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 5374 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 5163 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 5410 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 5863 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 6188 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 5951 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 6069 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 4925 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 4669 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 5184 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 5694 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 5956 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 5914 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 6273 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 5934 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 4493 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 4309 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 4025 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 4097 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 4752 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 4893 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 4726 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 4839 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 3464 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 3572 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 4023 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 4337 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 4609 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 4582 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 5213 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 4499 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 6 # Number of times wr buffer was full causing retry -system.physmem.totGap 5135869541000 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 5140092000000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 99105 # Categorize read packet sizes +system.physmem.readPktSize::6 90446 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 78746 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 75637 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 7751 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 3409 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1725 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1554 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1226 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 983 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 957 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 916 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 876 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 581 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 527 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 479 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 448 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 405 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 409 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 465 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 448 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 189 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 97 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 12 # What read queue length does an incoming req see +system.physmem.writePktSize::6 70433 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 70577 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 8282 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 3161 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1284 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1096 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 890 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 563 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 524 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 494 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 461 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 417 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 407 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 373 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 391 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 408 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 405 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 308 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 227 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 98 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 52 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -156,304 +156,522 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2865 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3038 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3360 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3392 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3411 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3426 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3425 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3425 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3422 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 3426 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 3424 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 3421 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 3419 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 3417 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 3415 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3414 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3412 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3407 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3405 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3404 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3403 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3402 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 3400 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 594 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 412 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7 # What write queue length does an incoming req see -system.physmem.totQLat 2229520000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 4250910000 # Sum of mem lat for all requests -system.physmem.totBusLat 495470000 # Total cycles spent in databus access -system.physmem.totBankLat 1525920000 # Total cycles spent in bank access -system.physmem.avgQLat 22499.04 # Average queueing delay per request -system.physmem.avgBankLat 15398.71 # Average bank access latency per request +system.physmem.wrQLenPdf::0 2678 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2775 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3060 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3074 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3071 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3068 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3068 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3066 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 3065 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 3063 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 3061 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 3060 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 3059 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 3059 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 3058 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3054 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3052 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3051 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3040 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 3035 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 439 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 30233 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 340.294645 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 151.805560 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1124.042449 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 13536 44.77% 44.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 4627 15.30% 60.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 2854 9.44% 69.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 1864 6.17% 75.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 1230 4.07% 79.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 1007 3.33% 83.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 772 2.55% 85.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 598 1.98% 87.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 458 1.51% 89.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 438 1.45% 90.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 281 0.93% 91.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 279 0.92% 92.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 209 0.69% 93.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 207 0.68% 93.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 177 0.59% 94.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 236 0.78% 95.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 132 0.44% 95.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 98 0.32% 95.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 103 0.34% 96.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 81 0.27% 96.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 87 0.29% 96.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 80 0.26% 97.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 236 0.78% 97.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 88 0.29% 98.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 47 0.16% 98.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 40 0.13% 98.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 31 0.10% 98.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 30 0.10% 98.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 19 0.06% 98.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 16 0.05% 98.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 8 0.03% 98.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 13 0.04% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 5 0.02% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 8 0.03% 98.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2243 4 0.01% 98.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 5 0.02% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2371 9 0.03% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 4 0.01% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 3 0.01% 98.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2563 4 0.01% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 2 0.01% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 4 0.01% 99.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2755 4 0.01% 99.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 2 0.01% 99.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 4 0.01% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2947 4 0.01% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3011 2 0.01% 99.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 5 0.02% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3139 1 0.00% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3203 2 0.01% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3267 2 0.01% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3331 2 0.01% 99.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3395 5 0.02% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3459 7 0.02% 99.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3523 2 0.01% 99.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3587 3 0.01% 99.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3715 1 0.00% 99.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3779 6 0.02% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3843 2 0.01% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3907 1 0.00% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3971 2 0.01% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4099 12 0.04% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4163 1 0.00% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4227 1 0.00% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4291 2 0.01% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4355 1 0.00% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4483 1 0.00% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4611 2 0.01% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4867 1 0.00% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5059 3 0.01% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5123 2 0.01% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5251 1 0.00% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5379 1 0.00% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5443 1 0.00% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5507 1 0.00% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5571 1 0.00% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5699 1 0.00% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5763 1 0.00% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5827 1 0.00% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5891 1 0.00% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6083 1 0.00% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6147 3 0.01% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6339 1 0.00% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6403 1 0.00% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6595 2 0.01% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6659 1 0.00% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6723 4 0.01% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6787 1 0.00% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6851 4 0.01% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6915 2 0.01% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6979 1 0.00% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7107 1 0.00% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7235 1 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7491 2 0.01% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7555 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7811 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7939 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8003 1 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8067 2 0.01% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8195 29 0.10% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8384-8387 2 0.01% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8576-8579 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8707 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8768-8771 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9088-9091 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9280-9283 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9536-9539 3 0.01% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9664-9667 1 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9731 1 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9792-9795 1 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9920-9923 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9987 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10112-10115 2 0.01% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10176-10179 1 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10499 1 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10624-10627 2 0.01% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10755 1 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10816-10819 1 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10880-10883 1 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11072-11075 1 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11136-11139 2 0.01% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11456-11459 2 0.01% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12160-12163 1 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12224-12227 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12352-12355 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12608-12611 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13120-13123 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14083 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14595 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14656-14659 2 0.01% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14720-14723 1 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14851 1 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14915 15 0.05% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14979 11 0.04% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15040-15043 7 0.02% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15107 2 0.01% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15171 6 0.02% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15296-15299 3 0.01% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 3 0.01% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15488-15491 4 0.01% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15552-15555 4 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15619 2 0.01% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15744-15747 2 0.01% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15808-15811 3 0.01% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15875 5 0.02% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15936-15939 1 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16000-16003 1 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16064-16067 2 0.01% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16131 5 0.02% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16192-16195 2 0.01% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16256-16259 3 0.01% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16320-16323 1 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16387 21 0.07% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16448-16451 3 0.01% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16768-16771 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17024-17027 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 30233 # Bytes accessed per row activation +system.physmem.totQLat 1718746250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 3502520000 # Sum of mem lat for all requests +system.physmem.totBusLat 452100000 # Total cycles spent in databus access +system.physmem.totBankLat 1331673750 # Total cycles spent in bank access +system.physmem.avgQLat 19008.47 # Average queueing delay per request +system.physmem.avgBankLat 14727.65 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 42897.75 # Average memory access latency -system.physmem.avgRdBW 1.23 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.98 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1.23 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.98 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 38736.12 # Average memory access latency +system.physmem.avgRdBW 1.13 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.88 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 1.13 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.88 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 0.10 # Average write queue length over time -system.physmem.readRowHits 83478 # Number of row buffer hits during reads -system.physmem.writeRowHits 56534 # Number of row buffer hits during writes -system.physmem.readRowHitRate 84.24 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 71.79 # Row buffer hit rate for writes -system.physmem.avgGap 28877372.30 # Average gap between requests -system.l2c.replacements 104936 # number of replacements -system.l2c.tagsinuse 64827.217537 # Cycle average of tags in use -system.l2c.total_refs 3630977 # Total number of references to valid blocks. -system.l2c.sampled_refs 168979 # Sample count of references to valid blocks. -system.l2c.avg_refs 21.487741 # Average number of references to valid blocks. +system.physmem.avgWrQLen 0.11 # Average write queue length over time +system.physmem.readRowHits 78857 # Number of row buffer hits during reads +system.physmem.writeRowHits 51763 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.21 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.49 # Row buffer hit rate for writes +system.physmem.avgGap 31950049.42 # Average gap between requests +system.membus.throughput 6398386 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 425816 # Transaction distribution +system.membus.trans_dist::ReadResp 425816 # Transaction distribution +system.membus.trans_dist::WriteReq 5631 # Transaction distribution +system.membus.trans_dist::WriteResp 5631 # Transaction distribution +system.membus.trans_dist::Writeback 70433 # Transaction distribution +system.membus.trans_dist::UpgradeReq 476 # Transaction distribution +system.membus.trans_dist::UpgradeResp 476 # Transaction distribution +system.membus.trans_dist::ReadExReq 69519 # Transaction distribution +system.membus.trans_dist::ReadExResp 69519 # Transaction distribution +system.membus.trans_dist::MessageReq 269 # Transaction distribution +system.membus.trans_dist::MessageResp 269 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 538 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 538 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 197349 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 312424 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 498122 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1007895 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 60171 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 60171 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 257520 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.bridge.slave 312424 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.cpu0.interrupts.pio 498122 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.cpu0.interrupts.int_slave 538 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1068604 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 1076 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::total 1076 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 7851072 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 159641 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 996241 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 9006954 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2445184 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 2445184 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 10296256 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.bridge.slave 159641 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.cpu0.interrupts.pio 996241 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.cpu0.interrupts.int_slave 1076 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 11453214 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 32574935 # Total data (bytes) +system.membus.snoop_data_through_bus 335808 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 770602000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 164025500 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 314786000 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer3.occupancy 538000 # Layer occupancy (ticks) +system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.membus.respLayer0.occupancy 269000 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 1575668988 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer4.occupancy 198012000 # Layer occupancy (ticks) +system.membus.respLayer4.utilization 0.0 # Layer utilization (%) +system.l2c.replacements 103562 # number of replacements +system.l2c.tagsinuse 64796.800964 # Cycle average of tags in use +system.l2c.total_refs 3619781 # Total number of references to valid blocks. +system.l2c.sampled_refs 167743 # Sample count of references to valid blocks. +system.l2c.avg_refs 21.579327 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 50639.454481 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.125451 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 1092.997242 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 4517.674660 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 223.356063 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 1300.523613 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.dtb.walker 6.306120 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.inst 1891.819622 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.data 5154.960284 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.772697 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 51276.359665 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 0.126176 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 1273.083994 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 4560.482374 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 265.925814 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 1312.167499 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.dtb.walker 5.741812 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.inst 1370.746219 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.data 4732.167410 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.782415 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.016678 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.068934 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.003408 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.019844 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.dtb.walker 0.000096 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.inst 0.028867 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.data 0.078658 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.989185 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 20688 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 11397 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 368018 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 524840 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 3790 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1830 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 151783 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 229669 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 45217 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 8673 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 312711 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 544544 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2223160 # number of ReadReq hits +system.l2c.occ_percent::cpu0.inst 0.019426 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.069587 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.004058 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.020022 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.dtb.walker 0.000088 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.inst 0.020916 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.data 0.072207 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.988721 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 21527 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 11247 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 380736 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 540863 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 5306 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 2771 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 154822 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 225347 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 39624 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 7543 # 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number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 4768622840 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4768622840 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 910 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 910 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47626 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47626 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47626 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47626 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47630 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47630 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47630 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47630 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -626,56 +844,56 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 23953.637969 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 23953.637969 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 112590.537329 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 112590.537329 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 110904.377861 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 110904.377861 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 110904.377861 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 110904.377861 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 67344 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 145447.587912 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 145447.587912 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 99235.135595 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 99235.135595 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 100118.052488 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 100118.052488 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 100118.052488 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 100118.052488 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 62980 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 6552 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 5996 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.278388 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.503669 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 169 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 169 # number of ReadReq MSHR misses -system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 24864 # number of WriteReq MSHR misses -system.iocache.WriteReq_mshr_misses::total 24864 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 25033 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 25033 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 25033 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 25033 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 12912498 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12912498 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 3966572850 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 3966572850 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 3979485348 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 3979485348 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 3979485348 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 3979485348 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.186534 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.186534 # mshr miss rate for ReadReq accesses -system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 0.532192 # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::total 0.532192 # mshr miss rate for WriteReq accesses -system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.525616 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.525616 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.525616 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.525616 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 76405.313609 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 76405.313609 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 159530.761342 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 159530.761342 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 158969.574082 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 158969.574082 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 158969.574082 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 158969.574082 # average overall mshr miss latency +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 701 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 701 # number of ReadReq MSHR misses +system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 21264 # number of WriteReq MSHR misses +system.iocache.WriteReq_mshr_misses::total 21264 # number of WriteReq MSHR misses +system.iocache.demand_mshr_misses::pc.south_bridge.ide 21965 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 21965 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 21965 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 21965 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 95889055 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 95889055 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 3530226785 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 3530226785 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 3626115840 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 3626115840 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 3626115840 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 3626115840 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.770330 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.770330 # mshr miss rate for ReadReq accesses +system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 0.455137 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total 0.455137 # mshr miss rate for WriteReq accesses +system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.461159 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.461159 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.461159 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.461159 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 136788.951498 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 136788.951498 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 166018.942109 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 166018.942109 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 165086.084225 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 165086.084225 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 165086.084225 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 165086.084225 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -689,336 +907,488 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu0.numCycles 1838156995 # number of cpu cycles simulated +system.toL2Bus.throughput 52020310 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 1696057 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 1695532 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 5631 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 5631 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 870189 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 384 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 384 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 160044 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 138785 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 912543 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 3510594 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.port 23321 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port 95695 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count 4542153 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 29200384 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 115384682 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.port 82512 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.port 359600 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size 145027178 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 267476487 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 95232 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4838788408 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 814500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 2054232112 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 4517736918 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 13025458 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 50823334 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.throughput 1261125 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 151553 # Transaction distribution +system.iobus.trans_dist::ReadResp 151553 # Transaction distribution +system.iobus.trans_dist::WriteReq 26624 # Transaction distribution +system.iobus.trans_dist::WriteResp 26624 # Transaction distribution +system.iobus.trans_dist::MessageReq 269 # Transaction distribution +system.iobus.trans_dist::MessageResp 269 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 36 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 2 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 4120 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 2 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 26 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 18 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 290304 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 54 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 86 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 15696 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 4 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2048 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 312424 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 43930 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 43930 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 538 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 538 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.apicbridge.slave 538 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.south_bridge.cmos.pio 36 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.south_bridge.dma1.pio 2 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.south_bridge.ide.pio 4120 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.south_bridge.ide-pciconf 2 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.south_bridge.keyboard.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.south_bridge.pic1.pio 26 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.south_bridge.pic2.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.south_bridge.pit.pio 18 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.south_bridge.speaker.pio 290304 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.south_bridge.io_apic.pio 54 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.i_dont_exist.pio 86 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.com_1.pio 15696 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.fake_floppy.pio 4 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.iocache.cpu_side 43930 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.pciconfig.pio 2048 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 356892 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 1 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 2333 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 4 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 13 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 9 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 145152 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 108 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 43 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 7848 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 2 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4096 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 159641 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 1396968 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 1396968 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 1076 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 1076 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.apicbridge.slave 1076 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.south_bridge.dma1.pio 1 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.south_bridge.ide.pio 2333 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.south_bridge.ide-pciconf 4 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.south_bridge.keyboard.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.south_bridge.pic1.pio 13 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.south_bridge.pic2.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.south_bridge.pit.pio 9 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.south_bridge.speaker.pio 145152 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.south_bridge.io_apic.pio 108 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.i_dont_exist.pio 43 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.com_1.pio 7848 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.fake_floppy.pio 2 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.iocache.cpu_side 1396968 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.pciconfig.pio 4096 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 1557685 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 6486722 # Total data (bytes) +system.iobus.reqLayer0.occupancy 624016 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 28000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 2000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 3409000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) +system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer5.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer6.occupancy 24000 # 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Number of integer alu accesses +system.cpu0.committedInsts 74314462 # Number of instructions committed +system.cpu0.committedOps 150407349 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 138687072 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 1069041 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 14289344 # number of instructions that are conditional controls -system.cpu0.num_int_insts 136919559 # number of integer instructions +system.cpu0.num_func_calls 1088594 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 14472613 # number of instructions that are conditional controls +system.cpu0.num_int_insts 138687072 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 336929611 # number of times the integer registers were read -system.cpu0.num_int_register_writes 173945922 # number of times the integer registers were written +system.cpu0.num_int_register_reads 341744011 # number of times the integer registers were read +system.cpu0.num_int_register_writes 175930003 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_mem_refs 14717824 # number of memory refs -system.cpu0.num_load_insts 10660250 # Number of load instructions -system.cpu0.num_store_insts 4057574 # Number of store instructions -system.cpu0.num_idle_cycles 1090327710419.609375 # Number of idle cycles -system.cpu0.num_busy_cycles -1088489553424.609375 # Number of busy cycles -system.cpu0.not_idle_fraction -592.163540 # Percentage of non-idle cycles -system.cpu0.idle_fraction 593.163540 # Percentage of idle cycles +system.cpu0.num_mem_refs 15165282 # number of memory refs +system.cpu0.num_load_insts 10883561 # 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number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 38020458 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 2884963 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 130590962 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.004185 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.004045 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.116363 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.006622 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.004185 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.004045 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.116363 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.006622 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.004185 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.004045 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.116363 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.006622 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13717.337443 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14203.046097 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 7952.656857 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13717.337443 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14203.046097 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 7952.656857 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13717.337443 # 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miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.126748 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.038265 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.038803 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.035446 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.037518 # miss rate for WriteReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.067635 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.070573 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.142914 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.092055 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.067635 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.070573 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.142914 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.092055 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14241.890997 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16884.127041 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 10919.703444 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 34198.474579 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 32219.127659 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 15874.755714 # average WriteReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 18476.783023 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 18289.450774 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 11704.904021 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 18476.783023 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 18289.450774 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 11704.904021 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 179212 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 11859 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 11783 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 15.185597 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 15.209369 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 1544951 # number of writebacks -system.cpu0.dcache.writebacks::total 1544951 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 358302 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 358302 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 11322 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 11322 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 369624 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 369624 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 369624 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 369624 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 233721 # 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number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 10451842999 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 15061563999 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 31167993500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33212773000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 64380766500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 368756500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 730986500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1099743000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 31536750000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 33943759500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 65480509500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.095720 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.120441 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.059855 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.042784 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.031393 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018453 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.074628 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.087399 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.043778 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.074628 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.087399 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.043778 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11932.806637 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14625.649630 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13832.065698 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26315.178275 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 26401.324191 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 26362.920003 # average WriteReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 15218.020415 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16195.092434 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15882.984298 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 15218.020415 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16195.092434 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15882.984298 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 1541993 # number of writebacks +system.cpu0.dcache.writebacks::total 1541993 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 342834 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 342834 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 12370 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 12370 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 355204 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 355204 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 355204 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 355204 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 229498 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 546200 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 775698 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 61819 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 77322 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 139141 # number of WriteReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 291317 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 623522 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 914839 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 291317 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 623522 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 914839 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2809489500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 8130780549 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 10940270049 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1990477500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2600292531 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4590770031 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4799967000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 10731073080 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 15531040080 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 4799967000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 10731073080 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 15531040080 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 31033142000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33153511000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 64186653000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 465277000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 664192000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1129469000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 31498419000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 33817703000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 65316122000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.090541 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.126495 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.058734 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.038803 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.030557 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.016561 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.070573 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.091047 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.042337 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.070573 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.091047 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.042337 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12241.890997 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14886.086688 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14103.774986 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32198.474579 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 33629.400830 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32993.654142 # average WriteReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 16476.783023 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17210.416120 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16976.801470 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16476.783023 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17210.416120 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16976.801470 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1029,303 +1399,303 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 2606004355 # number of cpu cycles simulated +system.cpu1.numCycles 2608004713 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 34463532 # Number of instructions committed -system.cpu1.committedOps 67005357 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 62150402 # Number of integer alu accesses +system.cpu1.committedInsts 34942757 # Number of instructions committed +system.cpu1.committedOps 68016284 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 63114732 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 411236 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 6382216 # number of instructions that are conditional controls -system.cpu1.num_int_insts 62150402 # number of integer instructions +system.cpu1.num_func_calls 430753 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 6467325 # number of instructions that are conditional controls +system.cpu1.num_int_insts 63114732 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 149729485 # number of times the integer registers were read -system.cpu1.num_int_register_writes 79937808 # number of times the integer registers were written +system.cpu1.num_int_register_reads 152021040 # number of times the integer registers were read +system.cpu1.num_int_register_writes 81233840 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_mem_refs 4253944 # number of memory refs -system.cpu1.num_load_insts 2634755 # Number of load instructions -system.cpu1.num_store_insts 1619189 # Number of store instructions -system.cpu1.num_idle_cycles 7677367348.593150 # Number of idle cycles -system.cpu1.num_busy_cycles -5071362993.593150 # Number of busy cycles -system.cpu1.not_idle_fraction -1.946030 # Percentage of non-idle cycles -system.cpu1.idle_fraction 2.946030 # Percentage of idle cycles +system.cpu1.num_mem_refs 4322210 # number of memory refs +system.cpu1.num_load_insts 2726743 # Number of load instructions +system.cpu1.num_store_insts 1595467 # Number of store instructions +system.cpu1.num_idle_cycles 9296961839.327438 # Number of idle cycles +system.cpu1.num_busy_cycles -6688957126.327438 # Number of busy cycles +system.cpu1.not_idle_fraction -2.564780 # Percentage of non-idle cycles +system.cpu1.idle_fraction 3.564780 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 28657213 # Number of BP lookups -system.cpu2.branchPred.condPredicted 28657213 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 282528 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 26332341 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 25809696 # Number of BTB hits +system.cpu2.branchPred.lookups 28107723 # Number of BP lookups +system.cpu2.branchPred.condPredicted 28107723 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 253065 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 25890078 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 25466613 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 98.015197 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 509678 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 56598 # Number of incorrect RAS predictions. -system.cpu2.numCycles 152138342 # number of cpu cycles simulated +system.cpu2.branchPred.BTBHitPct 98.364373 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 482621 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 53231 # Number of incorrect RAS predictions. +system.cpu2.numCycles 150677905 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 8765036 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 141230370 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 28657213 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 26319374 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 54195726 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 1350224 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 59186 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.BlockedCycles 22546148 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 3184 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 6465 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 18223 # Number of stall cycles due to pending traps -system.cpu2.fetch.IcacheWaitRetryStallCycles 777 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 2884967 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 126552 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 1685 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 86648155 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 3.214672 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 3.414816 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 8157389 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 138649085 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 28107723 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 25949234 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 53330196 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 1190060 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 46897 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.BlockedCycles 22689996 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 1645 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 6110 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 10082 # Number of stall cycles due to pending traps +system.cpu2.fetch.IcacheWaitRetryStallCycles 361 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 2679696 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 114342 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 1368 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 85168083 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 3.213895 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 3.414010 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 32565830 37.58% 37.58% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 546380 0.63% 38.21% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 23846422 27.52% 65.74% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 287955 0.33% 66.07% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 558507 0.64% 66.71% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 803239 0.93% 67.64% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 320738 0.37% 68.01% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 484990 0.56% 68.57% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 27234094 31.43% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 31941663 37.50% 37.50% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 506826 0.60% 38.10% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 23646883 27.76% 65.86% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 259157 0.30% 66.17% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 526154 0.62% 66.79% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 751269 0.88% 67.67% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 273870 0.32% 67.99% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 459070 0.54% 68.53% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 26803191 31.47% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 86648155 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.188363 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.928302 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 10203383 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 21434341 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 42926723 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 1270829 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1056674 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 277800524 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 10 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 1056674 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 11171095 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 12732005 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 3756843 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 43068844 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 5106557 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 276894625 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 6426 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 2483944 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 1961652 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.FullRegisterEvents 2548 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 331033770 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 601753258 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 601753178 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 80 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 321557178 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 9476592 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 136008 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 137084 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 11206153 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 5917951 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3223233 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 365517 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 302609 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 275352384 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 397965 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 273886109 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 53996 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 6700477 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 10323870 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 50144 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 86648155 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 3.160899 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 2.377923 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 85168083 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.186542 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.920169 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 9520844 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 21607924 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 39424228 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 1229084 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 928772 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 273051293 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 4 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 928772 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 10439907 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 13089260 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 3699901 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 39570553 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 4982521 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 272244708 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 6270 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 2417106 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 1932594 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.FullRegisterEvents 1355 # Number of times there has been no free registers +system.cpu2.rename.RenamedOperands 325535285 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 590374943 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 590374855 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 88 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 317221539 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 8313746 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 122579 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 123510 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 10816950 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 5506267 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 2968253 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 324837 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 268098 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 270840712 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 382144 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 269680817 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 48233 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 5882884 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 8996381 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 45929 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 85168083 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 3.166454 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 2.381789 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 23779115 27.44% 27.44% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 5842995 6.74% 34.19% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 3792974 4.38% 38.56% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 2596888 3.00% 41.56% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 25119641 28.99% 70.55% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1266341 1.46% 72.01% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 23944050 27.63% 99.65% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 257275 0.30% 99.94% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 48876 0.06% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 23491447 27.58% 27.58% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 5639421 6.62% 34.20% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 3592727 4.22% 38.42% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 2433201 2.86% 41.28% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 24826332 29.15% 70.43% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1184872 1.39% 71.82% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 23718098 27.85% 99.67% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 237817 0.28% 99.95% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 44168 0.05% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 86648155 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 85168083 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 118795 33.06% 33.06% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 241 0.07% 33.13% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 86 0.02% 33.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 33.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 33.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 33.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 33.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 33.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 33.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 33.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 33.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 33.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 33.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 33.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 33.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 33.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 33.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 33.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 33.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 33.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 33.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 33.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 33.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 33.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 33.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 33.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 33.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 33.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 188736 52.53% 85.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 51440 14.32% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 103037 31.19% 31.19% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 241 0.07% 31.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 31.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 31.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 31.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 31.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 31.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 31.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 31.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 31.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 31.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 31.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 31.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 31.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 31.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 31.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 31.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 31.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 31.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 31.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 31.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 31.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 31.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 31.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 31.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 31.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 31.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 31.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 31.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 181800 55.03% 86.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 45300 13.71% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 68063 0.02% 0.02% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 264478225 96.57% 96.59% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 51078 0.02% 96.61% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 47173 0.02% 96.63% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.63% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.63% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.63% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.63% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.63% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.63% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 6223177 2.27% 98.90% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3018393 1.10% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 57001 0.02% 0.02% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 260895656 96.74% 96.76% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 47542 0.02% 96.78% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 43696 0.02% 96.80% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.80% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.80% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.80% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.80% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.80% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.80% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.80% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.80% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.80% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.80% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.80% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.80% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.80% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.80% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.80% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.80% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.80% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.80% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.80% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.80% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.80% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.80% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.80% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.80% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.80% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.80% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 5855050 2.17% 98.97% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 2781872 1.03% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 273886109 # Type of FU issued -system.cpu2.iq.rate 1.800244 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 359298 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001312 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 634870698 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 282454128 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 272600027 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 31 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 8 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 274177330 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 14 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 614321 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 269680817 # Type of FU issued +system.cpu2.iq.rate 1.789783 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 330378 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001225 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 624940807 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 277108342 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 268465757 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 40 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 38 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 14 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 269954173 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 21 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 584645 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 929558 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 6267 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 3704 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 478908 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 814531 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 6351 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 3024 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 433740 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 656133 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 10377 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 655738 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 10426 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1056674 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 8226180 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 803204 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 275750349 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 63685 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 5917951 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3223233 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 220549 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 623968 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 3956 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 3704 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 161931 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 157888 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 319819 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 273437676 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 6124763 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 448433 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 928772 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 8598252 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 798569 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 271222856 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 58264 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 5506267 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 2968253 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 206333 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 621407 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 3570 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 3024 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 146514 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 137704 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 284218 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 269282728 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 5768116 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 398089 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed system.cpu2.iew.exec_nop 0 # number of nop insts executed -system.cpu2.iew.exec_refs 9083662 # number of memory reference insts executed -system.cpu2.iew.exec_branches 27821550 # Number of branches executed -system.cpu2.iew.exec_stores 2958899 # Number of stores executed -system.cpu2.iew.exec_rate 1.797296 # Inst execution rate -system.cpu2.iew.wb_sent 273301697 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 272600035 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 212879972 # num instructions producing a value -system.cpu2.iew.wb_consumers 348297595 # num instructions consuming a value +system.cpu2.iew.exec_refs 8495654 # number of memory reference insts executed +system.cpu2.iew.exec_branches 27379135 # Number of branches executed +system.cpu2.iew.exec_stores 2727538 # Number of stores executed +system.cpu2.iew.exec_rate 1.787141 # Inst execution rate +system.cpu2.iew.wb_sent 269160909 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 268465771 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 209852405 # num instructions producing a value +system.cpu2.iew.wb_consumers 343221010 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.791790 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.611201 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.781720 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.611421 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 6973062 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 347821 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 284653 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 85591481 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 3.140222 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.867307 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 6125563 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 336215 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 254201 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 84239311 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 3.146959 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.869440 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 28429929 33.22% 33.22% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4148762 4.85% 38.06% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1193631 1.39% 39.46% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 24678313 28.83% 68.29% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 797871 0.93% 69.22% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 541346 0.63% 69.85% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 330295 0.39% 70.24% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 23445398 27.39% 97.63% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 2025936 2.37% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 28027655 33.27% 33.27% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 3948624 4.69% 37.96% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1090324 1.29% 39.25% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 24397189 28.96% 68.21% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 757994 0.90% 69.11% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 507340 0.60% 69.72% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 301970 0.36% 70.08% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 23269432 27.62% 97.70% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1938783 2.30% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 85591481 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 136077221 # Number of instructions committed -system.cpu2.commit.committedOps 268776221 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 84239311 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 134086437 # Number of instructions committed +system.cpu2.commit.committedOps 265097623 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 7732718 # Number of memory references committed -system.cpu2.commit.loads 4988393 # Number of loads committed -system.cpu2.commit.membars 163760 # Number of memory barriers committed -system.cpu2.commit.branches 27507890 # Number of branches committed +system.cpu2.commit.refs 7226249 # Number of memory references committed +system.cpu2.commit.loads 4691736 # Number of loads committed +system.cpu2.commit.membars 162513 # Number of memory barriers committed +system.cpu2.commit.branches 27101249 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 245262632 # Number of committed integer instructions. -system.cpu2.commit.function_calls 414873 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 2025936 # number cycles where commit BW limit reached +system.cpu2.commit.int_insts 241753447 # Number of committed integer instructions. +system.cpu2.commit.function_calls 394614 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 1938783 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 359289994 # The number of ROB reads -system.cpu2.rob.rob_writes 552558663 # The number of ROB writes -system.cpu2.timesIdled 454161 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 65490187 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 4914041775 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 136077221 # Number of Instructions Simulated -system.cpu2.committedOps 268776221 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 136077221 # Number of Instructions Simulated -system.cpu2.cpi 1.118029 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.118029 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.894431 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.894431 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 502349004 # number of integer regfile reads -system.cpu2.int_regfile_writes 325553024 # number of integer regfile writes -system.cpu2.fp_regfile_reads 62552 # number of floating regfile reads -system.cpu2.fp_regfile_writes 62544 # number of floating regfile writes -system.cpu2.misc_regfile_reads 88383748 # number of misc regfile reads -system.cpu2.misc_regfile_writes 121022 # number of misc regfile writes +system.cpu2.rob.rob_reads 353502675 # The number of ROB reads +system.cpu2.rob.rob_writes 543377618 # The number of ROB writes +system.cpu2.timesIdled 448607 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 65509822 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 4919608430 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 134086437 # Number of Instructions Simulated +system.cpu2.committedOps 265097623 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 134086437 # Number of Instructions Simulated +system.cpu2.cpi 1.123737 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.123737 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.889888 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.889888 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 494284042 # number of integer regfile reads +system.cpu2.int_regfile_writes 320739139 # number of integer regfile writes +system.cpu2.fp_regfile_reads 62606 # number of floating regfile reads +system.cpu2.fp_regfile_writes 62592 # number of floating regfile writes +system.cpu2.misc_regfile_reads 86692309 # number of misc regfile reads +system.cpu2.misc_regfile_writes 109016 # number of misc regfile writes system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt index 91425a88c..e69de29bb 100644 --- a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt +++ b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt @@ -1,419 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 2.233778 # Number of seconds simulated -sim_ticks 4467555024 # Number of ticks simulated -final_tick 4467555024 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 2000000000 # Frequency of simulated ticks -host_inst_rate 3081772 # Simulator instruction rate (inst/s) -host_op_rate 3082983 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6178737 # Simulator tick rate (ticks/s) -host_mem_usage 519228 # Number of bytes of host memory used -host_seconds 723.05 # Real time elapsed on the host -sim_insts 2228284650 # Number of instructions simulated -sim_ops 2229160714 # Number of ops (including micro ops) simulated -system.hypervisor_desc.bytes_read::cpu.data 16792 # Number of bytes read from this memory -system.hypervisor_desc.bytes_read::total 16792 # Number of bytes read from this memory -system.hypervisor_desc.num_reads::cpu.data 9024 # Number of read requests responded to by this memory -system.hypervisor_desc.num_reads::total 9024 # Number of read requests responded to by this memory -system.hypervisor_desc.bw_read::cpu.data 7517 # Total read bandwidth from this memory (bytes/s) -system.hypervisor_desc.bw_read::total 7517 # Total read bandwidth from this memory (bytes/s) -system.hypervisor_desc.bw_total::cpu.data 7517 # Total bandwidth to/from this memory (bytes/s) -system.hypervisor_desc.bw_total::total 7517 # Total bandwidth to/from this memory (bytes/s) -system.partition_desc.bytes_read::cpu.data 4846 # Number of bytes read from this memory -system.partition_desc.bytes_read::total 4846 # Number of bytes read from this memory -system.partition_desc.num_reads::cpu.data 608 # Number of read requests responded to by this memory -system.partition_desc.num_reads::total 608 # Number of read requests responded to by this memory -system.partition_desc.bw_read::cpu.data 2169 # Total read bandwidth from this memory (bytes/s) -system.partition_desc.bw_read::total 2169 # Total read bandwidth from this memory (bytes/s) -system.partition_desc.bw_total::cpu.data 2169 # Total bandwidth to/from this memory (bytes/s) -system.partition_desc.bw_total::total 2169 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytes_read::cpu.inst 612291324 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 97534024 # Number of bytes read from this memory -system.physmem.bytes_read::total 709825348 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 612291324 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 612291324 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 15400223 # Number of bytes written to this memory -system.physmem.bytes_written::total 15400223 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 153072831 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 12152054 # Number of read requests responded to by this memory -system.physmem.num_reads::total 165224885 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 1927067 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1927067 # Number of write requests responded to by this memory -system.physmem.num_other::cpu.data 14 # Number of other requests responded to by this memory -system.physmem.num_other::total 14 # Number of other requests responded to by this memory -system.physmem.bw_read::cpu.inst 274105779 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 43663267 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 317769046 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 274105779 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 274105779 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 6894251 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6894251 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 274105779 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 50557518 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 324663297 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 0 # Total number of read requests seen -system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 0 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 0 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 0 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 0 # Sum of mem lat for all requests -system.physmem.totBusLat 0 # Total cycles spent in databus access -system.physmem.totBankLat 0 # Total cycles spent in bank access -system.physmem.avgQLat nan # Average queueing delay per request -system.physmem.avgBankLat nan # Average bank access latency per request -system.physmem.avgBusLat nan # Average bus latency per request -system.physmem.avgMemAccLat nan # Average memory access latency -system.physmem.avgRdBW 0.00 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.00 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 0 # Number of row buffer hits during reads -system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate nan # Row buffer hit rate for reads -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap nan # Average gap between requests -system.rom.bytes_read::cpu.inst 432296 # Number of bytes read from this memory -system.rom.bytes_read::cpu.data 696392 # Number of bytes read from this memory -system.rom.bytes_read::total 1128688 # Number of bytes read from this memory -system.rom.bytes_inst_read::cpu.inst 432296 # Number of instructions bytes read from this memory -system.rom.bytes_inst_read::total 432296 # Number of instructions bytes read from this memory -system.rom.num_reads::cpu.inst 108074 # Number of read requests responded to by this memory -system.rom.num_reads::cpu.data 87049 # Number of read requests responded to by this memory -system.rom.num_reads::total 195123 # Number of read requests responded to by this memory -system.rom.bw_read::cpu.inst 193527 # Total read bandwidth from this memory (bytes/s) -system.rom.bw_read::cpu.data 311755 # Total read bandwidth from this memory (bytes/s) -system.rom.bw_read::total 505282 # Total read bandwidth from this memory (bytes/s) -system.rom.bw_inst_read::cpu.inst 193527 # Instruction read bandwidth from this memory (bytes/s) -system.rom.bw_inst_read::total 193527 # Instruction read bandwidth from this memory (bytes/s) -system.rom.bw_total::cpu.inst 193527 # Total bandwidth to/from this memory (bytes/s) -system.rom.bw_total::cpu.data 311755 # Total bandwidth to/from this memory (bytes/s) -system.rom.bw_total::total 505282 # Total bandwidth to/from this memory (bytes/s) -system.physmem2.bytes_read::cpu.inst 8318106840 # Number of bytes read from this memory -system.physmem2.bytes_read::cpu.data 1495885127 # Number of bytes read from this memory -system.physmem2.bytes_read::total 9813991967 # Number of bytes read from this memory -system.physmem2.bytes_inst_read::cpu.inst 8318106840 # Number of instructions bytes read from this memory -system.physmem2.bytes_inst_read::total 8318106840 # Number of instructions bytes read from this memory -system.physmem2.bytes_written::cpu.data 897268422 # Number of bytes written to this memory -system.physmem2.bytes_written::total 897268422 # Number of bytes written to this memory -system.physmem2.num_reads::cpu.inst 2079526710 # Number of read requests responded to by this memory -system.physmem2.num_reads::cpu.data 323962420 # Number of read requests responded to by this memory -system.physmem2.num_reads::total 2403489130 # Number of read requests responded to by this memory -system.physmem2.num_writes::cpu.data 187387796 # Number of write requests responded to by this memory -system.physmem2.num_writes::total 187387796 # Number of write requests responded to by this memory -system.physmem2.num_other::cpu.data 5403067 # Number of other requests responded to by this memory -system.physmem2.num_other::total 5403067 # Number of other requests responded to by this memory -system.physmem2.bw_read::cpu.inst 3723784842 # Total read bandwidth from this memory (bytes/s) -system.physmem2.bw_read::cpu.data 669666123 # Total read bandwidth from this memory (bytes/s) -system.physmem2.bw_read::total 4393450966 # Total read bandwidth from this memory (bytes/s) -system.physmem2.bw_inst_read::cpu.inst 3723784842 # Instruction read bandwidth from this memory (bytes/s) -system.physmem2.bw_inst_read::total 3723784842 # Instruction read bandwidth from this memory (bytes/s) -system.physmem2.bw_write::cpu.data 401682091 # Write bandwidth from this memory (bytes/s) -system.physmem2.bw_write::total 401682091 # Write bandwidth from this memory (bytes/s) -system.physmem2.bw_total::cpu.inst 3723784842 # Total bandwidth to/from this memory (bytes/s) -system.physmem2.bw_total::cpu.data 1071348214 # Total bandwidth to/from this memory (bytes/s) -system.physmem2.bw_total::total 4795133057 # Total bandwidth to/from this memory (bytes/s) -system.physmem2.readReqs 0 # Total number of read requests seen -system.physmem2.writeReqs 0 # Total number of write requests seen -system.physmem2.cpureqs 0 # Reqs generatd by CPU via cache - shady -system.physmem2.bytesRead 0 # Total number of bytes read from memory -system.physmem2.bytesWritten 0 # Total number of bytes written to memory -system.physmem2.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize() -system.physmem2.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem2.servicedByWrQ 0 # Number of read reqs serviced by write Q -system.physmem2.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem2.perBankRdReqs::0 0 # Track reads on a per bank basis -system.physmem2.perBankRdReqs::1 0 # Track reads on a per bank basis -system.physmem2.perBankRdReqs::2 0 # Track reads on a per bank basis -system.physmem2.perBankRdReqs::3 0 # Track reads on a per bank basis -system.physmem2.perBankRdReqs::4 0 # Track reads on a per bank basis -system.physmem2.perBankRdReqs::5 0 # Track reads on a per bank basis -system.physmem2.perBankRdReqs::6 0 # Track reads on a per bank basis -system.physmem2.perBankRdReqs::7 0 # Track reads on a per bank basis -system.physmem2.perBankRdReqs::8 0 # Track reads on a per bank basis -system.physmem2.perBankRdReqs::9 0 # Track reads on a per bank basis -system.physmem2.perBankRdReqs::10 0 # Track reads on a per bank basis -system.physmem2.perBankRdReqs::11 0 # Track reads on a per bank basis -system.physmem2.perBankRdReqs::12 0 # Track reads on a per bank basis -system.physmem2.perBankRdReqs::13 0 # Track reads on a per bank basis -system.physmem2.perBankRdReqs::14 0 # Track reads on a per bank basis -system.physmem2.perBankRdReqs::15 0 # Track reads on a per bank basis -system.physmem2.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem2.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem2.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem2.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem2.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem2.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem2.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem2.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem2.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem2.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem2.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem2.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem2.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem2.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem2.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem2.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem2.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem2.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem2.totGap 0 # Total gap between requests -system.physmem2.readPktSize::0 0 # Categorize read packet sizes -system.physmem2.readPktSize::1 0 # Categorize read packet sizes -system.physmem2.readPktSize::2 0 # Categorize read packet sizes -system.physmem2.readPktSize::3 0 # Categorize read packet sizes -system.physmem2.readPktSize::4 0 # Categorize read packet sizes -system.physmem2.readPktSize::5 0 # Categorize read packet sizes -system.physmem2.readPktSize::6 0 # Categorize read packet sizes -system.physmem2.writePktSize::0 0 # Categorize write packet sizes -system.physmem2.writePktSize::1 0 # Categorize write packet sizes -system.physmem2.writePktSize::2 0 # Categorize write packet sizes -system.physmem2.writePktSize::3 0 # Categorize write packet sizes -system.physmem2.writePktSize::4 0 # Categorize write packet sizes -system.physmem2.writePktSize::5 0 # Categorize write packet sizes -system.physmem2.writePktSize::6 0 # Categorize write packet sizes -system.physmem2.rdQLenPdf::0 0 # What read queue length does an incoming req see -system.physmem2.rdQLenPdf::1 0 # What read queue length does an incoming req see -system.physmem2.rdQLenPdf::2 0 # What read queue length does an incoming req see -system.physmem2.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.physmem2.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.physmem2.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem2.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem2.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem2.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem2.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem2.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem2.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem2.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem2.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem2.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem2.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem2.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem2.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem2.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem2.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem2.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem2.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem2.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem2.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem2.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem2.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem2.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem2.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem2.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem2.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem2.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem2.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem2.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.physmem2.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.physmem2.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.physmem2.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.physmem2.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.physmem2.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.physmem2.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.physmem2.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.physmem2.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.physmem2.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.physmem2.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.physmem2.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.physmem2.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.physmem2.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.physmem2.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.physmem2.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.physmem2.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.physmem2.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.physmem2.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.physmem2.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.physmem2.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.physmem2.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.physmem2.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem2.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem2.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem2.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem2.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem2.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem2.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem2.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem2.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem2.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem2.totQLat 0 # Total cycles spent in queuing delays -system.physmem2.totMemAccLat 0 # Sum of mem lat for all requests -system.physmem2.totBusLat 0 # Total cycles spent in databus access -system.physmem2.totBankLat 0 # Total cycles spent in bank access -system.physmem2.avgQLat nan # Average queueing delay per request -system.physmem2.avgBankLat nan # Average bank access latency per request -system.physmem2.avgBusLat nan # Average bus latency per request -system.physmem2.avgMemAccLat nan # Average memory access latency -system.physmem2.avgRdBW 0.00 # Average achieved read bandwidth in MB/s -system.physmem2.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem2.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s -system.physmem2.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem2.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem2.busUtil 0.00 # Data bus utilization in percentage -system.physmem2.avgRdQLen 0.00 # Average read queue length over time -system.physmem2.avgWrQLen 0.00 # Average write queue length over time -system.physmem2.readRowHits 0 # Number of row buffer hits during reads -system.physmem2.writeRowHits 0 # Number of row buffer hits during writes -system.physmem2.readRowHitRate nan # Row buffer hit rate for reads -system.physmem2.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem2.avgGap nan # Average gap between requests -system.nvram.bytes_read::cpu.data 284 # Number of bytes read from this memory -system.nvram.bytes_read::total 284 # Number of bytes read from this memory -system.nvram.bytes_written::cpu.data 92 # Number of bytes written to this memory -system.nvram.bytes_written::total 92 # Number of bytes written to this memory -system.nvram.num_reads::cpu.data 284 # Number of read requests responded to by this memory -system.nvram.num_reads::total 284 # Number of read requests responded to by this memory -system.nvram.num_writes::cpu.data 92 # Number of write requests responded to by this memory -system.nvram.num_writes::total 92 # Number of write requests responded to by this memory -system.nvram.bw_read::cpu.data 127 # Total read bandwidth from this memory (bytes/s) -system.nvram.bw_read::total 127 # Total read bandwidth from this memory (bytes/s) -system.nvram.bw_write::cpu.data 41 # Write bandwidth from this memory (bytes/s) -system.nvram.bw_write::total 41 # Write bandwidth from this memory (bytes/s) -system.nvram.bw_total::cpu.data 168 # Total bandwidth to/from this memory (bytes/s) -system.nvram.bw_total::total 168 # Total bandwidth to/from this memory (bytes/s) -system.cpu.numCycles 2233777513 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 2228284650 # Number of instructions committed -system.cpu.committedOps 2229160714 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1839325658 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 14608322 # Number of float alu accesses -system.cpu.num_func_calls 44037246 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 316367761 # number of instructions that are conditional controls -system.cpu.num_int_insts 1839325658 # number of integer instructions -system.cpu.num_fp_insts 14608322 # number of float instructions -system.cpu.num_int_register_reads 4305540407 # number of times the integer registers were read -system.cpu.num_int_register_writes 2100562807 # number of times the integer registers were written -system.cpu.num_fp_register_reads 35401841 # number of times the floating registers were read -system.cpu.num_fp_register_writes 22917558 # number of times the floating registers were written -system.cpu.num_mem_refs 547951940 # number of memory refs -system.cpu.num_load_insts 349807670 # Number of load instructions -system.cpu.num_store_insts 198144270 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 2233777513 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed - ----------- End Simulation Statistics ---------- |