diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2014-01-24 15:29:34 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2014-01-24 15:29:34 -0600 |
| commit | cfb805cc71bd1c4b72691b69faa879663e548c11 (patch) | |
| tree | 4ef4be8b34eb3722e303546a96956b1adaa3315b /tests/long/fs | |
| parent | 612f8f074fa1099cf70faf495d46cc647762a031 (diff) | |
| download | gem5-cfb805cc71bd1c4b72691b69faa879663e548c11.tar.xz | |
stats: update stats for ARMv8 changes
Diffstat (limited to 'tests/long/fs')
24 files changed, 11275 insertions, 9772 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini index d2896598b..add5f9d75 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini @@ -14,6 +14,7 @@ children=bridge cf0 clk_domain cpu cpu_clk_domain intrctrl iobus iocache membus atags_addr=256 boot_loader=/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain dtb_filename= @@ -22,9 +23,16 @@ enable_context_switch_stats_dump=false eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 +have_generic_timer=false +have_large_asid_64=false +have_lpae=false +have_security=false +have_virtualization=false +highest_el_is_64=false init_param=0 kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 +load_offset=0 machine_type=RealView_PBX mem_mode=timing mem_ranges=0:134217727 @@ -33,7 +41,9 @@ multi_proc=true num_work_ids=16 panic_on_oops=true panic_on_panic=true +phys_addr_range_64=40 readfile=tests/halt.sh +reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -86,7 +96,7 @@ voltage_domain=system.voltage_domain [system.cpu] type=DerivO3CPU -children=branchPred checker dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer +children=branchPred checker dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer LFSTSize=1024 LQEntries=32 LSQCheckLoads=true @@ -112,6 +122,7 @@ dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 fetchBufferSize=64 @@ -130,6 +141,7 @@ interrupts=system.cpu.interrupts isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -191,13 +203,14 @@ predType=tournament [system.cpu.checker] type=O3Checker -children=dtb isa itb tracer +children=dstage2_mmu dtb isa istage2_mmu itb tracer checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.checker.dstage2_mmu dtb=system.cpu.checker.dtb eventq_index=0 exitOnError=false @@ -205,6 +218,7 @@ function_trace=false function_trace_start=0 interrupts=Null isa=system.cpu.checker.isa +istage2_mmu=system.cpu.checker.istage2_mmu itb=system.cpu.checker.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -221,10 +235,35 @@ updateOnError=true warnOnlyOnLoadError=true workload= +[system.cpu.checker.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.checker.dstage2_mmu.stage2_tlb +tlb=system.cpu.checker.dtb + +[system.cpu.checker.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.checker.dstage2_mmu.stage2_tlb.walker + +[system.cpu.checker.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[9] + [system.cpu.checker.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.checker.dtb.walker @@ -232,32 +271,69 @@ walker=system.cpu.checker.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system -port=system.cpu.toL2Bus.slave[5] +port=system.cpu.toL2Bus.slave[7] [system.cpu.checker.isa] type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.checker.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.checker.istage2_mmu.stage2_tlb +tlb=system.cpu.checker.itb + +[system.cpu.checker.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.checker.istage2_mmu.stage2_tlb.walker + +[system.cpu.checker.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[8] [system.cpu.checker.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.checker.itb.walker @@ -265,9 +341,10 @@ walker=system.cpu.checker.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system -port=system.cpu.toL2Bus.slave[4] +port=system.cpu.toL2Bus.slave[6] [system.cpu.checker.tracer] type=ExeTracer @@ -308,10 +385,35 @@ hit_latency=2 sequential_access=false size=32768 +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[5] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -319,6 +421,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -673,24 +776,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[4] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -698,6 +837,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -746,7 +886,7 @@ system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port system.cpu.checker.istage2_mmu.stage2_tlb.walker.port system.cpu.checker.dstage2_mmu.stage2_tlb.walker.port [system.cpu.tracer] type=ExeTracer diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr index ccd250823..43698041c 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr @@ -10,25 +10,20 @@ warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr dccimvac' unimplemented warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented -warn: 6165886500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3744, checker: 0x3748 -warn: 6172734500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708 -warn: 6181171500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8 -warn: 6216960500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608 -warn: 6232347500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8 -warn: 6775306000: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8 +warn: 6176053500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708 +warn: 6184767500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8 +warn: 6220839500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608 +warn: 6236327500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8 +warn: 6779610500: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8 warn: LCD dual screen mode not supported -warn: 51869237500: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04 -warn: instruction 'mcr icialluis' unimplemented -warn: instruction 'mcr bpiallis' unimplemented -warn: 2475417694000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0 -warn: 2489281853500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 -warn: 2490491047500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2a4, checker: 0 -warn: 2511643992000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 -warn: 2512158375000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 -warn: 2516381302500: Instruction results do not match! (Values may not actually be integers) Inst: 0xee6b2, checker: 0 -warn: 2516399186500: Instruction results do not match! (Values may not actually be integers) Inst: 0x4001f92c, checker: 0x4001ef10 -warn: 2517881609000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0 -warn: 2518389750000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d954, checker: 0 -warn: 2518949430500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0 -warn: 2518950618000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0 -warn: 2519498238000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2fc, checker: 0 +warn: 51874115000: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04 +warn: 2476169247000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0 +warn: 2490093200000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 +warn: 2491309014500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2a4, checker: 0 +warn: 2512521404000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 +warn: 2513043156000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 +warn: 2517323856500: Instruction results do not match! (Values may not actually be integers) Inst: 0x4001f92c, checker: 0x4001ef10 +warn: 2518814467000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0 +warn: 2519896624000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0 +warn: 2519897721500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0 +warn: 2520452967000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2fc, checker: 0 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout index a9e6de1f3..a26501a59 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout @@ -1,12 +1,15 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 23 2014 00:07:43 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 18:47:40 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 + 0: system.cpu.checker.isa: ISA system set to: 0x645a800 0x645a800 + 0: system.cpu.isa: ISA system set to: 0x645a800 0x645a800 info: Using bootloader at address 0x80000000 +info: Using kernel entry physical address at 0x8000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2525131633500 because m5_exit instruction encountered +Exiting @ tick 2526146947500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index e81d47f63..1902f9930 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,136 +1,136 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.525132 # Number of seconds simulated -sim_ticks 2525131633500 # Number of ticks simulated -final_tick 2525131633500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.526147 # Number of seconds simulated +sim_ticks 2526146947500 # Number of ticks simulated +final_tick 2526146947500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 63748 # Simulator instruction rate (inst/s) -host_op_rate 82026 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2669254242 # Simulator tick rate (ticks/s) -host_mem_usage 403420 # Number of bytes of host memory used -host_seconds 946.01 # Real time elapsed on the host -sim_insts 60305678 # Number of instructions simulated -sim_ops 77596684 # Number of ops (including micro ops) simulated +host_inst_rate 57077 # Simulator instruction rate (inst/s) +host_op_rate 73443 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2390895648 # Simulator tick rate (ticks/s) +host_mem_usage 424332 # Number of bytes of host memory used +host_seconds 1056.57 # Real time elapsed on the host +sim_insts 60306154 # Number of instructions simulated +sim_ops 77597242 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 2688 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3328 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 796928 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9094736 # Number of bytes read from this memory -system.physmem.bytes_read::total 129432144 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 796928 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 796928 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3784384 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 796736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9093720 # Number of bytes read from this memory +system.physmem.bytes_read::total 129431576 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 796736 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 796736 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3782528 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6800456 # Number of bytes written to this memory +system.physmem.bytes_written::total 6798600 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 42 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 52 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12452 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142139 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096843 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59131 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 12449 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142125 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096836 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59102 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813149 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47339181 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1064 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 813120 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47320155 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1317 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 315599 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3601688 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51257583 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 315599 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 315599 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1498688 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1194422 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2693110 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1498688 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47339181 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1064 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 315396 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3599838 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51236756 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 315396 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 315396 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1497351 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1193942 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2691292 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1497351 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47320155 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1317 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 315599 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4796110 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53950692 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15096843 # Number of read requests accepted -system.physmem.writeReqs 813149 # Number of write requests accepted -system.physmem.readBursts 15096843 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 813149 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 963738752 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 2459200 # Total number of bytes read from write queue -system.physmem.bytesWritten 6902144 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 129432144 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6800456 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 38425 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 705284 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4682 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 943580 # Per bank write bursts -system.physmem.perBankRdBursts::1 943152 # Per bank write bursts -system.physmem.perBankRdBursts::2 939288 # Per bank write bursts -system.physmem.perBankRdBursts::3 939310 # Per bank write bursts -system.physmem.perBankRdBursts::4 943113 # Per bank write bursts -system.physmem.perBankRdBursts::5 943139 # Per bank write bursts -system.physmem.perBankRdBursts::6 939134 # Per bank write bursts -system.physmem.perBankRdBursts::7 938551 # Per bank write bursts -system.physmem.perBankRdBursts::8 944000 # Per bank write bursts -system.physmem.perBankRdBursts::9 943392 # Per bank write bursts -system.physmem.perBankRdBursts::10 938425 # Per bank write bursts -system.physmem.perBankRdBursts::11 937973 # Per bank write bursts -system.physmem.perBankRdBursts::12 943928 # Per bank write bursts -system.physmem.perBankRdBursts::13 943534 # Per bank write bursts -system.physmem.perBankRdBursts::14 939230 # Per bank write bursts -system.physmem.perBankRdBursts::15 938669 # Per bank write bursts -system.physmem.perBankWrBursts::0 6703 # Per bank write bursts -system.physmem.perBankWrBursts::1 6464 # Per bank write bursts -system.physmem.perBankWrBursts::2 6595 # Per bank write bursts -system.physmem.perBankWrBursts::3 6634 # Per bank write bursts -system.physmem.perBankWrBursts::4 6559 # Per bank write bursts -system.physmem.perBankWrBursts::5 6792 # Per bank write bursts -system.physmem.perBankWrBursts::6 6793 # Per bank write bursts -system.physmem.perBankWrBursts::7 6730 # Per bank write bursts -system.physmem.perBankWrBursts::8 7130 # Per bank write bursts -system.physmem.perBankWrBursts::9 6877 # Per bank write bursts -system.physmem.perBankWrBursts::10 6539 # Per bank write bursts -system.physmem.perBankWrBursts::11 6181 # Per bank write bursts -system.physmem.perBankWrBursts::12 7151 # Per bank write bursts -system.physmem.perBankWrBursts::13 6766 # Per bank write bursts -system.physmem.perBankWrBursts::14 7035 # Per bank write bursts -system.physmem.perBankWrBursts::15 6897 # Per bank write bursts +system.physmem.bw_total::cpu.inst 315396 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4793780 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53928049 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15096836 # Number of read requests accepted +system.physmem.writeReqs 813120 # Number of write requests accepted +system.physmem.readBursts 15096836 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 813120 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 963731584 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 2465920 # Total number of bytes read from write queue +system.physmem.bytesWritten 6899264 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 129431576 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6798600 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 38530 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 705302 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4683 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 943582 # Per bank write bursts +system.physmem.perBankRdBursts::1 943071 # Per bank write bursts +system.physmem.perBankRdBursts::2 939289 # Per bank write bursts +system.physmem.perBankRdBursts::3 939279 # Per bank write bursts +system.physmem.perBankRdBursts::4 943119 # Per bank write bursts +system.physmem.perBankRdBursts::5 943242 # Per bank write bursts +system.physmem.perBankRdBursts::6 939090 # Per bank write bursts +system.physmem.perBankRdBursts::7 938633 # Per bank write bursts +system.physmem.perBankRdBursts::8 943981 # Per bank write bursts +system.physmem.perBankRdBursts::9 943506 # Per bank write bursts +system.physmem.perBankRdBursts::10 938534 # Per bank write bursts +system.physmem.perBankRdBursts::11 937721 # Per bank write bursts +system.physmem.perBankRdBursts::12 943933 # Per bank write bursts +system.physmem.perBankRdBursts::13 943406 # Per bank write bursts +system.physmem.perBankRdBursts::14 939034 # Per bank write bursts +system.physmem.perBankRdBursts::15 938886 # Per bank write bursts +system.physmem.perBankWrBursts::0 6687 # Per bank write bursts +system.physmem.perBankWrBursts::1 6452 # Per bank write bursts +system.physmem.perBankWrBursts::2 6617 # Per bank write bursts +system.physmem.perBankWrBursts::3 6618 # Per bank write bursts +system.physmem.perBankWrBursts::4 6551 # Per bank write bursts +system.physmem.perBankWrBursts::5 6799 # Per bank write bursts +system.physmem.perBankWrBursts::6 6798 # Per bank write bursts +system.physmem.perBankWrBursts::7 6724 # Per bank write bursts +system.physmem.perBankWrBursts::8 7121 # Per bank write bursts +system.physmem.perBankWrBursts::9 6870 # Per bank write bursts +system.physmem.perBankWrBursts::10 6536 # Per bank write bursts +system.physmem.perBankWrBursts::11 6184 # Per bank write bursts +system.physmem.perBankWrBursts::12 7152 # Per bank write bursts +system.physmem.perBankWrBursts::13 6752 # Per bank write bursts +system.physmem.perBankWrBursts::14 7039 # Per bank write bursts +system.physmem.perBankWrBursts::15 6901 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2525130505500 # Total gap between requests +system.physmem.totGap 2526145872500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 36 # Read request sizes (log2) +system.physmem.readPktSize::2 38 # Read request sizes (log2) system.physmem.readPktSize::3 14942208 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 154599 # Read request sizes (log2) +system.physmem.readPktSize::6 154590 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 754018 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 59131 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1173486 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1117689 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1073548 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3627714 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2609756 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2597217 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2603662 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 53378 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 57682 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 21065 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 20906 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 20772 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 20512 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 20369 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 20252 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 20160 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 238 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59102 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1174955 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1121426 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1077218 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3628637 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2607777 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2593781 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2599800 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 53131 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 57465 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 21079 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 20890 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 20765 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 20515 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 20363 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 20256 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 20150 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 94 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -145,616 +145,621 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 4766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5445 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4889 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5098 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4856 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4880 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4887 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4810 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4807 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4811 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4797 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4789 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4789 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4794 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4797 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4825 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4820 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4809 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5448 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4902 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4875 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4866 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4857 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4818 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4808 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4790 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4794 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4798 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4790 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4786 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4809 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4807 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4795 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 86134 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 11268.950798 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 1000.903149 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 16775.480046 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-71 23607 27.41% 27.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-135 14081 16.35% 43.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-199 2628 3.05% 46.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-263 2075 2.41% 49.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-327 1317 1.53% 50.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-391 1250 1.45% 52.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-455 847 0.98% 53.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-519 989 1.15% 54.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-583 557 0.65% 54.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-647 603 0.70% 55.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-711 514 0.60% 56.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-775 583 0.68% 56.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-839 284 0.33% 57.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-903 264 0.31% 57.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-967 155 0.18% 57.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1031 634 0.74% 58.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1095 90 0.10% 58.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1159 143 0.17% 58.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1223 77 0.09% 58.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1287 121 0.14% 59.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1351 52 0.06% 59.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1415 516 0.60% 59.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1479 33 0.04% 59.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1543 269 0.31% 60.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1607 22 0.03% 60.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1671 94 0.11% 60.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1735 18 0.02% 60.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1799 142 0.16% 60.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1863 22 0.03% 60.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1927 57 0.07% 60.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1991 13 0.02% 60.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2055 390 0.45% 60.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2119 6 0.01% 60.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2183 32 0.04% 60.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2247 13 0.02% 60.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2311 120 0.14% 61.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2375 5 0.01% 61.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2439 22 0.03% 61.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2503 8 0.01% 61.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2567 107 0.12% 61.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2631 7 0.01% 61.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2695 24 0.03% 61.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2759 11 0.01% 61.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2823 86 0.10% 61.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2887 7 0.01% 61.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2951 27 0.03% 61.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 86110 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 11271.974916 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 1003.850407 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 16772.129499 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 23407 27.18% 27.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 14160 16.44% 43.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 2694 3.13% 46.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 2155 2.50% 49.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 1262 1.47% 50.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 1178 1.37% 52.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 892 1.04% 53.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 1078 1.25% 54.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 591 0.69% 55.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 609 0.71% 55.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 535 0.62% 56.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-775 547 0.64% 57.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-839 279 0.32% 57.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-903 297 0.34% 57.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 152 0.18% 57.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 456 0.53% 58.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 120 0.14% 58.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1159 137 0.16% 58.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1223 61 0.07% 58.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1287 169 0.20% 58.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1351 52 0.06% 59.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1415 508 0.59% 59.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1479 23 0.03% 59.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1543 260 0.30% 59.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1607 13 0.02% 59.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1671 93 0.11% 60.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1735 18 0.02% 60.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1799 141 0.16% 60.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1863 16 0.02% 60.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1927 46 0.05% 60.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1991 16 0.02% 60.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2055 376 0.44% 60.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2119 11 0.01% 60.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2183 34 0.04% 60.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2247 13 0.02% 60.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2311 70 0.08% 60.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2375 7 0.01% 60.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2439 29 0.03% 60.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2503 6 0.01% 60.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2567 165 0.19% 61.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2631 6 0.01% 61.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2695 16 0.02% 61.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2759 8 0.01% 61.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2823 175 0.20% 61.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2887 13 0.02% 61.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2951 17 0.02% 61.45% # Bytes accessed per row activation system.physmem.bytesPerActivate::3008-3015 4 0.00% 61.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3079 358 0.42% 61.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3143 7 0.01% 61.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3207 18 0.02% 61.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3271 8 0.01% 61.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3335 154 0.18% 62.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3399 9 0.01% 62.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3463 15 0.02% 62.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3527 8 0.01% 62.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3591 31 0.04% 62.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3655 4 0.00% 62.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3719 11 0.01% 62.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3783 7 0.01% 62.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3847 39 0.05% 62.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3911 9 0.01% 62.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3975 15 0.02% 62.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4039 10 0.01% 62.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4103 368 0.43% 62.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4167 4 0.00% 62.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4231 15 0.02% 62.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4295 8 0.01% 62.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4359 165 0.19% 62.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4423 14 0.02% 62.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4487 12 0.01% 62.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4551 8 0.01% 62.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4615 92 0.11% 63.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4679 3 0.00% 63.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4743 8 0.01% 63.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4807 2 0.00% 63.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4871 95 0.11% 63.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4935 2 0.00% 63.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4999 16 0.02% 63.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5063 5 0.01% 63.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5127 379 0.44% 63.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5191 5 0.01% 63.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5255 10 0.01% 63.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5319 5 0.01% 63.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5383 88 0.10% 63.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5447 11 0.01% 63.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5511 21 0.02% 63.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5575 3 0.00% 63.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5639 146 0.17% 63.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5703 2 0.00% 63.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5767 8 0.01% 64.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5831 2 0.00% 64.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5895 64 0.07% 64.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5959 1 0.00% 64.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6023 13 0.02% 64.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6087 11 0.01% 64.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6151 283 0.33% 64.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6215 1 0.00% 64.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6279 8 0.01% 64.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6343 2 0.00% 64.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6407 88 0.10% 64.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6471 4 0.00% 64.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6535 11 0.01% 64.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6599 6 0.01% 64.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6663 153 0.18% 64.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6727 1 0.00% 64.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6791 14 0.02% 64.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6855 7 0.01% 64.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6919 78 0.09% 64.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6983 2 0.00% 64.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7047 9 0.01% 64.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7111 4 0.00% 64.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7175 368 0.43% 65.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7239 2 0.00% 65.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7303 11 0.01% 65.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7367 12 0.01% 65.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7431 136 0.16% 65.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7495 5 0.01% 65.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3079 306 0.36% 61.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3143 11 0.01% 61.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3207 15 0.02% 61.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3271 9 0.01% 61.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3335 94 0.11% 61.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3399 11 0.01% 61.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3463 22 0.03% 61.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3527 5 0.01% 62.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3591 99 0.11% 62.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3655 9 0.01% 62.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3719 12 0.01% 62.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3783 8 0.01% 62.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3847 93 0.11% 62.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3911 7 0.01% 62.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3975 21 0.02% 62.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4039 5 0.01% 62.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4103 365 0.42% 62.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4167 6 0.01% 62.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4231 12 0.01% 62.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4295 7 0.01% 62.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4359 91 0.11% 62.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4423 13 0.02% 62.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4487 7 0.01% 62.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4551 5 0.01% 62.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4615 21 0.02% 62.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4679 3 0.00% 62.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4743 11 0.01% 62.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4807 9 0.01% 62.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4871 161 0.19% 63.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4935 5 0.01% 63.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4999 16 0.02% 63.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5063 7 0.01% 63.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5127 409 0.47% 63.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5191 11 0.01% 63.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5255 9 0.01% 63.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5319 13 0.02% 63.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5383 56 0.07% 63.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5447 5 0.01% 63.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5511 15 0.02% 63.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5575 8 0.01% 63.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5639 79 0.09% 63.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5703 2 0.00% 63.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5767 10 0.01% 63.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5831 9 0.01% 63.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5895 142 0.16% 64.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5959 3 0.00% 64.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6023 18 0.02% 64.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6087 9 0.01% 64.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6151 348 0.40% 64.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6215 6 0.01% 64.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6279 7 0.01% 64.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6343 3 0.00% 64.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6407 23 0.03% 64.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6471 1 0.00% 64.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6535 7 0.01% 64.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6599 4 0.00% 64.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6663 95 0.11% 64.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6791 17 0.02% 64.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6855 3 0.00% 64.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6919 100 0.12% 64.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7047 11 0.01% 64.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7111 7 0.01% 64.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7175 484 0.56% 65.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7239 2 0.00% 65.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7303 7 0.01% 65.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7367 12 0.01% 65.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7431 86 0.10% 65.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7495 3 0.00% 65.50% # Bytes accessed per row activation system.physmem.bytesPerActivate::7552-7559 9 0.01% 65.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7623 1 0.00% 65.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7687 88 0.10% 65.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7751 2 0.00% 65.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7815 9 0.01% 65.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7879 5 0.01% 65.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7943 84 0.10% 65.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8007 1 0.00% 65.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8071 11 0.01% 65.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7623 2 0.00% 65.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7687 27 0.03% 65.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7815 10 0.01% 65.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7879 1 0.00% 65.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7943 155 0.18% 65.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8007 1 0.00% 65.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8071 8 0.01% 65.75% # Bytes accessed per row activation system.physmem.bytesPerActivate::8128-8135 1 0.00% 65.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8199 389 0.45% 66.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8256-8263 1 0.00% 66.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8320-8327 2 0.00% 66.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8455 79 0.09% 66.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8640-8647 1 0.00% 66.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8711 78 0.09% 66.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8832-8839 1 0.00% 66.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8896-8903 1 0.00% 66.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8967 130 0.15% 66.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9088-9095 1 0.00% 66.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9223 355 0.41% 66.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9344-9351 2 0.00% 66.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9479 73 0.08% 67.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9536-9543 1 0.00% 67.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9600-9607 4 0.00% 67.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9664-9671 1 0.00% 67.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9735 140 0.16% 67.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9792-9799 2 0.00% 67.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9920-9927 1 0.00% 67.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9991 79 0.09% 67.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10112-10119 4 0.00% 67.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10247 272 0.32% 67.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10432-10439 1 0.00% 67.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10503 15 0.02% 67.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10560-10567 1 0.00% 67.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10624-10631 1 0.00% 67.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10759 132 0.15% 67.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10944-10951 3 0.00% 67.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11015 75 0.09% 67.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11271 373 0.43% 68.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11392-11399 1 0.00% 68.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11527 86 0.10% 68.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11584-11591 2 0.00% 68.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11648-11655 1 0.00% 68.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11712-11719 2 0.00% 68.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11783 77 0.09% 68.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11904-11911 2 0.00% 68.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11968-11975 1 0.00% 68.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12039 144 0.17% 68.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12096-12103 1 0.00% 68.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12160-12167 4 0.00% 68.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12295 340 0.39% 69.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12352-12359 1 0.00% 69.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12416-12423 2 0.00% 69.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12480-12487 1 0.00% 69.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12551 26 0.03% 69.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12807 18 0.02% 69.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12864-12871 1 0.00% 69.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12928-12935 1 0.00% 69.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12992-12999 2 0.00% 69.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13063 146 0.17% 69.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13120-13127 1 0.00% 69.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13184-13191 2 0.00% 69.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13319 339 0.39% 69.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13575 74 0.09% 69.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13831 78 0.09% 69.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13888-13895 1 0.00% 69.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13952-13959 1 0.00% 69.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14087 87 0.10% 70.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14144-14151 2 0.00% 70.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14215 4 0.00% 70.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14343 340 0.39% 70.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14599 79 0.09% 70.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14720-14727 4 0.00% 70.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14855 86 0.10% 70.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14912-14919 2 0.00% 70.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14976-14983 1 0.00% 70.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15111 13 0.02% 70.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15232-15239 2 0.00% 70.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15296-15303 1 0.00% 70.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15367 405 0.47% 71.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15424-15431 1 0.00% 71.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15552-15559 1 0.00% 71.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15623 83 0.10% 71.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15680-15687 1 0.00% 71.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15879 89 0.10% 71.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16064-16071 1 0.00% 71.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16135 86 0.10% 71.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16256-16263 12 0.01% 71.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16391 642 0.75% 72.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16647 86 0.10% 72.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16704-16711 2 0.00% 72.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16768-16775 1 0.00% 72.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16903 84 0.10% 72.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17088-17095 1 0.00% 72.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17159 92 0.11% 72.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17280-17287 4 0.00% 72.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17344-17351 1 0.00% 72.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17415 410 0.48% 72.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17472-17479 2 0.00% 72.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17536-17543 3 0.00% 72.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17671 15 0.02% 72.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17728-17735 1 0.00% 72.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17792-17799 5 0.01% 72.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17856-17863 1 0.00% 72.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17927 86 0.10% 73.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17984-17991 1 0.00% 73.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18048-18055 1 0.00% 73.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18112-18119 2 0.00% 73.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18183 83 0.10% 73.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18304-18311 3 0.00% 73.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18439 331 0.38% 73.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18496-18503 1 0.00% 73.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18560-18567 1 0.00% 73.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18695 89 0.10% 73.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18880-18887 2 0.00% 73.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18944-18951 83 0.10% 73.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19136-19143 1 0.00% 73.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19207 74 0.09% 73.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19328-19335 3 0.00% 73.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19463 326 0.38% 74.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19520-19527 1 0.00% 74.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19584-19591 3 0.00% 74.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19648-19655 1 0.00% 74.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19719 138 0.16% 74.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19840-19847 1 0.00% 74.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19968-19975 15 0.02% 74.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20231 23 0.03% 74.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20288-20295 1 0.00% 74.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20352-20359 3 0.00% 74.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20487 336 0.39% 74.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20608-20615 1 0.00% 74.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20672-20679 2 0.00% 74.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20736-20743 143 0.17% 75.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20864-20871 3 0.00% 75.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-20999 73 0.08% 75.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21184-21191 1 0.00% 75.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21248-21255 89 0.10% 75.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21312-21319 1 0.00% 75.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21376-21383 3 0.00% 75.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21440-21447 1 0.00% 75.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21511 367 0.43% 75.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21568-21575 1 0.00% 75.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21632-21639 1 0.00% 75.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21767 76 0.09% 75.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21824-21831 1 0.00% 75.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21888-21895 5 0.01% 75.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22023 129 0.15% 75.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22144-22151 1 0.00% 75.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22279 14 0.02% 75.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22336-22343 1 0.00% 75.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22400-22407 3 0.00% 75.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22464-22471 2 0.00% 75.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22535 268 0.31% 76.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22720-22727 2 0.00% 76.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22791 78 0.09% 76.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22848-22855 1 0.00% 76.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22912-22919 1 0.00% 76.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22976-22983 2 0.00% 76.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23040-23047 143 0.17% 76.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23104-23111 1 0.00% 76.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23168-23175 1 0.00% 76.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23296-23303 77 0.09% 76.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23360-23367 3 0.00% 76.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23424-23431 2 0.00% 76.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23559 350 0.41% 76.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23680-23687 1 0.00% 76.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23808-23815 126 0.15% 77.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23936-23943 1 0.00% 77.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24000-24007 2 0.00% 77.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24071 74 0.09% 77.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24192-24199 2 0.00% 77.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24256-24263 1 0.00% 77.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24327 82 0.10% 77.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24448-24455 3 0.00% 77.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24583 270 0.31% 77.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24839 79 0.09% 77.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25024-25031 1 0.00% 77.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25088-25095 77 0.09% 77.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8199 378 0.44% 66.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8256-8263 1 0.00% 66.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8455 152 0.18% 66.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8711 21 0.02% 66.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8832-8839 2 0.00% 66.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8967 72 0.08% 66.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9024-9031 2 0.00% 66.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9088-9095 5 0.01% 66.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9152-9159 1 0.00% 66.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9223 466 0.54% 67.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9344-9351 1 0.00% 67.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9479 96 0.11% 67.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9536-9543 1 0.00% 67.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9735 85 0.10% 67.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9920-9927 1 0.00% 67.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9991 17 0.02% 67.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10112-10119 2 0.00% 67.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10247 345 0.40% 67.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10304-10311 1 0.00% 67.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10368-10375 1 0.00% 67.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10432-10439 1 0.00% 67.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10503 83 0.10% 67.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10759 68 0.08% 67.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10944-10951 1 0.00% 67.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11015 39 0.05% 67.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11136-11143 4 0.00% 67.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11271 396 0.46% 68.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11328-11335 2 0.00% 68.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11456-11463 1 0.00% 68.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11527 156 0.18% 68.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11584-11591 2 0.00% 68.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11783 8 0.01% 68.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11968-11975 1 0.00% 68.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12039 83 0.10% 68.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12160-12167 2 0.00% 68.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12224-12231 1 0.00% 68.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12295 336 0.39% 69.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12352-12359 1 0.00% 69.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12416-12423 1 0.00% 69.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12480-12487 1 0.00% 69.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12551 83 0.10% 69.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12672-12679 2 0.00% 69.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12736-12743 1 0.00% 69.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12807 81 0.09% 69.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12864-12871 1 0.00% 69.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12928-12935 2 0.00% 69.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13063 70 0.08% 69.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13184-13191 3 0.00% 69.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13248-13255 1 0.00% 69.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13319 277 0.32% 69.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13376-13383 1 0.00% 69.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13440-13447 3 0.00% 69.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13575 151 0.18% 69.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13696-13703 1 0.00% 69.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13831 132 0.15% 69.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14087 32 0.04% 70.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14215 2 0.00% 70.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14343 338 0.39% 70.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14464-14471 1 0.00% 70.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14528-14535 1 0.00% 70.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14599 77 0.09% 70.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14720-14727 2 0.00% 70.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14784-14791 1 0.00% 70.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14855 81 0.09% 70.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14919 1 0.00% 70.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15111 72 0.08% 70.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15239 2 0.00% 70.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15367 269 0.31% 71.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15424-15431 2 0.00% 71.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15488-15495 1 0.00% 71.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15623 83 0.10% 71.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15680-15687 1 0.00% 71.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15744-15751 3 0.00% 71.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15808-15815 1 0.00% 71.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15879 157 0.18% 71.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16000-16007 3 0.00% 71.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16135 129 0.15% 71.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16192-16199 1 0.00% 71.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16256-16263 7 0.01% 71.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16320-16327 2 0.00% 71.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16391 524 0.61% 72.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16512-16519 3 0.00% 72.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16647 130 0.15% 72.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16768-16775 2 0.00% 72.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16832-16839 3 0.00% 72.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16896-16903 155 0.18% 72.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16960-16967 3 0.00% 72.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17024-17031 1 0.00% 72.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17159 86 0.10% 72.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17216-17223 1 0.00% 72.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17280-17287 1 0.00% 72.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17344-17351 1 0.00% 72.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17415 268 0.31% 72.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17472-17479 3 0.00% 72.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17536-17543 1 0.00% 72.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17671 70 0.08% 72.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17927 80 0.09% 73.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17984-17991 2 0.00% 73.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18048-18055 2 0.00% 73.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18183 82 0.10% 73.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18240-18247 1 0.00% 73.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18304-18311 2 0.00% 73.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18439 328 0.38% 73.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18560-18567 1 0.00% 73.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18624-18631 1 0.00% 73.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18688-18695 35 0.04% 73.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18816-18823 1 0.00% 73.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18944-18951 133 0.15% 73.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19008-19015 1 0.00% 73.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19072-19079 2 0.00% 73.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19207 154 0.18% 73.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19328-19335 3 0.00% 73.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19392-19399 1 0.00% 73.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19463 281 0.33% 74.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19712-19719 67 0.08% 74.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19840-19847 1 0.00% 74.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19968-19975 79 0.09% 74.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20032-20039 1 0.00% 74.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20160-20167 1 0.00% 74.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20224-20231 87 0.10% 74.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20352-20359 4 0.00% 74.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20416-20423 1 0.00% 74.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20487 327 0.38% 74.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20608-20615 1 0.00% 74.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20736-20743 77 0.09% 74.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20992-20999 10 0.01% 74.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21056-21063 1 0.00% 74.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21120-21127 1 0.00% 74.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21184-21191 2 0.00% 74.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21248-21255 151 0.18% 75.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21376-21383 4 0.00% 75.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21440-21447 1 0.00% 75.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21511 401 0.47% 75.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21568-21575 1 0.00% 75.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21632-21639 1 0.00% 75.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21760-21767 39 0.05% 75.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21824-21831 2 0.00% 75.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21888-21895 1 0.00% 75.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22016-22023 65 0.08% 75.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22144-22151 2 0.00% 75.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22272-22279 85 0.10% 75.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22336-22343 2 0.00% 75.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22400-22407 4 0.00% 75.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22464-22471 1 0.00% 75.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22535 336 0.39% 76.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22592-22599 1 0.00% 76.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22656-22663 1 0.00% 76.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22784-22791 18 0.02% 76.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22912-22919 3 0.00% 76.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23040-23047 81 0.09% 76.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23104-23111 2 0.00% 76.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23168-23175 1 0.00% 76.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23232-23239 2 0.00% 76.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23296-23303 92 0.11% 76.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23360-23367 1 0.00% 76.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23424-23431 4 0.00% 76.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23488-23495 1 0.00% 76.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23559 463 0.54% 77.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23680-23687 1 0.00% 77.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23808-23815 70 0.08% 77.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23936-23943 1 0.00% 77.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24000-24007 1 0.00% 77.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24064-24071 19 0.02% 77.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24192-24199 1 0.00% 77.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24327 148 0.17% 77.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24384-24391 1 0.00% 77.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24448-24455 5 0.01% 77.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24583 262 0.30% 77.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24640-24647 1 0.00% 77.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24704-24711 3 0.00% 77.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24768-24775 2 0.00% 77.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24832-24839 150 0.17% 77.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24896-24903 1 0.00% 77.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24960-24967 2 0.00% 77.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25088-25095 20 0.02% 77.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25152-25159 1 0.00% 77.82% # Bytes accessed per row activation system.physmem.bytesPerActivate::25216-25223 2 0.00% 77.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25280-25287 1 0.00% 77.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25344-25351 133 0.15% 77.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25472-25479 2 0.00% 77.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25607 355 0.41% 78.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25728-25735 1 0.00% 78.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25856-25863 72 0.08% 78.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25984-25991 2 0.00% 78.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26112-26119 138 0.16% 78.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26176-26183 1 0.00% 78.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26240-26247 1 0.00% 78.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26304-26311 2 0.00% 78.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26375 79 0.09% 78.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26432-26439 1 0.00% 78.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26496-26503 2 0.00% 78.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26560-26567 1 0.00% 78.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26631 269 0.31% 79.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26688-26695 1 0.00% 79.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26752-26759 1 0.00% 79.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26816-26823 1 0.00% 79.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26880-26887 14 0.02% 79.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27008-27015 4 0.00% 79.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27072-27079 1 0.00% 79.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27143 130 0.15% 79.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27200-27207 1 0.00% 79.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27399 74 0.09% 79.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27520-27527 3 0.00% 79.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27584-27591 1 0.00% 79.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27655 367 0.43% 79.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27840-27847 1 0.00% 79.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27911 85 0.10% 79.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27968-27975 2 0.00% 79.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28032-28039 2 0.00% 79.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28096-28103 1 0.00% 79.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28160-28167 75 0.09% 79.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28288-28295 2 0.00% 79.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28352-28359 2 0.00% 79.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28423 143 0.17% 80.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28480-28487 2 0.00% 80.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28544-28551 4 0.00% 80.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28608-28615 1 0.00% 80.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28679 337 0.39% 80.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28736-28743 1 0.00% 80.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28864-28871 2 0.00% 80.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28935 26 0.03% 80.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28992-28999 1 0.00% 80.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29191 17 0.02% 80.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29248-29255 2 0.00% 80.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29312-29319 1 0.00% 80.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29447 139 0.16% 80.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29504-29511 3 0.00% 80.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29568-29575 4 0.00% 80.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25344-25351 73 0.08% 77.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25472-25479 2 0.00% 77.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25607 464 0.54% 78.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25728-25735 1 0.00% 78.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25792-25799 1 0.00% 78.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25856-25863 93 0.11% 78.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25984-25991 3 0.00% 78.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26048-26055 1 0.00% 78.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26112-26119 84 0.10% 78.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26176-26183 1 0.00% 78.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26240-26247 1 0.00% 78.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26304-26311 1 0.00% 78.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26375 18 0.02% 78.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26432-26439 1 0.00% 78.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26496-26503 5 0.01% 78.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26631 339 0.39% 79.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26880-26887 80 0.09% 79.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27008-27015 3 0.00% 79.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27136-27143 63 0.07% 79.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27200-27207 2 0.00% 79.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27399 47 0.05% 79.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27520-27527 2 0.00% 79.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27584-27591 2 0.00% 79.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27655 394 0.46% 79.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27776-27783 2 0.00% 79.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27840-27847 1 0.00% 79.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27911 150 0.17% 79.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28032-28039 1 0.00% 79.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28096-28103 1 0.00% 79.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28160-28167 8 0.01% 79.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28288-28295 2 0.00% 79.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28352-28359 1 0.00% 79.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28423 82 0.10% 80.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28480-28487 1 0.00% 80.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28544-28551 5 0.01% 80.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28608-28615 1 0.00% 80.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28679 329 0.38% 80.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28736-28743 2 0.00% 80.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28800-28807 3 0.00% 80.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28935 83 0.10% 80.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28992-28999 1 0.00% 80.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29120-29127 2 0.00% 80.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29191 82 0.10% 80.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29248-29255 1 0.00% 80.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29312-29319 2 0.00% 80.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29447 72 0.08% 80.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29504-29511 2 0.00% 80.74% # Bytes accessed per row activation system.physmem.bytesPerActivate::29632-29639 1 0.00% 80.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29703 329 0.38% 81.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29824-29831 2 0.00% 81.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29888-29895 2 0.00% 81.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-29959 70 0.08% 81.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30208-30215 79 0.09% 81.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30336-30343 1 0.00% 81.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30471 92 0.11% 81.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30592-30599 4 0.00% 81.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30656-30663 1 0.00% 81.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30727 327 0.38% 81.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30848-30855 4 0.00% 81.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30912-30919 2 0.00% 81.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-30983 84 0.10% 81.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31239 89 0.10% 82.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31360-31367 1 0.00% 82.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31424-31431 1 0.00% 82.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31488-31495 19 0.02% 82.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31552-31559 2 0.00% 82.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31616-31623 5 0.01% 82.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31680-31687 1 0.00% 82.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31751 406 0.47% 82.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31872-31879 1 0.00% 82.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32000-32007 83 0.10% 82.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32064-32071 1 0.00% 82.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32128-32135 2 0.00% 82.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32256-32263 82 0.10% 82.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32320-32327 1 0.00% 82.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32448-32455 2 0.00% 82.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32512-32519 93 0.11% 82.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32576-32583 1 0.00% 82.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32775 645 0.75% 83.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32832-32839 2 0.00% 83.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32896-32903 1 0.00% 83.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33031 83 0.10% 83.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33088-33095 1 0.00% 83.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33152-33159 1 0.00% 83.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33216-33223 2 0.00% 83.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33287 82 0.10% 83.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33408-33415 4 0.00% 83.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33472-33479 1 0.00% 83.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33543 95 0.11% 83.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33664-33671 1 0.00% 83.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33799 411 0.48% 84.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33984-33991 1 0.00% 84.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34048-34055 13 0.02% 84.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34112-34119 1 0.00% 84.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34304-34311 83 0.10% 84.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34432-34439 2 0.00% 84.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34560-34567 86 0.10% 84.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34688-34695 1 0.00% 84.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34823 328 0.38% 84.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35072-35079 86 0.10% 85.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35136-35143 1 0.00% 85.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35200-35207 1 0.00% 85.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35328-35335 76 0.09% 85.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35456-35463 3 0.00% 85.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35584-35591 72 0.08% 85.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35712-35719 1 0.00% 85.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35847 328 0.38% 85.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36096-36103 138 0.16% 85.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36224-36231 1 0.00% 85.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36352-36359 15 0.02% 85.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36480-36487 3 0.00% 85.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36608-36615 25 0.03% 85.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36864-36871 337 0.39% 86.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36992-36999 2 0.00% 86.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37120-37127 141 0.16% 86.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37184-37191 1 0.00% 86.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37376-37383 73 0.08% 86.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37504-37511 3 0.00% 86.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37568-37575 1 0.00% 86.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37632-37639 82 0.10% 86.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37895 365 0.42% 86.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37952-37959 1 0.00% 86.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38016-38023 2 0.00% 86.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38144-38151 75 0.09% 87.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38336-38343 1 0.00% 87.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38400-38407 129 0.15% 87.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38464-38471 1 0.00% 87.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38528-38535 2 0.00% 87.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38592-38599 1 0.00% 87.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38656-38663 14 0.02% 87.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38720-38727 1 0.00% 87.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38912-38919 267 0.31% 87.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38976-38983 1 0.00% 87.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39104-39111 1 0.00% 87.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39168-39175 77 0.09% 87.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39232-39239 1 0.00% 87.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39296-39303 1 0.00% 87.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39424-39431 140 0.16% 87.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39552-39559 2 0.00% 87.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39680-39687 70 0.08% 87.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39808-39815 1 0.00% 87.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39936-39943 351 0.41% 88.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40064-40071 1 0.00% 88.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40192-40199 129 0.15% 88.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40448-40455 76 0.09% 88.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40576-40583 2 0.00% 88.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40640-40647 1 0.00% 88.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40704-40711 80 0.09% 88.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40832-40839 2 0.00% 88.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40960-40967 269 0.31% 88.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41152-41159 2 0.00% 88.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41216-41223 77 0.09% 89.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41408-41415 1 0.00% 89.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41472-41479 75 0.09% 89.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41600-41607 2 0.00% 89.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41728-41735 131 0.15% 89.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41856-41863 3 0.00% 89.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-41991 349 0.41% 89.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42112-42119 2 0.00% 89.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42240-42247 70 0.08% 89.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42496-42503 140 0.16% 89.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42624-42631 2 0.00% 89.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42688-42695 1 0.00% 89.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42752-42759 77 0.09% 90.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42816-42823 1 0.00% 90.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43008-43015 267 0.31% 90.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43136-43143 3 0.00% 90.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43200-43207 1 0.00% 90.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43264-43271 14 0.02% 90.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43328-43335 1 0.00% 90.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43520-43527 127 0.15% 90.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43648-43655 1 0.00% 90.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43776-43783 80 0.09% 90.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43840-43847 2 0.00% 90.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43904-43911 2 0.00% 90.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44032-44039 364 0.42% 91.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44096-44103 1 0.00% 91.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44160-44167 1 0.00% 91.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44224-44231 1 0.00% 91.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44288-44295 83 0.10% 91.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44352-44359 1 0.00% 91.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44416-44423 1 0.00% 91.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44544-44551 73 0.08% 91.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44672-44679 2 0.00% 91.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44800-44807 144 0.17% 91.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44864-44871 2 0.00% 91.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45056-45063 337 0.39% 91.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45184-45191 1 0.00% 91.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45248-45255 1 0.00% 91.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45312-45319 24 0.03% 91.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45440-45447 3 0.00% 91.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45568-45575 16 0.02% 91.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45696-45703 3 0.00% 91.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45824-45831 144 0.17% 92.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45888-45895 2 0.00% 92.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46087 327 0.38% 92.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46144-46151 1 0.00% 92.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46272-46279 1 0.00% 92.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46336-46343 69 0.08% 92.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46464-46471 1 0.00% 92.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46592-46599 79 0.09% 92.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46720-46727 2 0.00% 92.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46848-46855 89 0.10% 92.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46912-46919 1 0.00% 92.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46976-46983 1 0.00% 92.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47104-47111 334 0.39% 93.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47232-47239 2 0.00% 93.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47296-47303 3 0.00% 93.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47360-47367 78 0.09% 93.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47616-47623 88 0.10% 93.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47744-47751 4 0.00% 93.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47872-47879 24 0.03% 93.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47936-47943 1 0.00% 93.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48000-48007 1 0.00% 93.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48135 398 0.46% 93.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48384-48391 83 0.10% 93.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48640-48647 77 0.09% 93.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48768-48775 72 0.08% 94.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48903 83 0.10% 94.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48960-48967 1 0.00% 94.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49024-49031 3 0.00% 94.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49088-49095 1 0.00% 94.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49159 5012 5.82% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29703 276 0.32% 81.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29824-29831 3 0.00% 81.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29888-29895 1 0.00% 81.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-29959 155 0.18% 81.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30016-30023 1 0.00% 81.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30080-30087 2 0.00% 81.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30144-30151 1 0.00% 81.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30215 130 0.15% 81.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30272-30279 1 0.00% 81.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30471 35 0.04% 81.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30592-30599 7 0.01% 81.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30656-30663 2 0.00% 81.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30727 330 0.38% 81.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30784-30791 2 0.00% 81.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30848-30855 1 0.00% 81.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-30983 79 0.09% 81.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31040-31047 1 0.00% 81.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31104-31111 2 0.00% 81.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31239 75 0.09% 82.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31296-31303 1 0.00% 82.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31360-31367 1 0.00% 82.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31495 72 0.08% 82.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31552-31559 2 0.00% 82.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31616-31623 3 0.00% 82.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31680-31687 1 0.00% 82.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31751 264 0.31% 82.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31872-31879 1 0.00% 82.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32007 85 0.10% 82.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32064-32071 2 0.00% 82.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32128-32135 1 0.00% 82.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32263 158 0.18% 82.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32320-32327 1 0.00% 82.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32384-32391 1 0.00% 82.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32448-32455 1 0.00% 82.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32519 132 0.15% 82.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32576-32583 2 0.00% 82.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32640-32647 1 0.00% 82.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32775 526 0.61% 83.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32896-32903 2 0.00% 83.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33031 130 0.15% 83.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33216-33223 1 0.00% 83.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33287 160 0.19% 83.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33408-33415 2 0.00% 83.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33472-33479 1 0.00% 83.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33543 90 0.10% 83.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33600-33607 4 0.00% 83.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33799 276 0.32% 84.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33856-33863 1 0.00% 84.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33920-33927 2 0.00% 84.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34048-34055 69 0.08% 84.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34112-34119 1 0.00% 84.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34304-34311 76 0.09% 84.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34432-34439 3 0.00% 84.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34560-34567 78 0.09% 84.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34688-34695 1 0.00% 84.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34752-34759 1 0.00% 84.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34823 329 0.38% 84.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34944-34951 1 0.00% 84.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35072-35079 37 0.04% 84.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35200-35207 1 0.00% 84.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35328-35335 132 0.15% 85.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35456-35463 1 0.00% 85.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35584-35591 157 0.18% 85.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35712-35719 3 0.00% 85.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35847 272 0.32% 85.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36032-36039 1 0.00% 85.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36096-36103 68 0.08% 85.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36224-36231 2 0.00% 85.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36352-36359 82 0.10% 85.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36480-36487 3 0.00% 85.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36608-36615 85 0.10% 85.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36800-36807 2 0.00% 85.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36871 328 0.38% 86.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37120-37127 78 0.09% 86.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37184-37191 2 0.00% 86.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37248-37255 1 0.00% 86.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37312-37319 1 0.00% 86.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37376-37383 7 0.01% 86.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37504-37511 1 0.00% 86.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37632-37639 154 0.18% 86.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37895 389 0.45% 87.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38016-38023 2 0.00% 87.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38151 41 0.05% 87.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38272-38279 2 0.00% 87.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38336-38343 1 0.00% 87.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38400-38407 63 0.07% 87.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38528-38535 4 0.00% 87.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38656-38663 83 0.10% 87.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38919 332 0.39% 87.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39040-39047 1 0.00% 87.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39168-39175 17 0.02% 87.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39424-39431 81 0.09% 87.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39552-39559 2 0.00% 87.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39680-39687 95 0.11% 87.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39936-39943 463 0.54% 88.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40192-40199 69 0.08% 88.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40320-40327 4 0.00% 88.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40384-40391 1 0.00% 88.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40448-40455 15 0.02% 88.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40576-40583 4 0.00% 88.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40640-40647 1 0.00% 88.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40704-40711 149 0.17% 88.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40967 257 0.30% 88.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41152-41159 1 0.00% 88.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41223 145 0.17% 89.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41344-41351 1 0.00% 89.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41408-41415 1 0.00% 89.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41472-41479 16 0.02% 89.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41536-41543 1 0.00% 89.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41600-41607 2 0.00% 89.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41728-41735 72 0.08% 89.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-41991 458 0.53% 89.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42176-42183 1 0.00% 89.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42240-42247 90 0.10% 89.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42304-42311 2 0.00% 89.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42432-42439 1 0.00% 89.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42503 82 0.10% 89.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42624-42631 4 0.00% 89.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42688-42695 1 0.00% 89.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42759 17 0.02% 90.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42816-42823 1 0.00% 90.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42880-42887 2 0.00% 90.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43015 331 0.38% 90.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43200-43207 1 0.00% 90.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43271 81 0.09% 90.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43328-43335 1 0.00% 90.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43527 64 0.07% 90.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43648-43655 4 0.00% 90.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43712-43719 1 0.00% 90.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43776-43783 37 0.04% 90.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43840-43847 1 0.00% 90.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 395 0.46% 91.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44096-44103 1 0.00% 91.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44295 150 0.17% 91.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44352-44359 2 0.00% 91.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44551 10 0.01% 91.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44608-44615 2 0.00% 91.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44672-44679 4 0.00% 91.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44807 81 0.09% 91.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44864-44871 2 0.00% 91.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 328 0.38% 91.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45319 82 0.10% 91.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45376-45383 2 0.00% 91.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45440-45447 2 0.00% 91.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 83 0.10% 91.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45696-45703 3 0.00% 91.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 69 0.08% 92.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45952-45959 1 0.00% 92.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 277 0.32% 92.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46208-46215 3 0.00% 92.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46343 151 0.18% 92.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46599 129 0.15% 92.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46656-46663 1 0.00% 92.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46720-46727 2 0.00% 92.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46784-46791 1 0.00% 92.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 36 0.04% 92.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46912-46919 1 0.00% 92.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46976-46983 2 0.00% 92.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 330 0.38% 93.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47168-47175 1 0.00% 93.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47296-47303 1 0.00% 93.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 81 0.09% 93.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47488-47495 1 0.00% 93.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47552-47559 1 0.00% 93.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 82 0.10% 93.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47744-47751 1 0.00% 93.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47808-47815 2 0.00% 93.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 74 0.09% 93.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47936-47943 1 0.00% 93.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48000-48007 1 0.00% 93.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 266 0.31% 93.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48256-48263 1 0.00% 93.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 83 0.10% 93.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48512-48519 1 0.00% 93.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 154 0.18% 93.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48704-48711 2 0.00% 93.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48768-48775 62 0.07% 94.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 129 0.15% 94.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48960-48967 2 0.00% 94.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49024-49031 2 0.00% 94.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 4 0.00% 94.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 4946 5.74% 99.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::49216-49223 1 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49408-49415 1 0.00% 99.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::49600-49607 1 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49664-49671 1 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49728-49735 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49856-49863 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49920-49927 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50240-50247 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50368-50375 2 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50496-50503 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50560-50567 2 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50624-50631 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50688-50695 2 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50752-50759 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50944-50951 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51008-51015 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51072-51079 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51136-51143 3 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51200-51207 3 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51264-51271 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51392-51399 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51456-51463 2 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51520-51527 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51840-51847 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49664-49671 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49920-49927 2 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50048-50055 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50176-50183 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50432-50439 4 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50496-50503 2 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50560-50567 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50624-50631 2 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50688-50695 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50816-50823 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50880-50887 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51136-51143 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51200-51207 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51264-51271 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51456-51463 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51584-51591 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51712-51719 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51904-51911 1 0.00% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::51968-51975 2 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 86134 # Bytes accessed per row activation -system.physmem.totQLat 365453646000 # Total ticks spent queuing -system.physmem.totMemAccLat 458164497250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 75292090000 # Total ticks spent in databus transfers -system.physmem.totBankLat 17418761250 # Total ticks spent accessing banks -system.physmem.avgQLat 24269.06 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1156.75 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::52160-52167 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::52288-52295 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 86110 # Bytes accessed per row activation +system.physmem.totQLat 365142496500 # Total ticks spent queuing +system.physmem.totMemAccLat 457904364000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 75291530000 # Total ticks spent in databus transfers +system.physmem.totBankLat 17470337500 # Total ticks spent accessing banks +system.physmem.avgQLat 24248.58 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1160.18 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30425.81 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 381.66 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 30408.76 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 381.50 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.73 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 51.26 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 51.24 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.69 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 3.00 # Data bus utilization in percentage system.physmem.busUtilRead 2.98 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing -system.physmem.avgWrQLen 12.83 # Average write queue length when enqueuing -system.physmem.readRowHits 14986798 # Number of row buffer hits during reads -system.physmem.writeRowHits 93332 # Number of row buffer hits during writes +system.physmem.avgWrQLen 13.37 # Average write queue length when enqueuing +system.physmem.readRowHits 14986658 # Number of row buffer hits during reads +system.physmem.writeRowHits 93339 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 86.53 # Row buffer hit rate for writes -system.physmem.avgGap 158713.50 # Average gap between requests +system.physmem.writeRowHitRate 86.57 # Row buffer hit rate for writes +system.physmem.avgGap 158777.68 # Average gap between requests system.physmem.pageHitRate 99.43 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 1.72 # Percentage of time for which DRAM has all the banks in precharge state +system.physmem.prechargeAllPercent 2.54 # Percentage of time for which DRAM has all the banks in precharge state system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -767,50 +772,50 @@ system.realview.nvmem.bw_inst_read::cpu.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54900302 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16149434 # Transaction distribution -system.membus.trans_dist::ReadResp 16149434 # Transaction distribution +system.membus.throughput 54877277 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16149448 # Transaction distribution +system.membus.trans_dist::ReadResp 16149448 # Transaction distribution system.membus.trans_dist::WriteReq 763332 # Transaction distribution system.membus.trans_dist::WriteResp 763332 # Transaction distribution -system.membus.trans_dist::Writeback 59131 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4679 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4682 # Transaction distribution -system.membus.trans_dist::ReadExReq 131448 # Transaction distribution -system.membus.trans_dist::ReadExResp 131448 # Transaction distribution +system.membus.trans_dist::Writeback 59102 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4681 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4683 # Transaction distribution +system.membus.trans_dist::ReadExReq 131427 # Transaction distribution +system.membus.trans_dist::ReadExResp 131427 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382942 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3760 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885801 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272507 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885760 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272466 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29884416 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 29884416 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34156923 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 34156882 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390301 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7520 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16694936 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19092825 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16692512 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19090401 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119537664 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 119537664 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 138630489 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 138630489 # Total data (bytes) +system.membus.tot_pkt_size::total 138628065 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 138628065 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1486873500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1486850000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3694000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3609000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17363465500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17361408000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4733669250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4731178629 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 33737503451 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 33737119450 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -818,7 +823,7 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 48285786 # Throughput (bytes/s) +system.iobus.throughput 48266379 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 16125522 # Transaction distribution system.iobus.trans_dist::ReadResp 16125522 # Transaction distribution system.iobus.trans_dist::WriteReq 8157 # Transaction distribution @@ -928,40 +933,82 @@ system.iobus.reqLayer25.occupancy 14942208000 # La system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) system.iobus.respLayer0.occupancy 2374785000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 40921719549 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 40921538550 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 14384927 # Number of BP lookups -system.cpu.branchPred.condPredicted 11469310 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 704177 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9471049 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7661571 # Number of BTB hits +system.cpu.branchPred.lookups 14756776 # Number of BP lookups +system.cpu.branchPred.condPredicted 11839520 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 705876 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9493937 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7667614 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.894640 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1398227 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72610 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 80.763270 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1398139 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 72469 # Number of incorrect RAS predictions. +system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 14986834 # DTB read hits +system.cpu.checker.dtb.read_hits 14986903 # DTB read hits system.cpu.checker.dtb.read_misses 7307 # DTB read misses -system.cpu.checker.dtb.write_hits 11227416 # DTB write hits +system.cpu.checker.dtb.write_hits 11227441 # DTB write hits system.cpu.checker.dtb.write_misses 2191 # DTB write misses system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.checker.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.checker.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.checker.dtb.flush_entries 6418 # Number of entries that have been flushed from TLB +system.cpu.checker.dtb.flush_entries 3398 # Number of entries that have been flushed from TLB system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.dtb.prefetch_faults 179 # Number of TLB faults due to prefetch +system.cpu.checker.dtb.prefetch_faults 180 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 14994141 # DTB read accesses -system.cpu.checker.dtb.write_accesses 11229607 # DTB write accesses +system.cpu.checker.dtb.read_accesses 14994210 # DTB read accesses +system.cpu.checker.dtb.write_accesses 11229632 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 26214250 # DTB hits +system.cpu.checker.dtb.hits 26214344 # DTB hits system.cpu.checker.dtb.misses 9498 # DTB misses -system.cpu.checker.dtb.accesses 26223748 # DTB accesses -system.cpu.checker.itb.inst_hits 61479661 # ITB inst hits +system.cpu.checker.dtb.accesses 26223842 # DTB accesses +system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.checker.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.checker.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.checker.itb.inst_hits 61480126 # ITB inst hits system.cpu.checker.itb.inst_misses 4473 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -971,43 +1018,85 @@ system.cpu.checker.itb.flush_tlb 4 # Nu system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.checker.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.checker.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.checker.itb.flush_entries 4683 # Number of entries that have been flushed from TLB +system.cpu.checker.itb.flush_entries 2372 # Number of entries that have been flushed from TLB system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 61484134 # ITB inst accesses -system.cpu.checker.itb.hits 61479661 # DTB hits +system.cpu.checker.itb.inst_accesses 61484599 # ITB inst accesses +system.cpu.checker.itb.hits 61480126 # DTB hits system.cpu.checker.itb.misses 4473 # DTB misses -system.cpu.checker.itb.accesses 61484134 # DTB accesses -system.cpu.checker.numCycles 77882476 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 61484599 # DTB accesses +system.cpu.checker.numCycles 77883033 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51182106 # DTB read hits -system.cpu.dtb.read_misses 64421 # DTB read misses -system.cpu.dtb.write_hits 11699698 # DTB write hits -system.cpu.dtb.write_misses 15824 # DTB write misses +system.cpu.dtb.read_hits 51181584 # DTB read hits +system.cpu.dtb.read_misses 65031 # DTB read misses +system.cpu.dtb.write_hits 11699885 # DTB write hits +system.cpu.dtb.write_misses 15694 # DTB write misses system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 6560 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2374 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 404 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 3476 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2524 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 396 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1314 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51246527 # DTB read accesses -system.cpu.dtb.write_accesses 11715522 # DTB write accesses +system.cpu.dtb.perms_faults 1369 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51246615 # DTB read accesses +system.cpu.dtb.write_accesses 11715579 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 62881804 # DTB hits -system.cpu.dtb.misses 80245 # DTB misses -system.cpu.dtb.accesses 62962049 # DTB accesses -system.cpu.itb.inst_hits 11522583 # ITB inst hits -system.cpu.itb.inst_misses 11276 # ITB inst misses +system.cpu.dtb.hits 62881469 # DTB hits +system.cpu.dtb.misses 80725 # DTB misses +system.cpu.dtb.accesses 62962194 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.inst_hits 11524718 # ITB inst hits +system.cpu.itb.inst_misses 11477 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -1016,114 +1105,114 @@ system.cpu.itb.flush_tlb 4 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 4956 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2510 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 3012 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2880 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 11533859 # ITB inst accesses -system.cpu.itb.hits 11522583 # DTB hits -system.cpu.itb.misses 11276 # DTB misses -system.cpu.itb.accesses 11533859 # DTB accesses -system.cpu.numCycles 474898657 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 11536195 # ITB inst accesses +system.cpu.itb.hits 11524718 # DTB hits +system.cpu.itb.misses 11477 # DTB misses +system.cpu.itb.accesses 11536195 # DTB accesses +system.cpu.numCycles 477111575 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 29752889 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 90273347 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14384927 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9059798 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 20146705 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4653497 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 122274 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 96010555 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2615 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 88482 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 2690288 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 446 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11519088 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 708911 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5337 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 152021113 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.740504 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.094585 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 29753545 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 90325732 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14756776 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9065753 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 20157040 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4656007 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 125616 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 98208682 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2521 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 87096 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 2698608 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 449 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11521342 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 709389 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5491 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 154241572 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.730167 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.081671 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 131890125 86.76% 86.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1304050 0.86% 87.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1713045 1.13% 88.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2295968 1.51% 90.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2102742 1.38% 91.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1107769 0.73% 92.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2555355 1.68% 94.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 744146 0.49% 94.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8307913 5.46% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 134100120 86.94% 86.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1306005 0.85% 87.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1712076 1.11% 88.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2296227 1.49% 90.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2110153 1.37% 91.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1105630 0.72% 92.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2555237 1.66% 94.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 745864 0.48% 94.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8310260 5.39% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 152021113 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.030291 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.190090 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 31508438 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 98138099 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18373215 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 963804 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3037557 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1957081 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 171807 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 107274658 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 567663 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3037557 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 33258738 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 39476292 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52673596 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 17529662 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6045268 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102285915 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 20597 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1004806 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4066044 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 644 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 106018919 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 466959682 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 432092489 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10446 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78387358 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27631560 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 830464 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 736820 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12181979 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 19715902 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13307123 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1978281 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2470778 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 95109477 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1982753 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 122906700 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 167286 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 18927569 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 47237054 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 500451 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 152021113 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.808484 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.527863 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 154241572 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.030929 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.189318 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31783151 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 100076545 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18079225 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1264474 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3038177 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1958594 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 172374 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 107306930 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 570435 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3038177 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 33521222 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 38625715 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 55163536 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 17589404 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6303518 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102301164 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 457 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 997569 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4061695 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 772 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 106380900 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 473930729 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 432790417 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 10427 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78723244 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 27657655 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1170957 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1077143 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12622955 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 19717794 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13303938 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1949827 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2475969 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 95121483 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1987498 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 122914150 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 166701 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 18940781 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 47245549 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 505193 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 154241572 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.796894 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.515720 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 108300469 71.24% 71.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13447891 8.85% 80.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 6945073 4.57% 84.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5857007 3.85% 88.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12370739 8.14% 96.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2808869 1.85% 98.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1695394 1.12% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 467391 0.31% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 128280 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 109895599 71.25% 71.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 14389173 9.33% 80.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 6873802 4.46% 85.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5671511 3.68% 88.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12312296 7.98% 96.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2806335 1.82% 98.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1696199 1.10% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 468469 0.30% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 128188 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 152021113 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 154241572 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 61937 0.70% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 6 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 62148 0.70% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.70% # attempts to use FU when none available @@ -1151,437 +1240,436 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8370529 94.64% 95.34% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 412377 4.66% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8367826 94.63% 95.33% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 412812 4.67% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 363666 0.30% 0.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 57620183 46.88% 47.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93128 0.08% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 24 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 6 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 20 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 20 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52507579 42.72% 89.98% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12319960 10.02% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 28518 0.02% 0.02% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 57963749 47.16% 47.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93288 0.08% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 22 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 18 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 19 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52506877 42.72% 89.98% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12319545 10.02% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 122906700 # Type of FU issued -system.cpu.iq.rate 0.258806 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8844849 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071964 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 406902990 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 116036304 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85470220 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23531 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12536 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10316 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 131375312 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12571 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 623425 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 122914150 # Type of FU issued +system.cpu.iq.rate 0.257621 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8842790 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071943 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 409136453 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 116066186 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85476047 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23300 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12528 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10301 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 131716001 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12421 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 624558 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4061911 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6363 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30197 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1575391 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4063711 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6653 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30079 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1572166 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107753 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 681273 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107729 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 680356 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3037557 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 30701555 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 434229 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 97313991 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 205819 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 19715902 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13307123 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1410230 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 113324 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3566 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30197 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 350181 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 268988 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 619169 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 120829627 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 51869148 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2077073 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3038177 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 30160267 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 434164 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 97330281 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 206491 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 19717794 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13303938 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1415153 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 113233 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3362 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30079 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 350155 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 270547 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 620702 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 120836027 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 51869099 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2078123 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 221761 # number of nop insts executed -system.cpu.iew.exec_refs 64080783 # number of memory reference insts executed -system.cpu.iew.exec_branches 11475005 # Number of branches executed -system.cpu.iew.exec_stores 12211635 # Number of stores executed -system.cpu.iew.exec_rate 0.254432 # Inst execution rate -system.cpu.iew.wb_sent 119890224 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85480536 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47031033 # num instructions producing a value -system.cpu.iew.wb_consumers 87879900 # num instructions consuming a value +system.cpu.iew.exec_nop 221300 # number of nop insts executed +system.cpu.iew.exec_refs 64080526 # number of memory reference insts executed +system.cpu.iew.exec_branches 11821026 # Number of branches executed +system.cpu.iew.exec_stores 12211427 # Number of stores executed +system.cpu.iew.exec_rate 0.253266 # Inst execution rate +system.cpu.iew.wb_sent 119895169 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85486348 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47016858 # num instructions producing a value +system.cpu.iew.wb_consumers 87565512 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.179997 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.535174 # average fanout of values written-back +system.cpu.iew.wb_rate 0.179175 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.536934 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 18664214 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1482302 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 534875 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 148983556 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.521850 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.510275 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 18677700 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1482305 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 536038 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 151203395 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.514192 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.490223 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 121547303 81.58% 81.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13306218 8.93% 90.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3902162 2.62% 93.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2119528 1.42% 94.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1937783 1.30% 95.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 976082 0.66% 96.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1595601 1.07% 97.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 718241 0.48% 98.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2880638 1.93% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 122740077 81.18% 81.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 14637973 9.68% 90.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3917047 2.59% 93.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2134429 1.41% 94.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1622101 1.07% 95.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 972992 0.64% 96.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1598831 1.06% 97.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 713641 0.47% 98.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2866304 1.90% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 148983556 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60456059 # Number of instructions committed -system.cpu.commit.committedOps 77747065 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 151203395 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60456535 # Number of instructions committed +system.cpu.commit.committedOps 77747623 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27385723 # Number of memory references committed -system.cpu.commit.loads 15653991 # Number of loads committed +system.cpu.commit.refs 27385855 # Number of memory references committed +system.cpu.commit.loads 15654083 # Number of loads committed system.cpu.commit.membars 403571 # Number of memory barriers committed -system.cpu.commit.branches 9961071 # Number of branches committed +system.cpu.commit.branches 10305769 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68852511 # Number of committed integer instructions. -system.cpu.commit.function_calls 991207 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2880638 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 69188185 # Number of committed integer instructions. +system.cpu.commit.function_calls 991209 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2866304 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 240665808 # The number of ROB reads -system.cpu.rob.rob_writes 195946920 # The number of ROB writes -system.cpu.timesIdled 1776652 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 322877544 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4575281578 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60305678 # Number of Instructions Simulated -system.cpu.committedOps 77596684 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60305678 # Number of Instructions Simulated -system.cpu.cpi 7.874858 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.874858 # CPI: Total CPI of All Threads -system.cpu.ipc 0.126986 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.126986 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 547244885 # number of integer regfile reads -system.cpu.int_regfile_writes 87532646 # number of integer regfile writes -system.cpu.fp_regfile_reads 8511 # number of floating regfile reads -system.cpu.fp_regfile_writes 2972 # number of floating regfile writes -system.cpu.misc_regfile_reads 30145050 # number of misc regfile reads -system.cpu.misc_regfile_writes 831837 # number of misc regfile writes -system.cpu.toL2Bus.throughput 58898886 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2658060 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2658059 # Transaction distribution +system.cpu.rob.rob_reads 242914035 # The number of ROB reads +system.cpu.rob.rob_writes 195975439 # The number of ROB writes +system.cpu.timesIdled 1776357 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 322870003 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4575099289 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60306154 # Number of Instructions Simulated +system.cpu.committedOps 77597242 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60306154 # Number of Instructions Simulated +system.cpu.cpi 7.911491 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.911491 # CPI: Total CPI of All Threads +system.cpu.ipc 0.126398 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.126398 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 548607877 # number of integer regfile reads +system.cpu.int_regfile_writes 87541392 # number of integer regfile writes +system.cpu.fp_regfile_reads 8324 # number of floating regfile reads +system.cpu.fp_regfile_writes 2920 # number of floating regfile writes +system.cpu.misc_regfile_reads 268241142 # number of misc regfile reads +system.cpu.misc_regfile_writes 1173227 # number of misc regfile writes +system.cpu.toL2Bus.throughput 58865094 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2658464 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2658463 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 763332 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 763332 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 607897 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2956 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 13 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2969 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 246128 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 246128 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1961789 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5796637 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30578 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 127052 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7916056 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62740736 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85535129 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 41644 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 210260 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 148527769 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 148527769 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 199672 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3129078659 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::Writeback 607582 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2966 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 12 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2978 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 246158 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 246158 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1961995 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5795878 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31363 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128647 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7917883 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62746624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85500065 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 43624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 215596 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 148505909 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 148505909 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 195968 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3128804200 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1474541718 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1474711974 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2550360089 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2550008218 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 20171491 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 20466481 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 74593037 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 74842560 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 980798 # number of replacements -system.cpu.icache.tags.tagsinuse 511.579102 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 10457750 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 981310 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 10.656928 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 6918450250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.579102 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999178 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999178 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 980909 # number of replacements +system.cpu.icache.tags.tagsinuse 511.574447 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 10459956 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 981421 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 10.657970 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 6918965000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.574447 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999169 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999169 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 225 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 150 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 221 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 155 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 12500309 # Number of tag accesses -system.cpu.icache.tags.data_accesses 12500309 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 10457750 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 10457750 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 10457750 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 10457750 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 10457750 # number of overall hits -system.cpu.icache.overall_hits::total 10457750 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1061214 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1061214 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1061214 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1061214 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1061214 # number of overall misses -system.cpu.icache.overall_misses::total 1061214 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14272429649 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14272429649 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14272429649 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14272429649 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14272429649 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14272429649 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11518964 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11518964 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11518964 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11518964 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11518964 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11518964 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092128 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.092128 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.092128 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.092128 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.092128 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.092128 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13449.153186 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13449.153186 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13449.153186 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13449.153186 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13449.153186 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13449.153186 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 5990 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 12502670 # Number of tag accesses +system.cpu.icache.tags.data_accesses 12502670 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 10459956 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 10459956 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 10459956 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 10459956 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 10459956 # number of overall hits +system.cpu.icache.overall_hits::total 10459956 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1061258 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1061258 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1061258 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1061258 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1061258 # number of overall misses +system.cpu.icache.overall_misses::total 1061258 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14277146640 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14277146640 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14277146640 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14277146640 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14277146640 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14277146640 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11521214 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11521214 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11521214 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11521214 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11521214 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11521214 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092113 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.092113 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.092113 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.092113 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.092113 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.092113 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13453.040297 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13453.040297 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13453.040297 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13453.040297 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13453.040297 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13453.040297 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 6445 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 322 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 336 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 18.602484 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 19.181548 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79868 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 79868 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 79868 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 79868 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 79868 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 79868 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 981346 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 981346 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 981346 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 981346 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 981346 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 981346 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11584683024 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11584683024 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11584683024 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11584683024 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11584683024 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11584683024 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 8658250 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 8658250 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 8658250 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 8658250 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.085194 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.085194 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.085194 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.085194 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.085194 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.085194 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11804.891469 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11804.891469 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11804.891469 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11804.891469 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11804.891469 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11804.891469 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79801 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 79801 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 79801 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 79801 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 79801 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 79801 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 981457 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 981457 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 981457 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 981457 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 981457 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 981457 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11591245017 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11591245017 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11591245017 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11591245017 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11591245017 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11591245017 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 8870000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 8870000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 8870000 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 8870000 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.085187 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.085187 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.085187 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.085187 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.085187 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.085187 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11810.242341 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11810.242341 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11810.242341 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11810.242341 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11810.242341 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11810.242341 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 64371 # number of replacements -system.cpu.l2cache.tags.tagsinuse 51362.964424 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1886397 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 129765 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 14.537025 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 2489982729000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 36926.272860 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 27.936805 # Average occupied blocks per requestor +system.cpu.l2cache.tags.replacements 64359 # number of replacements +system.cpu.l2cache.tags.tagsinuse 51360.491961 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1887854 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 129751 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 14.549822 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 2490800967500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 36938.900442 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 39.947099 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000373 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 8173.687928 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 6235.066458 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.563450 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000426 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 8146.352593 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 6235.291454 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.563643 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000610 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.124721 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.095140 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.783737 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 19 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65375 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 18 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 355 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3055 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6962 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54965 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000290 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997543 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 18784884 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 18784884 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 52523 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10409 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 967861 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 387146 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1417939 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 607897 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 607897 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 41 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 41 # number of UpgradeReq hits +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.124303 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.095143 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.783699 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 28 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 65364 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 28 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 357 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3045 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6929 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54997 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000427 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997375 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 18795937 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 18795937 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 53847 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10904 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 967954 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 386879 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1419584 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 607582 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 607582 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 43 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 43 # number of UpgradeReq hits system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 10 # number of SCUpgradeReq hits system.cpu.l2cache.SCUpgradeReq_hits::total 10 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 112916 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 112916 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 52523 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 10409 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 967861 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 500062 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1530855 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 52523 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 10409 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 967861 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 500062 # number of overall hits -system.cpu.l2cache.overall_hits::total 1530855 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 42 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_hits::cpu.data 112973 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 112973 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 53847 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 10904 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 967954 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 499852 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1532557 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 53847 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 10904 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 967954 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 499852 # number of overall hits +system.cpu.l2cache.overall_hits::total 1532557 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 52 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 12345 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 10721 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 23110 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 2915 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 2915 # number of UpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 133212 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 133212 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 42 # number of demand (read+write) misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 12341 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 10725 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 23120 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 2923 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 2923 # number of UpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 133185 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 133185 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 52 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 12345 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 143933 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 156322 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 42 # number of overall misses +system.cpu.l2cache.demand_misses::cpu.inst 12341 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 143910 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 156305 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 52 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 12345 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 143933 # number of overall misses -system.cpu.l2cache.overall_misses::total 156322 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 3605250 # number of ReadReq miss cycles +system.cpu.l2cache.overall_misses::cpu.inst 12341 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 143910 # number of overall misses +system.cpu.l2cache.overall_misses::total 156305 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 4042250 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 158000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 903018500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 812779249 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1719560999 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 510978 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 510978 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10116159486 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 10116159486 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 3605250 # number of demand (read+write) miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 908634500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 819979999 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1732814749 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 583475 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 583475 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9837869742 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 9837869742 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 4042250 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 158000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 903018500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10928938735 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 11835720485 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 3605250 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 908634500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10657849741 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 11570684491 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 4042250 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 158000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 903018500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10928938735 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 11835720485 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 52565 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10411 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 980206 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 397867 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1441049 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 607897 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 607897 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2956 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2956 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 13 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::total 13 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 246128 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 246128 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 52565 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 10411 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 980206 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 643995 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1687177 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 52565 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 10411 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 980206 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 643995 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1687177 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000799 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000192 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012594 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026946 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.016037 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986130 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986130 # miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.230769 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.230769 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541231 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.541231 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000799 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000192 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012594 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.223500 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.092653 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000799 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000192 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012594 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.223500 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.092653 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 85839.285714 # average ReadReq miss latency +system.cpu.l2cache.overall_miss_latency::cpu.inst 908634500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10657849741 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 11570684491 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 53899 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10906 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 980295 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 397604 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1442704 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 607582 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 607582 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2966 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2966 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 12 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::total 12 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 246158 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 246158 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 53899 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 10906 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 980295 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 643762 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1688862 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 53899 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 10906 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 980295 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 643762 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1688862 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000965 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000183 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012589 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026974 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.016025 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.985502 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.985502 # miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.166667 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.166667 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541055 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.541055 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000965 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000183 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012589 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.223545 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.092550 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000965 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000183 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012589 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.223545 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.092550 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 77735.576923 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 79000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73148.521669 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75811.887790 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 74407.658979 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 175.292624 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 175.292624 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75940.301820 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75940.301820 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 85839.285714 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73627.299246 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76455.011562 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 74948.734818 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 199.615121 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 199.615121 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73866.199212 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73866.199212 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 77735.576923 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 79000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73148.521669 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75930.736766 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75713.722221 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 85839.285714 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73627.299246 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74059.132381 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 74026.323477 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 77735.576923 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 79000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73148.521669 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75930.736766 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75713.722221 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73627.299246 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74059.132381 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 74026.323477 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1590,109 +1678,109 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 59131 # number of writebacks -system.cpu.l2cache.writebacks::total 59131 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 11 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 66 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 66 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 77 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 66 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 77 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 42 # number of ReadReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 59102 # number of writebacks +system.cpu.l2cache.writebacks::total 59102 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 13 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 65 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 78 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 13 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 65 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 78 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 13 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 65 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 78 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 52 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12334 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10655 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 23033 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2915 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 2915 # number of UpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133212 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 133212 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 42 # number of demand (read+write) MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12328 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10660 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 23042 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2923 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 2923 # number of UpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133185 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 133185 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 52 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 12334 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 143867 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 156245 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 42 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 12328 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 143845 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 156227 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 52 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 12334 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 143867 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 156245 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 3085750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.inst 12328 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 143845 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 156227 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 3398750 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 133500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 747187750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 675762749 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1426169749 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29153914 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29153914 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 30003 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 30003 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8455143514 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8455143514 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 3085750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 752714750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 682165499 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1438412499 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29232923 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29232923 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 20002 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 20002 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8179067758 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8179067758 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 3398750 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 133500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 747187750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9130906263 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9881313263 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 3085750 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 752714750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8861233257 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9617480257 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 3398750 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 133500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 747187750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9130906263 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9881313263 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 6187249 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166935059000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166941246249 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 17442653817 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 17442653817 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 6187249 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184377712817 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184383900066 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000799 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000192 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012583 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026780 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015983 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986130 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986130 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.230769 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.230769 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541231 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541231 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000799 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000192 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012583 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223398 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.092607 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000799 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000192 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012583 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223398 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.092607 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 73470.238095 # average ReadReq mshr miss latency +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 752714750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8861233257 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9617480257 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 6336999 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166935139250 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166941476249 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 17447345437 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 17447345437 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 6336999 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184382484687 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184388821686 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000965 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000183 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012576 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026811 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015971 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.985502 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.985502 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.166667 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.166667 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541055 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541055 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000965 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000183 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012576 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223444 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.092504 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000965 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000183 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012576 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223444 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.092504 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 65360.576923 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 66750 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60579.515972 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63422.125669 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61918.540746 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001.342710 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.342710 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61057.328845 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63993.011163 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62425.679151 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63471.335270 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63471.335270 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 73470.238095 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61411.328288 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61411.328288 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 65360.576923 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 66750 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60579.515972 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63467.690735 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63242.428641 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 73470.238095 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61057.328845 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61602.650471 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61560.935414 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 65360.576923 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 66750 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60579.515972 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63467.690735 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63242.428641 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61057.328845 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61602.650471 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61560.935414 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1702,13 +1790,13 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 643483 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.993331 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 21507621 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 643995 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 33.397186 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 42430250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.993331 # Average occupied blocks per requestor +system.cpu.dcache.tags.replacements 643250 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.993295 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 21507454 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 643762 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 33.409015 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 42602250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.993295 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999987 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -1716,154 +1804,154 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 192 system.cpu.dcache.tags.age_task_id_blocks_1024::1 302 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 101519243 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 101519243 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 13755484 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13755484 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7258628 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7258628 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 242811 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 242811 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247593 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 247593 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21014112 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21014112 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21014112 # number of overall hits -system.cpu.dcache.overall_hits::total 21014112 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 737297 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 737297 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2963410 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2963410 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13576 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13576 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 13 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 13 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3700707 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3700707 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3700707 # number of overall misses -system.cpu.dcache.overall_misses::total 3700707 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10005137822 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10005137822 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 141347559382 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 141347559382 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 185728250 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 185728250 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 206503 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 206503 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 151352697204 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 151352697204 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 151352697204 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 151352697204 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14492781 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 14492781 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10222038 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10222038 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256387 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 256387 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 101513406 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 101513406 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 13755166 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13755166 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7258873 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7258873 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 242710 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 242710 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247594 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247594 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21014039 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21014039 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21014039 # number of overall hits +system.cpu.dcache.overall_hits::total 21014039 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 736315 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 736315 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2963189 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2963189 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13552 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13552 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 12 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 12 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3699504 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3699504 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3699504 # number of overall misses +system.cpu.dcache.overall_misses::total 3699504 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10015008577 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10015008577 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 140227660304 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 140227660304 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 186052000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 186052000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 181002 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 181002 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 150242668881 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 150242668881 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 150242668881 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 150242668881 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14491481 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14491481 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10222062 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10222062 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256262 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 256262 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 247606 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 247606 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24714819 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24714819 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24714819 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24714819 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050873 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.050873 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289904 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.289904 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052951 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052951 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000053 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000053 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.149736 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.149736 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.149736 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.149736 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13570.023779 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13570.023779 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47697.604915 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 47697.604915 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13680.631261 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13680.631261 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15884.846154 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15884.846154 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 40898.319484 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 40898.319484 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 40898.319484 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 40898.319484 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 32831 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 27415 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2635 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 279 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.459583 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 98.261649 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 24713543 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24713543 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24713543 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24713543 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050810 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.050810 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289882 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.289882 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052883 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052883 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000048 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000048 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.149695 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.149695 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.149695 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.149695 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13601.527304 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13601.527304 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47323.225182 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 47323.225182 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13728.748524 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13728.748524 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15083.500000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15083.500000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 40611.570870 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 40611.570870 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 40611.570870 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 40611.570870 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 31857 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 27549 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2688 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 281 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.851562 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 98.039146 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 607897 # number of writebacks -system.cpu.dcache.writebacks::total 607897 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351582 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 351582 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714405 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2714405 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1345 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1345 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3065987 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3065987 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3065987 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3065987 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385715 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 385715 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249005 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 249005 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12231 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12231 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 13 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 13 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 634720 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 634720 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 634720 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 634720 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4972029375 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4972029375 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11600619783 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11600619783 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 146011500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 146011500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 180497 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 180497 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16572649158 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16572649158 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16572649158 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 16572649158 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182328280000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182328280000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26841536765 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26841536765 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209169816765 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 209169816765 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026614 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026614 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024360 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024360 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047705 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047705 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000053 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000053 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025682 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025682 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12890.422657 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12890.422657 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46587.898970 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46587.898970 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11937.821928 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11937.821928 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13884.384615 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13884.384615 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26110.173239 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26110.173239 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26110.173239 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26110.173239 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 607582 # number of writebacks +system.cpu.dcache.writebacks::total 607582 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 350850 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 350850 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714158 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2714158 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1320 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1320 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3065008 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3065008 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3065008 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3065008 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385465 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385465 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249031 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 249031 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12232 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12232 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 12 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 634496 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634496 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634496 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634496 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4975619608 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4975619608 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11323354786 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11323354786 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 146514250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 146514250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 156998 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 156998 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16298974394 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16298974394 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16298974394 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16298974394 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182328293250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182328293250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26845365872 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26845365872 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209173659122 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 209173659122 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026599 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026599 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024362 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024362 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047732 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047732 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000048 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000048 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025674 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025674 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025674 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025674 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12908.096995 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12908.096995 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45469.659544 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45469.659544 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11977.947188 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11977.947188 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13083.166667 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13083.166667 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25688.064848 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25688.064848 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25688.064848 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25688.064848 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1887,16 +1975,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1499067779549 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1499067779549 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1499067779549 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1499067779549 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1499072952550 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1499072952550 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1499072952550 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1499072952550 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83033 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 83032 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini index 5b8c35474..518b7284a 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini @@ -14,6 +14,7 @@ children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l atags_addr=256 boot_loader=/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain dtb_filename= @@ -22,9 +23,16 @@ enable_context_switch_stats_dump=false eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 +have_generic_timer=false +have_large_asid_64=false +have_lpae=false +have_security=false +have_virtualization=false +highest_el_is_64=false init_param=0 kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 +load_offset=0 machine_type=RealView_PBX mem_mode=timing mem_ranges=0:134217727 @@ -33,7 +41,9 @@ multi_proc=true num_work_ids=16 panic_on_oops=true panic_on_panic=true +phys_addr_range_64=40 readfile=tests/halt.sh +reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -86,7 +96,7 @@ voltage_domain=system.voltage_domain [system.cpu0] type=DerivO3CPU -children=branchPred dcache dtb fuPool icache interrupts isa itb tracer +children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb tracer LFSTSize=1024 LQEntries=32 LSQCheckLoads=true @@ -112,6 +122,7 @@ dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu0.dstage2_mmu dtb=system.cpu0.dtb eventq_index=0 fetchBufferSize=64 @@ -130,6 +141,7 @@ interrupts=system.cpu0.interrupts isa=system.cpu0.isa issueToExecuteDelay=1 issueWidth=8 +istage2_mmu=system.cpu0.istage2_mmu itb=system.cpu0.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -224,10 +236,35 @@ hit_latency=2 sequential_access=false size=32768 +[system.cpu0.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb +tlb=system.cpu0.dtb + +[system.cpu0.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu0.dstage2_mmu.stage2_tlb.walker + +[system.cpu0.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[5] + [system.cpu0.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu0.dtb.walker @@ -235,6 +272,7 @@ walker=system.cpu0.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[3] @@ -589,24 +627,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu0.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb +tlb=system.cpu0.itb + +[system.cpu0.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu0.istage2_mmu.stage2_tlb.walker + +[system.cpu0.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[4] [system.cpu0.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu0.itb.walker @@ -614,6 +688,7 @@ walker=system.cpu0.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[2] @@ -624,7 +699,7 @@ eventq_index=0 [system.cpu1] type=DerivO3CPU -children=branchPred dcache dtb fuPool icache interrupts isa itb tracer +children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb tracer LFSTSize=1024 LQEntries=32 LSQCheckLoads=true @@ -650,6 +725,7 @@ dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu1.dstage2_mmu dtb=system.cpu1.dtb eventq_index=0 fetchBufferSize=64 @@ -668,6 +744,7 @@ interrupts=system.cpu1.interrupts isa=system.cpu1.isa issueToExecuteDelay=1 issueWidth=8 +istage2_mmu=system.cpu1.istage2_mmu itb=system.cpu1.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -750,7 +827,7 @@ tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu1.dcache_port -mem_side=system.toL2Bus.slave[5] +mem_side=system.toL2Bus.slave[7] [system.cpu1.dcache.tags] type=LRU @@ -762,10 +839,35 @@ hit_latency=2 sequential_access=false size=32768 +[system.cpu1.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb +tlb=system.cpu1.dtb + +[system.cpu1.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu1.dstage2_mmu.stage2_tlb.walker + +[system.cpu1.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[11] + [system.cpu1.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu1.dtb.walker @@ -773,9 +875,10 @@ walker=system.cpu1.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[7] +port=system.toL2Bus.slave[9] [system.cpu1.fuPool] type=FUPool @@ -1107,7 +1210,7 @@ tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu1.icache_port -mem_side=system.toL2Bus.slave[4] +mem_side=system.toL2Bus.slave[6] [system.cpu1.icache.tags] type=LRU @@ -1127,24 +1230,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu1.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb +tlb=system.cpu1.itb + +[system.cpu1.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu1.istage2_mmu.stage2_tlb.walker + +[system.cpu1.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[10] [system.cpu1.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu1.itb.walker @@ -1152,9 +1291,10 @@ walker=system.cpu1.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[6] +port=system.toL2Bus.slave[8] [system.cpu1.tracer] type=ExeTracer @@ -1791,7 +1931,7 @@ system=system use_default_range=false width=8 master=system.l2c.cpu_side -slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port +slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port [system.vncserver] type=VncServer diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr index 5a43c8b18..9dee17aa2 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr @@ -10,7 +10,4 @@ warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr dccimvac' unimplemented warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented -warn: instruction 'mcr bpiallis' unimplemented warn: LCD dual screen mode not supported -warn: instruction 'mcr icialluis' unimplemented -warn: instruction 'mcr icialluis' unimplemented diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout index 8a51f6391..a00c0b470 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout @@ -1,12 +1,15 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 23 2014 00:17:38 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 18:56:34 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 + 0: system.cpu0.isa: ISA system set to: 0x6856800 0x6856800 + 0: system.cpu1.isa: ISA system set to: 0x6856800 0x6856800 info: Using bootloader at address 0x80000000 +info: Using kernel entry physical address at 0x8000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1104766159000 because m5_exit instruction encountered +Exiting @ tick 2605645191500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 3b2b0bf59..2d523b33d 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,156 +1,156 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.104766 # Number of seconds simulated -sim_ticks 1104766159000 # Number of ticks simulated -final_tick 1104766159000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.605645 # Number of seconds simulated +sim_ticks 2605645191500 # Number of ticks simulated +final_tick 2605645191500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 77156 # Simulator instruction rate (inst/s) -host_op_rate 99328 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1383749494 # Simulator tick rate (ticks/s) -host_mem_usage 406496 # Number of bytes of host memory used -host_seconds 798.39 # Real time elapsed on the host -sim_insts 61600257 # Number of instructions simulated -sim_ops 79301805 # Number of ops (including micro ops) simulated +host_inst_rate 69894 # Simulator instruction rate (inst/s) +host_op_rate 90000 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2899968268 # Simulator tick rate (ticks/s) +host_mem_usage 430484 # Number of bytes of host memory used +host_seconds 898.51 # Real time elapsed on the host +sim_insts 62800764 # Number of instructions simulated +sim_ops 80866121 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::realview.clcd 48758784 # Number of bytes read from this memory +system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 409280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4366772 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 405824 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5250416 # Number of bytes read from this memory -system.physmem.bytes_read::total 59192932 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 409280 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 405824 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 815104 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4267520 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 392704 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4367548 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 1024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 428032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5265336 # Number of bytes read from this memory +system.physmem.bytes_read::total 131566132 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 392704 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 428032 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 820736 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4282176 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7294864 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 6094848 # Number of read requests responded to by this memory +system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory +system.physmem.bytes_written::total 7311312 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 13 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6395 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 68303 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 13 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6341 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 82064 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6257980 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66680 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6136 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 68317 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 16 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6688 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 82299 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15302287 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66909 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 823516 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 44134936 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 753 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 174 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 370468 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3952666 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 753 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 367339 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4752513 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 53579603 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 370468 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 367339 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 737807 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3862827 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 15388 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2724870 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6603084 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3862827 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 44134936 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 753 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 174 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 370468 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3968054 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 753 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 367339 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 7477383 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 60182687 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 6257980 # Number of read requests accepted -system.physmem.writeReqs 823516 # Number of write requests accepted -system.physmem.readBursts 6257980 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 823516 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 398158784 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 2351936 # Total number of bytes read from write queue -system.physmem.bytesWritten 7399168 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 59192932 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7294864 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 36749 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 707898 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 12570 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 391105 # Per bank write bursts -system.physmem.perBankRdBursts::1 391040 # Per bank write bursts -system.physmem.perBankRdBursts::2 387008 # Per bank write bursts -system.physmem.perBankRdBursts::3 386856 # Per bank write bursts -system.physmem.perBankRdBursts::4 391768 # Per bank write bursts -system.physmem.perBankRdBursts::5 391357 # Per bank write bursts -system.physmem.perBankRdBursts::6 387221 # Per bank write bursts -system.physmem.perBankRdBursts::7 386642 # Per bank write bursts -system.physmem.perBankRdBursts::8 391438 # Per bank write bursts -system.physmem.perBankRdBursts::9 391160 # Per bank write bursts -system.physmem.perBankRdBursts::10 385906 # Per bank write bursts -system.physmem.perBankRdBursts::11 385319 # Per bank write bursts -system.physmem.perBankRdBursts::12 390977 # Per bank write bursts -system.physmem.perBankRdBursts::13 390642 # Per bank write bursts -system.physmem.perBankRdBursts::14 386557 # Per bank write bursts -system.physmem.perBankRdBursts::15 386235 # Per bank write bursts -system.physmem.perBankWrBursts::0 7173 # Per bank write bursts -system.physmem.perBankWrBursts::1 7194 # Per bank write bursts -system.physmem.perBankWrBursts::2 7298 # Per bank write bursts -system.physmem.perBankWrBursts::3 7217 # Per bank write bursts -system.physmem.perBankWrBursts::4 7815 # Per bank write bursts -system.physmem.perBankWrBursts::5 7451 # Per bank write bursts -system.physmem.perBankWrBursts::6 7359 # Per bank write bursts -system.physmem.perBankWrBursts::7 7185 # Per bank write bursts -system.physmem.perBankWrBursts::8 7499 # Per bank write bursts -system.physmem.perBankWrBursts::9 7507 # Per bank write bursts -system.physmem.perBankWrBursts::10 6838 # Per bank write bursts -system.physmem.perBankWrBursts::11 6616 # Per bank write bursts -system.physmem.perBankWrBursts::12 7156 # Per bank write bursts -system.physmem.perBankWrBursts::13 6834 # Per bank write bursts -system.physmem.perBankWrBursts::14 7291 # Per bank write bursts -system.physmem.perBankWrBursts::15 7179 # Per bank write bursts +system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory +system.physmem.num_writes::total 824193 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 46480054 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 319 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 150713 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1676187 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 393 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 164271 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 2020742 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50492727 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 150713 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 164271 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314984 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1643423 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6524 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 1156004 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2805951 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1643423 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 46480054 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 319 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 150713 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1682711 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 393 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 164271 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 3176746 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53298678 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15302287 # Number of read requests accepted +system.physmem.writeReqs 824193 # Number of write requests accepted +system.physmem.readBursts 15302287 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 824193 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 976879168 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 2467200 # Total number of bytes read from write queue +system.physmem.bytesWritten 7418176 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 131566132 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7311312 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 38550 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 708272 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 14191 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 956326 # Per bank write bursts +system.physmem.perBankRdBursts::1 956081 # Per bank write bursts +system.physmem.perBankRdBursts::2 952133 # Per bank write bursts +system.physmem.perBankRdBursts::3 952389 # Per bank write bursts +system.physmem.perBankRdBursts::4 956868 # Per bank write bursts +system.physmem.perBankRdBursts::5 956262 # Per bank write bursts +system.physmem.perBankRdBursts::6 951633 # Per bank write bursts +system.physmem.perBankRdBursts::7 951532 # Per bank write bursts +system.physmem.perBankRdBursts::8 956738 # Per bank write bursts +system.physmem.perBankRdBursts::9 956585 # Per bank write bursts +system.physmem.perBankRdBursts::10 951315 # Per bank write bursts +system.physmem.perBankRdBursts::11 950633 # Per bank write bursts +system.physmem.perBankRdBursts::12 956323 # Per bank write bursts +system.physmem.perBankRdBursts::13 956319 # Per bank write bursts +system.physmem.perBankRdBursts::14 951484 # Per bank write bursts +system.physmem.perBankRdBursts::15 951116 # Per bank write bursts +system.physmem.perBankWrBursts::0 7149 # Per bank write bursts +system.physmem.perBankWrBursts::1 7007 # Per bank write bursts +system.physmem.perBankWrBursts::2 7292 # Per bank write bursts +system.physmem.perBankWrBursts::3 7274 # Per bank write bursts +system.physmem.perBankWrBursts::4 7928 # Per bank write bursts +system.physmem.perBankWrBursts::5 7489 # Per bank write bursts +system.physmem.perBankWrBursts::6 7090 # Per bank write bursts +system.physmem.perBankWrBursts::7 7095 # Per bank write bursts +system.physmem.perBankWrBursts::8 7536 # Per bank write bursts +system.physmem.perBankWrBursts::9 7648 # Per bank write bursts +system.physmem.perBankWrBursts::10 6979 # Per bank write bursts +system.physmem.perBankWrBursts::11 6633 # Per bank write bursts +system.physmem.perBankWrBursts::12 7251 # Per bank write bursts +system.physmem.perBankWrBursts::13 7189 # Per bank write bursts +system.physmem.perBankWrBursts::14 7290 # Per bank write bursts +system.physmem.perBankWrBursts::15 7059 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1104765054500 # Total gap between requests +system.physmem.totGap 2605643958000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 105 # Read request sizes (log2) -system.physmem.readPktSize::3 6094848 # Read request sizes (log2) +system.physmem.readPktSize::2 109 # Read request sizes (log2) +system.physmem.readPktSize::3 15138816 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 163027 # Read request sizes (log2) +system.physmem.readPktSize::6 163362 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 756836 # Write request sizes (log2) +system.physmem.writePktSize::2 757284 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66680 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 551365 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 495534 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 447275 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1468617 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1056766 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1046048 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1041328 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 24902 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 24744 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 9802 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 9495 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 9368 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 9115 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 8928 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 8808 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 8712 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 281 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 115 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 11 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66909 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1182621 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1128295 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1080999 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3674790 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2650191 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2638240 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2645126 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 56320 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 60148 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 21515 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 21310 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 21179 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 20896 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 20716 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 20584 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 20486 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 211 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 98 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -161,579 +161,620 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 5114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5795 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 5243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5438 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5570 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 5125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 5252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5476 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5561 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5253 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5193 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 5180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5519 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5585 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 70891 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 5720.862056 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 370.371771 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 12983.455583 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-71 25780 36.37% 36.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-135 14831 20.92% 57.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-199 3170 4.47% 61.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-263 2175 3.07% 64.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-327 1493 2.11% 66.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-391 1297 1.83% 68.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-455 1053 1.49% 70.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-519 1149 1.62% 71.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-583 657 0.93% 72.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-647 651 0.92% 73.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-711 556 0.78% 74.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-775 523 0.74% 75.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-839 304 0.43% 75.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-903 266 0.38% 76.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-967 142 0.20% 76.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1031 425 0.60% 76.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1095 119 0.17% 77.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1159 139 0.20% 77.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1223 90 0.13% 77.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1287 153 0.22% 77.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1351 51 0.07% 77.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1415 550 0.78% 78.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1479 38 0.05% 78.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1543 222 0.31% 78.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1607 29 0.04% 78.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1671 108 0.15% 78.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1735 16 0.02% 78.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1799 111 0.16% 79.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1863 28 0.04% 79.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1927 57 0.08% 79.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1991 19 0.03% 79.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2055 237 0.33% 79.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2119 12 0.02% 79.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2183 45 0.06% 79.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2247 10 0.01% 79.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2311 54 0.08% 79.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2375 16 0.02% 79.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2439 29 0.04% 79.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2503 2 0.00% 79.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2567 27 0.04% 79.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2631 2 0.00% 79.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2695 17 0.02% 79.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2759 5 0.01% 79.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2823 28 0.04% 79.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2887 7 0.01% 79.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2951 22 0.03% 80.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3015 5 0.01% 80.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3079 178 0.25% 80.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3143 2 0.00% 80.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3207 13 0.02% 80.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3271 3 0.00% 80.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3335 91 0.13% 80.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3399 6 0.01% 80.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3463 20 0.03% 80.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3527 6 0.01% 80.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3591 46 0.06% 80.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3655 11 0.02% 80.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3719 27 0.04% 80.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3783 5 0.01% 80.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3847 37 0.05% 80.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3911 12 0.02% 80.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3975 18 0.03% 80.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4039 12 0.02% 80.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4103 201 0.28% 80.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4167 6 0.01% 80.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4231 17 0.02% 81.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4295 8 0.01% 81.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4359 92 0.13% 81.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4423 19 0.03% 81.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4487 20 0.03% 81.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4551 13 0.02% 81.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4615 19 0.03% 81.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4679 2 0.00% 81.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4743 6 0.01% 81.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4807 10 0.01% 81.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4871 20 0.03% 81.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4935 4 0.01% 81.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4999 13 0.02% 81.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5063 3 0.00% 81.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5127 93 0.13% 81.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5191 4 0.01% 81.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5255 15 0.02% 81.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5319 8 0.01% 81.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5383 84 0.12% 81.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5447 5 0.01% 81.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5511 9 0.01% 81.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5575 5 0.01% 81.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5639 19 0.03% 81.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5703 2 0.00% 81.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5767 7 0.01% 81.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5831 2 0.00% 81.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5895 138 0.19% 81.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5959 4 0.01% 81.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6023 11 0.02% 81.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6087 12 0.02% 81.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6151 85 0.12% 82.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6215 8 0.01% 82.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6279 6 0.01% 82.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6343 5 0.01% 82.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6407 96 0.14% 82.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6471 4 0.01% 82.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6535 12 0.02% 82.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6599 4 0.01% 82.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6663 80 0.11% 82.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6727 5 0.01% 82.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6791 21 0.03% 82.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6855 6 0.01% 82.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6919 25 0.04% 82.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6983 5 0.01% 82.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7047 3 0.00% 82.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7111 5 0.01% 82.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7175 24 0.03% 82.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7303 4 0.01% 82.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7367 11 0.02% 82.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7431 94 0.13% 82.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7495 1 0.00% 82.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7559 12 0.02% 82.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7623 4 0.01% 82.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7687 79 0.11% 82.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7751 3 0.00% 82.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7815 3 0.00% 82.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7879 2 0.00% 82.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7943 32 0.05% 82.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8007 4 0.01% 82.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8071 8 0.01% 82.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8199 266 0.38% 83.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8320-8327 2 0.00% 83.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8384-8391 1 0.00% 83.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8455 25 0.04% 83.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8711 67 0.09% 83.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8768-8775 3 0.00% 83.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8832-8839 1 0.00% 83.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8967 85 0.12% 83.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9152-9159 1 0.00% 83.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9223 19 0.03% 83.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9280-9287 1 0.00% 83.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9344-9351 1 0.00% 83.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9479 13 0.02% 83.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9536-9543 1 0.00% 83.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9735 69 0.10% 83.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9792-9799 1 0.00% 83.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9856-9863 2 0.00% 83.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9920-9927 1 0.00% 83.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9991 92 0.13% 83.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10176-10183 1 0.00% 83.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10247 80 0.11% 83.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10503 87 0.12% 84.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10560-10567 1 0.00% 84.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10624-10631 2 0.00% 84.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10688-10695 1 0.00% 84.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10759 16 0.02% 84.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11015 75 0.11% 84.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11136-11143 1 0.00% 84.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11271 80 0.11% 84.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11328-11335 2 0.00% 84.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11392-11399 1 0.00% 84.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11456-11463 1 0.00% 84.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11527 15 0.02% 84.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11783 10 0.01% 84.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12039 70 0.10% 84.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12096-12103 1 0.00% 84.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12160-12167 1 0.00% 84.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12224-12231 1 0.00% 84.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12295 175 0.25% 84.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12352-12359 1 0.00% 84.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12551 22 0.03% 84.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12672-12679 1 0.00% 84.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12807 37 0.05% 84.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12992-12999 1 0.00% 84.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13063 80 0.11% 84.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13184-13191 1 0.00% 84.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13319 161 0.23% 85.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13575 8 0.01% 85.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13696-13703 1 0.00% 85.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13831 12 0.02% 85.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13888-13895 2 0.00% 85.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13952-13959 2 0.00% 85.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14087 25 0.04% 85.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14144-14151 1 0.00% 85.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14215 1 0.00% 85.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14343 180 0.25% 85.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14400-14407 1 0.00% 85.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14528-14535 1 0.00% 85.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14599 23 0.03% 85.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14656-14663 1 0.00% 85.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14855 2 0.00% 85.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14976-14983 1 0.00% 85.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15040-15047 1 0.00% 85.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15111 22 0.03% 85.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15232-15239 1 0.00% 85.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15367 213 0.30% 85.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15552-15559 1 0.00% 85.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15623 15 0.02% 85.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15680-15687 2 0.00% 85.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15879 5 0.01% 85.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15936-15943 1 0.00% 85.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16000-16007 1 0.00% 85.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16135 4 0.01% 85.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16192-16199 3 0.00% 85.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16320-16327 1 0.00% 85.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16391 278 0.39% 86.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16576-16583 1 0.00% 86.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16647 6 0.01% 86.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16903 6 0.01% 86.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17159 16 0.02% 86.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17216-17223 2 0.00% 86.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17280-17287 4 0.01% 86.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17415 216 0.30% 86.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17600-17607 4 0.01% 86.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17671 28 0.04% 86.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17927 6 0.01% 86.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18112-18119 2 0.00% 86.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18183 20 0.03% 86.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18240-18247 1 0.00% 86.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18439 175 0.25% 86.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18560-18567 1 0.00% 86.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18695 21 0.03% 86.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18752-18759 2 0.00% 86.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18944-18951 11 0.02% 86.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19072-19079 1 0.00% 86.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19207 12 0.02% 86.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19328-19335 2 0.00% 86.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19392-19399 2 0.00% 86.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19463 153 0.22% 87.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19584-19591 1 0.00% 87.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19648-19655 2 0.00% 87.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19719 76 0.11% 87.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19776-19783 4 0.01% 87.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19840-19847 1 0.00% 87.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19904-19911 1 0.00% 87.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19968-19975 33 0.05% 87.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20231 20 0.03% 87.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20288-20295 1 0.00% 87.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20352-20359 1 0.00% 87.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20416-20423 1 0.00% 87.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20487 171 0.24% 87.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20608-20615 1 0.00% 87.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20736-20743 75 0.11% 87.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20928-20935 1 0.00% 87.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-20999 12 0.02% 87.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21056-21063 1 0.00% 87.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21248-21255 17 0.02% 87.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21376-21383 3 0.00% 87.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21511 73 0.10% 87.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21568-21575 1 0.00% 87.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21632-21639 1 0.00% 87.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21696-21703 1 0.00% 87.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21767 72 0.10% 87.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21824-21831 2 0.00% 87.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21888-21895 1 0.00% 87.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22023 12 0.02% 88.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22080-22087 1 0.00% 88.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22144-22151 1 0.00% 88.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22208-22215 2 0.00% 88.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22279 88 0.12% 88.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22464-22471 2 0.00% 88.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22535 73 0.10% 88.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22656-22663 3 0.00% 88.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22791 94 0.13% 88.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22848-22855 1 0.00% 88.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23040-23047 67 0.09% 88.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23168-23175 1 0.00% 88.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23296-23303 10 0.01% 88.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23360-23367 1 0.00% 88.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23424-23431 1 0.00% 88.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23488-23495 1 0.00% 88.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23559 18 0.03% 88.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23680-23687 2 0.00% 88.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23744-23751 1 0.00% 88.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23808-23815 82 0.12% 88.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24071 73 0.10% 88.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24327 24 0.03% 88.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24448-24455 1 0.00% 88.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24512-24519 1 0.00% 88.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24583 150 0.21% 88.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24704-24711 1 0.00% 89.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24768-24775 1 0.00% 89.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24839 25 0.04% 89.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24960-24967 1 0.00% 89.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25088-25095 68 0.10% 89.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25344-25351 86 0.12% 89.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25536-25543 1 0.00% 89.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25607 20 0.03% 89.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25792-25799 1 0.00% 89.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25856-25863 14 0.02% 89.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25984-25991 3 0.00% 89.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26048-26055 1 0.00% 89.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26112-26119 69 0.10% 89.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26176-26183 2 0.00% 89.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26240-26247 2 0.00% 89.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26304-26311 2 0.00% 89.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26375 93 0.13% 89.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26432-26439 1 0.00% 89.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26496-26503 2 0.00% 89.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26631 75 0.11% 89.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26688-26695 1 0.00% 89.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26880-26887 84 0.12% 89.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27072-27079 1 0.00% 89.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27143 14 0.02% 89.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27264-27271 1 0.00% 89.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27328-27335 2 0.00% 89.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27399 75 0.11% 89.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27584-27591 1 0.00% 89.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27655 77 0.11% 90.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27712-27719 1 0.00% 90.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27840-27847 1 0.00% 90.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27911 16 0.02% 90.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28032-28039 1 0.00% 90.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28096-28103 1 0.00% 90.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28160-28167 8 0.01% 90.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28224-28231 2 0.00% 90.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28288-28295 1 0.00% 90.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28423 75 0.11% 90.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28480-28487 1 0.00% 90.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28608-28615 1 0.00% 90.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28679 176 0.25% 90.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28736-28743 1 0.00% 90.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28935 20 0.03% 90.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28992-28999 1 0.00% 90.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29056-29063 2 0.00% 90.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29120-29127 1 0.00% 90.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29191 31 0.04% 90.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29248-29255 1 0.00% 90.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29312-29319 2 0.00% 90.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29376-29383 3 0.00% 90.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29447 76 0.11% 90.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29568-29575 1 0.00% 90.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29703 149 0.21% 90.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29824-29831 1 0.00% 90.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29888-29895 1 0.00% 90.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-29959 13 0.02% 90.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30080-30087 2 0.00% 90.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30208-30215 7 0.01% 90.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30272-30279 1 0.00% 90.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30471 23 0.03% 90.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30528-30535 2 0.00% 90.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30592-30599 1 0.00% 90.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30656-30663 1 0.00% 90.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30727 175 0.25% 91.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30784-30791 2 0.00% 91.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30912-30919 6 0.01% 91.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-30983 19 0.03% 91.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31168-31175 1 0.00% 91.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31239 4 0.01% 91.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31360-31367 1 0.00% 91.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31488-31495 24 0.03% 91.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31616-31623 2 0.00% 91.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31680-31687 1 0.00% 91.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31751 210 0.30% 91.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31808-31815 1 0.00% 91.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31872-31879 1 0.00% 91.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31936-31943 1 0.00% 91.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32000-32007 12 0.02% 91.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32256-32263 5 0.01% 91.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32384-32391 1 0.00% 91.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32512-32519 5 0.01% 91.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32704-32711 2 0.00% 91.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32775 275 0.39% 91.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33031 4 0.01% 91.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33152-33159 1 0.00% 91.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33287 5 0.01% 91.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33408-33415 1 0.00% 91.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33472-33479 1 0.00% 91.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33543 21 0.03% 92.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33600-33607 1 0.00% 92.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33664-33671 4 0.01% 92.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33799 214 0.30% 92.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33920-33927 1 0.00% 92.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33984-33991 1 0.00% 92.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34048-34055 20 0.03% 92.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34176-34183 1 0.00% 92.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34304-34311 2 0.00% 92.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34560-34567 21 0.03% 92.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34823 167 0.24% 92.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35072-35079 18 0.03% 92.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35200-35207 1 0.00% 92.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35328-35335 7 0.01% 92.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35456-35463 1 0.00% 92.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35520-35527 1 0.00% 92.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35584-35591 13 0.02% 92.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35648-35655 1 0.00% 92.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35712-35719 1 0.00% 92.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35847 147 0.21% 92.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35968-35975 1 0.00% 92.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36032-36039 1 0.00% 92.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36096-36103 73 0.10% 92.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36160-36167 1 0.00% 92.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36224-36231 1 0.00% 92.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36352-36359 29 0.04% 93.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36416-36423 1 0.00% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36480-36487 1 0.00% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36608-36615 20 0.03% 93.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36800-36807 1 0.00% 93.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36864-36871 174 0.25% 93.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37120-37127 72 0.10% 93.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37376-37383 7 0.01% 93.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37632-37639 17 0.02% 93.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37696-37703 2 0.00% 93.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37895 76 0.11% 93.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38144-38151 72 0.10% 93.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38336-38343 1 0.00% 93.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38400-38407 12 0.02% 93.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38592-38599 1 0.00% 93.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38656-38663 83 0.12% 93.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38912-38919 77 0.11% 93.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39040-39047 2 0.00% 93.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39168-39175 93 0.13% 94.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39360-39367 1 0.00% 94.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39424-39431 65 0.09% 94.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39552-39559 1 0.00% 94.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39680-39687 10 0.01% 94.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39936-39943 17 0.02% 94.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40000-40007 2 0.00% 94.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40128-40135 1 0.00% 94.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40192-40199 82 0.12% 94.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40256-40263 1 0.00% 94.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40448-40455 67 0.09% 94.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40640-40647 1 0.00% 94.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40704-40711 23 0.03% 94.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40896-40903 1 0.00% 94.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40960-40967 150 0.21% 94.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41024-41031 1 0.00% 94.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41088-41095 1 0.00% 94.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41216-41223 23 0.03% 94.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41280-41287 1 0.00% 94.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41344-41351 2 0.00% 94.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41472-41479 70 0.10% 94.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41536-41543 1 0.00% 94.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41664-41671 1 0.00% 94.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41728-41735 82 0.12% 94.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41792-41799 1 0.00% 94.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-41991 16 0.02% 94.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42240-42247 13 0.02% 94.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42368-42375 1 0.00% 94.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42496-42503 66 0.09% 95.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42688-42695 1 0.00% 95.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42752-42759 92 0.13% 95.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42816-42823 1 0.00% 95.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42944-42951 1 0.00% 95.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43008-43015 75 0.11% 95.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43264-43271 86 0.12% 95.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43520-43527 12 0.02% 95.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43648-43655 2 0.00% 95.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43776-43783 74 0.10% 95.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43904-43911 2 0.00% 95.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44032-44039 73 0.10% 95.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44160-44167 3 0.00% 95.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44224-44231 1 0.00% 95.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44288-44295 16 0.02% 95.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44544-44551 9 0.01% 95.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44608-44615 2 0.00% 95.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44800-44807 74 0.10% 95.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44928-44935 4 0.01% 95.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45056-45063 173 0.24% 96.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45120-45127 1 0.00% 96.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45248-45255 1 0.00% 96.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45312-45319 19 0.03% 96.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45504-45511 1 0.00% 96.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45568-45575 34 0.05% 96.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45696-45703 2 0.00% 96.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45824-45831 76 0.11% 96.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46087 150 0.21% 96.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46144-46151 1 0.00% 96.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46208-46215 1 0.00% 96.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46336-46343 8 0.01% 96.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46528-46535 1 0.00% 96.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46592-46599 9 0.01% 96.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46848-46855 17 0.02% 96.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46912-46919 1 0.00% 96.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47104-47111 174 0.25% 96.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47360-47367 22 0.03% 96.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47424-47431 1 0.00% 96.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47488-47495 1 0.00% 96.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47616-47623 2 0.00% 96.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47744-47751 3 0.00% 96.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47872-47879 21 0.03% 96.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48135 208 0.29% 97.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48192-48199 1 0.00% 97.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48384-48391 12 0.02% 97.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48640-48647 4 0.01% 97.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48768-48775 10 0.01% 97.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48903 4 0.01% 97.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48960-48967 3 0.00% 97.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49024-49031 3 0.00% 97.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49088-49095 3 0.00% 97.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49159 2000 2.82% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49216-49223 1 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49280-49287 1 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49664-49671 2 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49728-49735 1 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49920-49927 1 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50048-50055 2 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50176-50183 2 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50304-50311 1 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50368-50375 1 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50496-50503 2 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50624-50631 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50688-50695 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50752-50759 2 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50944-50951 2 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51008-51015 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51328-51335 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51456-51463 4 0.01% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51520-51527 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51584-51591 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51648-51655 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 91629 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 10742.195593 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 915.011801 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 16529.689653 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 25868 28.23% 28.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 14885 16.24% 44.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 3175 3.47% 47.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 2307 2.52% 50.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 1552 1.69% 52.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 1265 1.38% 53.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 967 1.06% 54.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 1319 1.44% 56.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 664 0.72% 56.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 632 0.69% 57.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 552 0.60% 58.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-775 612 0.67% 58.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-839 295 0.32% 59.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-903 299 0.33% 59.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 170 0.19% 59.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 591 0.64% 60.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 145 0.16% 60.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1159 120 0.13% 60.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1223 94 0.10% 60.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1287 139 0.15% 60.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1351 69 0.08% 60.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1415 555 0.61% 61.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1479 36 0.04% 61.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1543 297 0.32% 61.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1607 26 0.03% 61.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1671 93 0.10% 61.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1735 18 0.02% 61.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1799 171 0.19% 62.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1863 18 0.02% 62.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1927 53 0.06% 62.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1991 22 0.02% 62.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2055 386 0.42% 62.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2119 9 0.01% 62.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2183 41 0.04% 62.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2247 10 0.01% 62.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2311 62 0.07% 62.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2375 6 0.01% 62.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2439 32 0.03% 62.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2503 10 0.01% 62.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2567 171 0.19% 63.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2631 4 0.00% 63.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2695 16 0.02% 63.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2759 7 0.01% 63.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2823 87 0.09% 63.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2887 9 0.01% 63.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2951 23 0.03% 63.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3015 8 0.01% 63.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3079 355 0.39% 63.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3143 3 0.00% 63.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3207 16 0.02% 63.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3271 6 0.01% 63.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3335 101 0.11% 63.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3399 10 0.01% 63.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3463 14 0.02% 63.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3527 7 0.01% 63.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3591 93 0.10% 63.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3655 11 0.01% 63.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3719 22 0.02% 63.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3783 7 0.01% 63.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3847 109 0.12% 64.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3911 11 0.01% 64.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3975 14 0.02% 64.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4039 9 0.01% 64.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4103 384 0.42% 64.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4167 10 0.01% 64.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4231 16 0.02% 64.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4295 6 0.01% 64.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4359 99 0.11% 64.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4423 15 0.02% 64.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4487 11 0.01% 64.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4551 7 0.01% 64.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4615 45 0.05% 64.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4679 4 0.00% 64.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4743 10 0.01% 64.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4807 11 0.01% 64.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4871 152 0.17% 64.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4935 9 0.01% 64.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4999 16 0.02% 64.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5063 3 0.00% 64.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5127 484 0.53% 65.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5191 5 0.01% 65.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5255 12 0.01% 65.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5319 8 0.01% 65.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5383 12 0.01% 65.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5447 6 0.01% 65.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5511 6 0.01% 65.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5575 3 0.00% 65.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5639 100 0.11% 65.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5703 6 0.01% 65.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5767 10 0.01% 65.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5831 6 0.01% 65.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5895 142 0.15% 65.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5959 4 0.00% 65.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6023 15 0.02% 65.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6087 4 0.00% 65.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6151 300 0.33% 66.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6215 4 0.00% 66.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6279 14 0.02% 66.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6343 2 0.00% 66.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6407 89 0.10% 66.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6471 2 0.00% 66.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6535 8 0.01% 66.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6599 1 0.00% 66.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6663 160 0.17% 66.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6727 7 0.01% 66.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6791 20 0.02% 66.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6855 7 0.01% 66.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6919 31 0.03% 66.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6983 3 0.00% 66.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7047 11 0.01% 66.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7111 4 0.00% 66.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7175 463 0.51% 67.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7239 3 0.00% 67.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7303 5 0.01% 67.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7367 6 0.01% 67.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7431 163 0.18% 67.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7495 4 0.00% 67.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7559 11 0.01% 67.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7623 5 0.01% 67.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7687 15 0.02% 67.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7751 1 0.00% 67.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7815 2 0.00% 67.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7879 1 0.00% 67.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7943 91 0.10% 67.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8007 6 0.01% 67.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8071 9 0.01% 67.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8135 1 0.00% 67.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8199 397 0.43% 67.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8320-8327 1 0.00% 67.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8384-8391 1 0.00% 67.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8455 85 0.09% 67.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8512-8519 1 0.00% 67.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8576-8583 2 0.00% 67.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8711 6 0.01% 67.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8768-8775 1 0.00% 67.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8832-8839 2 0.00% 67.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8967 154 0.17% 68.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9088-9095 3 0.00% 68.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9152-9159 1 0.00% 68.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9223 460 0.50% 68.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9479 24 0.03% 68.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9536-9543 1 0.00% 68.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9600-9607 5 0.01% 68.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9735 143 0.16% 68.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9792-9799 1 0.00% 68.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9856-9863 1 0.00% 68.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9920-9927 1 0.00% 68.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9991 82 0.09% 68.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10112-10119 1 0.00% 68.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10247 282 0.31% 69.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10304-10311 1 0.00% 69.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10432-10439 1 0.00% 69.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10503 93 0.10% 69.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10560-10567 2 0.00% 69.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10624-10631 1 0.00% 69.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10688-10695 2 0.00% 69.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10759 93 0.10% 69.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10816-10823 1 0.00% 69.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11015 7 0.01% 69.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11136-11143 2 0.00% 69.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11200-11207 1 0.00% 69.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11271 476 0.52% 69.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11328-11335 1 0.00% 69.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11392-11399 1 0.00% 69.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11527 141 0.15% 70.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11584-11591 2 0.00% 70.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11648-11655 1 0.00% 70.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11783 20 0.02% 70.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11904-11911 2 0.00% 70.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12039 75 0.08% 70.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12160-12167 1 0.00% 70.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12224-12231 1 0.00% 70.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12295 353 0.39% 70.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12352-12359 1 0.00% 70.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12416-12423 1 0.00% 70.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12551 89 0.10% 70.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12672-12679 1 0.00% 70.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12736-12743 1 0.00% 70.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12807 73 0.08% 70.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12992-12999 2 0.00% 70.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13063 85 0.09% 70.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13120-13127 1 0.00% 70.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13184-13191 4 0.00% 70.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13248-13255 1 0.00% 70.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13319 331 0.36% 71.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13575 70 0.08% 71.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13696-13703 2 0.00% 71.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13831 145 0.16% 71.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13952-13959 2 0.00% 71.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14087 17 0.02% 71.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14215 2 0.00% 71.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14272-14279 1 0.00% 71.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14343 336 0.37% 71.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14464-14471 4 0.00% 71.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14599 80 0.09% 71.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14656-14663 1 0.00% 71.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14855 83 0.09% 72.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15111 18 0.02% 72.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15175 2 0.00% 72.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15239 1 0.00% 72.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15296-15303 1 0.00% 72.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15367 400 0.44% 72.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15488-15495 1 0.00% 72.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15623 77 0.08% 72.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15808-15815 1 0.00% 72.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15879 147 0.16% 72.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15936-15943 1 0.00% 72.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16000-16007 3 0.00% 72.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16135 74 0.08% 72.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16256-16263 4 0.00% 72.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16391 514 0.56% 73.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16512-16519 1 0.00% 73.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16647 75 0.08% 73.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16704-16711 1 0.00% 73.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16896-16903 140 0.15% 73.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17024-17031 1 0.00% 73.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17159 75 0.08% 73.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17280-17287 3 0.00% 73.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17344-17351 1 0.00% 73.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17415 397 0.43% 74.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17472-17479 1 0.00% 74.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17536-17543 1 0.00% 74.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17671 22 0.02% 74.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17728-17735 2 0.00% 74.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17927 82 0.09% 74.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18048-18055 3 0.00% 74.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18112-18119 2 0.00% 74.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18183 77 0.08% 74.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18240-18247 1 0.00% 74.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18304-18311 4 0.00% 74.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18368-18375 1 0.00% 74.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18439 337 0.37% 74.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18496-18503 1 0.00% 74.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18688-18695 20 0.02% 74.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18752-18759 1 0.00% 74.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18816-18823 2 0.00% 74.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18944-18951 146 0.16% 74.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19072-19079 1 0.00% 74.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19136-19143 1 0.00% 74.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19207 69 0.08% 75.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19328-19335 4 0.00% 75.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19392-19399 2 0.00% 75.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19463 330 0.36% 75.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19520-19527 1 0.00% 75.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19712-19719 82 0.09% 75.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19968-19975 77 0.08% 75.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20160-20167 1 0.00% 75.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20224-20231 92 0.10% 75.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20352-20359 2 0.00% 75.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20416-20423 1 0.00% 75.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20487 348 0.38% 76.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20544-20551 1 0.00% 76.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20608-20615 3 0.00% 76.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20672-20679 1 0.00% 76.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20736-20743 78 0.09% 76.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20992-20999 26 0.03% 76.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21120-21127 1 0.00% 76.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21184-21191 1 0.00% 76.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21248-21255 140 0.15% 76.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21312-21319 1 0.00% 76.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21376-21383 3 0.00% 76.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21440-21447 2 0.00% 76.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21511 469 0.51% 76.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21760-21767 6 0.01% 76.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21888-21895 1 0.00% 76.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22016-22023 94 0.10% 76.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22144-22151 1 0.00% 76.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22208-22215 4 0.00% 76.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22272-22279 92 0.10% 77.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22400-22407 3 0.00% 77.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22464-22471 1 0.00% 77.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22535 276 0.30% 77.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22592-22599 1 0.00% 77.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22656-22663 1 0.00% 77.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22784-22791 77 0.08% 77.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22912-22919 2 0.00% 77.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22976-22983 1 0.00% 77.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23040-23047 140 0.15% 77.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23168-23175 1 0.00% 77.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23232-23239 1 0.00% 77.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23296-23303 28 0.03% 77.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23360-23367 1 0.00% 77.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23424-23431 2 0.00% 77.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23559 459 0.50% 78.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23680-23687 3 0.00% 78.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23808-23815 146 0.16% 78.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23872-23879 1 0.00% 78.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23936-23943 1 0.00% 78.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24064-24071 7 0.01% 78.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24128-24135 1 0.00% 78.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24192-24199 1 0.00% 78.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24327 88 0.10% 78.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24384-24391 1 0.00% 78.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24448-24455 5 0.01% 78.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24512-24519 2 0.00% 78.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24583 281 0.31% 78.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24640-24647 1 0.00% 78.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24832-24839 86 0.09% 78.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24896-24903 1 0.00% 78.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25088-25095 6 0.01% 78.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25344-25351 153 0.17% 78.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25472-25479 4 0.00% 78.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25536-25543 1 0.00% 78.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25607 454 0.50% 79.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25792-25799 1 0.00% 79.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25856-25863 26 0.03% 79.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25984-25991 1 0.00% 79.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26112-26119 144 0.16% 79.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26240-26247 3 0.00% 79.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26375 79 0.09% 79.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26432-26439 2 0.00% 79.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26496-26503 5 0.01% 79.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26631 276 0.30% 80.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26752-26759 1 0.00% 80.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26816-26823 2 0.00% 80.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26880-26887 94 0.10% 80.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26944-26951 1 0.00% 80.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27008-27015 2 0.00% 80.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27072-27079 1 0.00% 80.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27136-27143 92 0.10% 80.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27200-27207 1 0.00% 80.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27264-27271 1 0.00% 80.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27399 9 0.01% 80.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27456-27463 1 0.00% 80.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27520-27527 4 0.00% 80.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27655 472 0.52% 80.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27712-27719 2 0.00% 80.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27776-27783 2 0.00% 80.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27911 140 0.15% 80.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27968-27975 1 0.00% 80.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28160-28167 21 0.02% 80.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28224-28231 2 0.00% 80.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28288-28295 2 0.00% 81.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28423 78 0.09% 81.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28480-28487 2 0.00% 81.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28544-28551 4 0.00% 81.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28679 344 0.38% 81.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28736-28743 1 0.00% 81.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28800-28807 2 0.00% 81.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28864-28871 1 0.00% 81.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28935 87 0.09% 81.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28992-28999 1 0.00% 81.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29191 75 0.08% 81.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29312-29319 2 0.00% 81.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29376-29383 2 0.00% 81.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29447 81 0.09% 81.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29504-29511 1 0.00% 81.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29568-29575 2 0.00% 81.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29632-29639 2 0.00% 81.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29703 325 0.35% 82.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29760-29767 3 0.00% 82.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29824-29831 2 0.00% 82.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-29959 72 0.08% 82.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30016-30023 2 0.00% 82.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30080-30087 2 0.00% 82.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30144-30151 3 0.00% 82.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30215 142 0.15% 82.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30272-30279 1 0.00% 82.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30336-30343 1 0.00% 82.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30471 20 0.02% 82.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30528-30535 1 0.00% 82.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30592-30599 3 0.00% 82.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30656-30663 1 0.00% 82.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30727 331 0.36% 82.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30848-30855 1 0.00% 82.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-30983 75 0.08% 82.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31040-31047 2 0.00% 82.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31104-31111 4 0.00% 82.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31168-31175 2 0.00% 82.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31239 80 0.09% 82.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31360-31367 2 0.00% 82.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31495 17 0.02% 82.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31616-31623 2 0.00% 82.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31680-31687 3 0.00% 82.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31751 402 0.44% 83.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32007 74 0.08% 83.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32128-32135 2 0.00% 83.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32263 141 0.15% 83.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32384-32391 1 0.00% 83.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32519 73 0.08% 83.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32640-32647 1 0.00% 83.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32775 516 0.56% 84.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32896-32903 3 0.00% 84.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33031 69 0.08% 84.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33088-33095 1 0.00% 84.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33287 142 0.15% 84.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33408-33415 2 0.00% 84.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33543 81 0.09% 84.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33664-33671 2 0.00% 84.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33799 419 0.46% 85.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33856-33863 1 0.00% 85.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33920-33927 2 0.00% 85.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34048-34055 17 0.02% 85.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34176-34183 1 0.00% 85.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34304-34311 80 0.09% 85.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34368-34375 1 0.00% 85.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34432-34439 2 0.00% 85.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34496-34503 1 0.00% 85.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34560-34567 75 0.08% 85.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34823 329 0.36% 85.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34944-34951 2 0.00% 85.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35072-35079 20 0.02% 85.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35136-35143 1 0.00% 85.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35200-35207 2 0.00% 85.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35328-35335 143 0.16% 85.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35456-35463 1 0.00% 85.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35584-35591 69 0.08% 85.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35648-35655 1 0.00% 85.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35712-35719 1 0.00% 85.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35776-35783 1 0.00% 85.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35847 324 0.35% 86.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36096-36103 79 0.09% 86.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36160-36167 2 0.00% 86.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36224-36231 2 0.00% 86.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36352-36359 71 0.08% 86.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36480-36487 2 0.00% 86.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36544-36551 1 0.00% 86.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36608-36615 87 0.09% 86.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36871 344 0.38% 86.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37120-37127 77 0.08% 86.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37248-37255 1 0.00% 86.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37312-37319 1 0.00% 86.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37376-37383 23 0.03% 86.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37504-37511 2 0.00% 86.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37632-37639 141 0.15% 87.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37760-37767 1 0.00% 87.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37895 468 0.51% 87.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38151 6 0.01% 87.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38272-38279 1 0.00% 87.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38336-38343 1 0.00% 87.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38400-38407 91 0.10% 87.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38528-38535 6 0.01% 87.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38656-38663 98 0.11% 87.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38784-38791 2 0.00% 87.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38848-38855 1 0.00% 87.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38919 273 0.30% 88.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39168-39175 79 0.09% 88.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39424-39431 143 0.16% 88.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39552-39559 3 0.00% 88.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39616-39623 1 0.00% 88.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39680-39687 23 0.03% 88.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39744-39751 1 0.00% 88.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39936-39943 454 0.50% 88.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40000-40007 1 0.00% 88.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40064-40071 2 0.00% 88.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40192-40199 151 0.16% 89.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40448-40455 4 0.00% 89.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40576-40583 4 0.00% 89.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40704-40711 86 0.09% 89.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40967 275 0.30% 89.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41024-41031 2 0.00% 89.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41088-41095 1 0.00% 89.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41223 85 0.09% 89.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41344-41351 2 0.00% 89.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41472-41479 4 0.00% 89.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41600-41607 2 0.00% 89.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41728-41735 148 0.16% 89.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-41991 453 0.49% 90.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42112-42119 3 0.00% 90.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42176-42183 1 0.00% 90.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42240-42247 24 0.03% 90.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42304-42311 1 0.00% 90.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42432-42439 1 0.00% 90.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42503 142 0.15% 90.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42560-42567 1 0.00% 90.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42624-42631 2 0.00% 90.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42759 76 0.08% 90.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43015 275 0.30% 90.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43136-43143 1 0.00% 90.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43271 88 0.10% 90.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43328-43335 1 0.00% 90.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43456-43463 1 0.00% 90.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43527 89 0.10% 91.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43648-43655 3 0.00% 91.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43776-43783 6 0.01% 91.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43904-43911 1 0.00% 91.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43968-43975 2 0.00% 91.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 468 0.51% 91.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44096-44103 1 0.00% 91.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44295 137 0.15% 91.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44416-44423 1 0.00% 91.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44551 25 0.03% 91.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44672-44679 2 0.00% 91.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44736-44743 1 0.00% 91.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44807 78 0.09% 91.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44928-44935 1 0.00% 91.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44992-44999 2 0.00% 91.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 347 0.38% 92.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45184-45191 1 0.00% 92.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45319 91 0.10% 92.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45440-45447 1 0.00% 92.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45504-45511 1 0.00% 92.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 81 0.09% 92.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45696-45703 3 0.00% 92.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45760-45767 1 0.00% 92.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 82 0.09% 92.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46016-46023 1 0.00% 92.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 326 0.36% 92.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46208-46215 1 0.00% 92.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46343 68 0.07% 92.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46400-46407 1 0.00% 92.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46464-46471 1 0.00% 92.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46599 144 0.16% 93.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46656-46663 1 0.00% 93.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46720-46727 1 0.00% 93.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 21 0.02% 93.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46912-46919 1 0.00% 93.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46976-46983 2 0.00% 93.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 330 0.36% 93.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47168-47175 2 0.00% 93.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47296-47303 1 0.00% 93.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 78 0.09% 93.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47424-47431 1 0.00% 93.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47488-47495 1 0.00% 93.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47552-47559 1 0.00% 93.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 85 0.09% 93.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47744-47751 2 0.00% 93.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 19 0.02% 93.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48000-48007 2 0.00% 93.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 398 0.43% 94.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 77 0.08% 94.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48512-48519 1 0.00% 94.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 140 0.15% 94.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48768-48775 56 0.06% 94.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 70 0.08% 94.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48960-48967 2 0.00% 94.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49024-49031 2 0.00% 94.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 3 0.00% 94.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 5010 5.47% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49600-49607 2 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49856-49863 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49920-49927 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50048-50055 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50112-50119 2 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50240-50247 2 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50432-50439 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50624-50631 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50752-50759 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50816-50823 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50880-50887 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50944-50951 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51136-51143 2 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51200-51207 2 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51328-51335 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51392-51399 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51456-51463 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51648-51655 2 0.00% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::51712-51719 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51904-51911 2 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51968-51975 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52160-52167 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52416-52423 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 70891 # Bytes accessed per row activation -system.physmem.totQLat 151784626000 # Total ticks spent queuing -system.physmem.totMemAccLat 191524282250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 31106155000 # Total ticks spent in databus transfers -system.physmem.totBankLat 8633501250 # Total ticks spent accessing banks -system.physmem.avgQLat 24397.84 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1387.75 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::51776-51783 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51840-51847 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51968-51975 2 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::52032-52039 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 91629 # Bytes accessed per row activation +system.physmem.totQLat 370859657500 # Total ticks spent queuing +system.physmem.totMemAccLat 464833837500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 76318685000 # Total ticks spent in databus transfers +system.physmem.totBankLat 17655495000 # Total ticks spent accessing banks +system.physmem.avgQLat 24296.78 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1156.70 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30785.59 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 360.40 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 6.70 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 53.58 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 6.60 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30453.48 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 374.91 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.85 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 50.49 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.81 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.87 # Data bus utilization in percentage -system.physmem.busUtilRead 2.82 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.17 # Average read queue length when enqueuing -system.physmem.avgWrQLen 10.13 # Average write queue length when enqueuing -system.physmem.readRowHits 6167948 # Number of row buffer hits during reads -system.physmem.writeRowHits 98004 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.14 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 84.77 # Row buffer hit rate for writes -system.physmem.avgGap 156007.30 # Average gap between requests -system.physmem.pageHitRate 98.88 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 3.90 # Percentage of time for which DRAM has all the banks in precharge state +system.physmem.busUtil 2.95 # Data bus utilization in percentage +system.physmem.busUtilRead 2.93 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing +system.physmem.avgWrQLen 12.21 # Average write queue length when enqueuing +system.physmem.readRowHits 15189856 # Number of row buffer hits during reads +system.physmem.writeRowHits 98161 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 84.68 # Row buffer hit rate for writes +system.physmem.avgGap 161575.49 # Average gap between requests +system.physmem.pageHitRate 99.40 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 2.44 # Percentage of time for which DRAM has all the banks in precharge state system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory @@ -743,308 +784,308 @@ system.realview.nvmem.bytes_inst_read::total 448 system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 58 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 348 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 406 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 58 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 348 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 406 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 58 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 348 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 406 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 62368825 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 7306736 # Transaction distribution -system.membus.trans_dist::ReadResp 7306736 # Transaction distribution -system.membus.trans_dist::WriteReq 767886 # Transaction distribution -system.membus.trans_dist::WriteResp 767886 # Transaction distribution -system.membus.trans_dist::Writeback 66680 # Transaction distribution -system.membus.trans_dist::UpgradeReq 33856 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 17703 # Transaction distribution -system.membus.trans_dist::UpgradeResp 12570 # Transaction distribution -system.membus.trans_dist::ReadExReq 138080 # Transaction distribution -system.membus.trans_dist::ReadExResp 137692 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382504 # Packet count per connected master and slave (bytes) +system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 147 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 172 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 147 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 172 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 147 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 172 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 54229250 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16352579 # Transaction distribution +system.membus.trans_dist::ReadResp 16352579 # Transaction distribution +system.membus.trans_dist::WriteReq 769165 # Transaction distribution +system.membus.trans_dist::WriteResp 769165 # Transaction distribution +system.membus.trans_dist::Writeback 66909 # Transaction distribution +system.membus.trans_dist::UpgradeReq 35978 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 18300 # Transaction distribution +system.membus.trans_dist::UpgradeResp 14191 # Transaction distribution +system.membus.trans_dist::ReadExReq 138286 # Transaction distribution +system.membus.trans_dist::ReadExResp 137908 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384274 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 11632 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13828 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 842 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1971133 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4366129 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12189696 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 12189696 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 16555825 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389767 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 2042 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1977266 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4377428 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 34655060 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2392545 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 23264 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 27656 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1684 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17729012 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 20144183 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 48758784 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 48758784 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 68902967 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 68902967 # Total data (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 4084 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17766916 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 20191657 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 141302185 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 141302185 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1486954500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1488154000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer1.occupancy 7000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 9891500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11766000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 3000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 747500 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1798000 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 8614133500 # Layer occupancy (ticks) -system.membus.reqLayer6.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 4838543340 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.respLayer2.occupancy 13759512942 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 1.2 # Layer utilization (%) +system.membus.reqLayer6.occupancy 17661743000 # Layer occupancy (ticks) +system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 4847485258 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.respLayer2.occupancy 34183780195 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 1.3 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 72740 # number of replacements -system.l2c.tags.tagsinuse 53860.173191 # Cycle average of tags in use -system.l2c.tags.total_refs 1837966 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 137924 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.325933 # Average number of references to valid blocks. +system.l2c.tags.replacements 73073 # number of replacements +system.l2c.tags.tagsinuse 53003.397460 # Cycle average of tags in use +system.l2c.tags.total_refs 1874154 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 138227 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.558523 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 39518.362493 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 5.391068 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.010261 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4016.186215 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2832.215798 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 8.504423 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3702.179063 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3777.323870 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.603002 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000082 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 37718.016524 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 5.174616 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000363 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4163.072469 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2965.510583 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 10.620056 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 4041.319246 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 4099.683602 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.575531 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000079 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.061282 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.043216 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000130 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.056491 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.057637 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.821841 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65179 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 312 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3125 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 8680 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 53038 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.994553 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 18564692 # Number of tag accesses -system.l2c.tags.data_accesses 18564692 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 22002 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4348 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 385872 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 166544 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 31083 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 5052 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 589425 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 198327 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1402653 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 581363 # number of Writeback hits -system.l2c.Writeback_hits::total 581363 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1344 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 738 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2082 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 204 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 140 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 344 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 48345 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 58632 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 106977 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 22002 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4348 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 385872 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 214889 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 31083 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 5052 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 589425 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 256959 # number of demand (read+write) hits -system.l2c.demand_hits::total 1509630 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 22002 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4348 # number of overall hits -system.l2c.overall_hits::cpu0.inst 385872 # number of overall hits -system.l2c.overall_hits::cpu0.data 214889 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 31083 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 5052 # number of overall hits -system.l2c.overall_hits::cpu1.inst 589425 # number of overall hits -system.l2c.overall_hits::cpu1.data 256959 # number of overall hits -system.l2c.overall_hits::total 1509630 # number of overall hits +system.l2c.tags.occ_percent::cpu0.inst 0.063523 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.045250 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000162 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.061666 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.062556 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.808768 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65150 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 313 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3081 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 9065 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 52647 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.994110 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 18858156 # Number of tag accesses +system.l2c.tags.data_accesses 18858156 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 22538 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 4343 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 393811 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 165625 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 33531 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 5781 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 608221 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 201520 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1435370 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 583255 # number of Writeback hits +system.l2c.Writeback_hits::total 583255 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 1158 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 763 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 1921 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 210 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 161 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 371 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 47894 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 59257 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 107151 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 22538 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 4343 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 393811 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 213519 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 33531 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 5781 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 608221 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 260777 # number of demand (read+write) hits +system.l2c.demand_hits::total 1542521 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 22538 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 4343 # number of overall hits +system.l2c.overall_hits::cpu0.inst 393811 # number of overall hits +system.l2c.overall_hits::cpu0.data 213519 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 33531 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 5781 # number of overall hits +system.l2c.overall_hits::cpu1.inst 608221 # number of overall hits +system.l2c.overall_hits::cpu1.data 260777 # number of overall hits +system.l2c.overall_hits::total 1542521 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 13 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 6278 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6388 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 13 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 6308 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 6245 # number of ReadReq misses -system.l2c.ReadReq_misses::total 25248 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 5144 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 3776 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 8920 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 633 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 420 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1053 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 63281 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 77008 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 140289 # number of ReadExReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 6016 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 6332 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 16 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 6652 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 6334 # number of ReadReq misses +system.l2c.ReadReq_misses::total 25365 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 5730 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 4444 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 10174 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 769 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 591 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1360 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 63376 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 77189 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 140565 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 13 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 6278 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 69669 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 13 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 6308 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 83253 # number of demand (read+write) misses -system.l2c.demand_misses::total 165537 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 6016 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 69708 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 16 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 6652 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 83523 # number of demand (read+write) misses +system.l2c.demand_misses::total 165930 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 13 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses -system.l2c.overall_misses::cpu0.inst 6278 # number of overall misses -system.l2c.overall_misses::cpu0.data 69669 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 13 # number of overall misses -system.l2c.overall_misses::cpu1.inst 6308 # number of overall misses -system.l2c.overall_misses::cpu1.data 83253 # number of overall misses -system.l2c.overall_misses::total 165537 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 1043750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 232500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 459739750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 479407748 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1279750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 475943000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 485330750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1902977248 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 8942096 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 12221481 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 21163577 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 441981 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2952874 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 3394855 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 4424511594 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 6267545062 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 10692056656 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 1043750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 232500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 459739750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 4903919342 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 1279750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 475943000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 6752875812 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 12595033904 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 1043750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 232500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 459739750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 4903919342 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 1279750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 475943000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 6752875812 # number of overall miss cycles -system.l2c.overall_miss_latency::total 12595033904 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 22015 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 4351 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 392150 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 172932 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 31096 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 5052 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 595733 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 204572 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1427901 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 581363 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 581363 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 6488 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 4514 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 11002 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 837 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 560 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1397 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 111626 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 135640 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 247266 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 22015 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 4351 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 392150 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 284558 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 31096 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 5052 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 595733 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 340212 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1675167 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 22015 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 4351 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 392150 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 284558 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 31096 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 5052 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 595733 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 340212 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1675167 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000591 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000689 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.016009 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.036939 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000418 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.010589 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.030527 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.017682 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.792848 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.836509 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.810762 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.756272 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.750000 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.753758 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.566902 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.567738 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.567361 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000591 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000689 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.016009 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.244832 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000418 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.010589 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.244709 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.098818 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000591 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000689 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.016009 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.244832 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000418 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.010589 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.244709 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.098818 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 80288.461538 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 77500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 73230.288308 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 75048.175955 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 98442.307692 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 75450.697527 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 77715.092074 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 75371.405577 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1738.354588 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3236.621028 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 2372.598318 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 698.232227 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 7030.652381 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 3223.983856 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 69918.484126 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81388.233197 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 76214.504744 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 80288.461538 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 77500 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 73230.288308 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 70388.829207 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 98442.307692 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 75450.697527 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 81112.702389 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 76085.913747 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 80288.461538 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 77500 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 73230.288308 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 70388.829207 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 98442.307692 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 75450.697527 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 81112.702389 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 76085.913747 # average overall miss latency +system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses +system.l2c.overall_misses::cpu0.inst 6016 # number of overall misses +system.l2c.overall_misses::cpu0.data 69708 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 16 # number of overall misses +system.l2c.overall_misses::cpu1.inst 6652 # number of overall misses +system.l2c.overall_misses::cpu1.data 83523 # number of overall misses +system.l2c.overall_misses::total 165930 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 1304750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 448000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 446523000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 475767500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 2003000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 503930500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 490115499 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1920092249 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 9037094 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 12252979 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 21290073 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 536977 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 3190365 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 3727342 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 4442697562 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 6102357274 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 10545054836 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 1304750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 448000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 446523000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 4918465062 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 2003000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 503930500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 6592472773 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 12465147085 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 1304750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 448000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 446523000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 4918465062 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 2003000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 503930500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 6592472773 # number of overall miss cycles +system.l2c.overall_miss_latency::total 12465147085 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 22551 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 4345 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 399827 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 171957 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 33547 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 5781 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 614873 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 207854 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1460735 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 583255 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 583255 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 6888 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 5207 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 12095 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 979 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 752 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1731 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 111270 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 136446 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 247716 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 22551 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 4345 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 399827 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 283227 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 33547 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 5781 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 614873 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 344300 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1708451 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 22551 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 4345 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 399827 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 283227 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 33547 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 5781 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 614873 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 344300 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1708451 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000576 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000460 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.015047 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.036823 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000477 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.010818 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.030473 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.017365 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.831882 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.853466 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.841174 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.785495 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.785904 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.785673 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.569570 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.565711 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.567444 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000576 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000460 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.015047 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.246121 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000477 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.010818 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.242588 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.097123 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000576 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000460 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.015047 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.246121 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000477 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.010818 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.242588 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.097123 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 100365.384615 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 224000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 74222.573138 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 75137.002527 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 125187.500000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 75756.238725 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 77378.512630 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 75698.491977 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1577.154276 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2757.195995 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 2092.596127 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 698.279584 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5398.248731 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 2740.692647 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 70100.630554 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 79057.343326 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 75019.064746 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 100365.384615 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 224000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 74222.573138 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 70558.114736 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 125187.500000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 75756.238725 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 78930.028531 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 75122.925842 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 100365.384615 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 224000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 74222.573138 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 70558.114736 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 125187.500000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 75756.238725 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 78930.028531 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 75122.925842 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1053,168 +1094,168 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 66680 # number of writebacks -system.l2c.writebacks::total 66680 # number of writebacks +system.l2c.writebacks::writebacks 66909 # number of writebacks +system.l2c.writebacks::total 66909 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu0.inst 4 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu0.data 38 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu0.data 39 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu1.inst 7 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.data 25 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.data 28 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 78 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu0.inst 4 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.data 38 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.data 39 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.data 25 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 74 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.data 28 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 78 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu0.inst 4 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.data 38 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.data 39 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.data 25 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 74 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.data 28 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 78 # number of overall MSHR hits system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 13 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 3 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 6274 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 6350 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 13 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 6301 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 6220 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 25174 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 5144 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 3776 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 8920 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 633 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 420 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1053 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 63281 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 77008 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 140289 # number of ReadExReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 6012 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 6293 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 16 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 6645 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 6306 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 25287 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 5730 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 4444 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 10174 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 769 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 591 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1360 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 63376 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 77189 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 140565 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu0.dtb.walker 13 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 3 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 6274 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 69631 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 13 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 6301 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 83228 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 165463 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 6012 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 69669 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 16 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 6645 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 83495 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 165852 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu0.dtb.walker 13 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 3 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 6274 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 69631 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 13 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 6301 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 83228 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 165463 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 881250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 196000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 380499000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 397371498 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 1120250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 396299500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 405553250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1581920748 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 51551580 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 38112192 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 89663772 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 6339632 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4220416 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 10560048 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3630585396 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 5309182934 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 8939768330 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 881250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 196000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 380499000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 4027956894 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1120250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 396299500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 5714736184 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 10521689078 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 881250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 196000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 380499000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 4027956894 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1120250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 396299500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 5714736184 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 10521689078 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 6382249 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12399518741 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 2397749 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154603727234 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 167012025973 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1005734999 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 16506425201 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 17512160200 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 6382249 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13405253740 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 2397749 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 171110152435 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 184524186173 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000591 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000689 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015999 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036720 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000418 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010577 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030405 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.017630 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.792848 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.836509 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.810762 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.756272 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.750000 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.753758 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.566902 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.567738 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.567361 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000591 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000689 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015999 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.244699 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000418 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010577 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.244636 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.098774 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000591 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000689 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015999 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.244699 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000418 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010577 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.244636 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.098774 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 67788.461538 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 65333.333333 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60646.955690 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 62578.188661 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 86173.076923 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62894.699254 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65201.487138 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 62839.467228 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10021.691291 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10093.271186 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10051.992377 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10015.216430 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10048.609524 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10028.535613 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 57372.440322 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 68943.264778 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 63723.943645 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 67788.461538 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 65333.333333 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60646.955690 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 57847.178613 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 86173.076923 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62894.699254 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 68663.625030 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 63589.376948 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 67788.461538 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 65333.333333 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60646.955690 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57847.178613 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 86173.076923 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62894.699254 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 68663.625030 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 63589.376948 # average overall mshr miss latency +system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 6012 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 69669 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 16 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 6645 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 83495 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 165852 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 1144250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 423500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 370171500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 394094000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 1806000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 419977000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 409755749 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1597371999 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 57405667 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 44808866 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 102214533 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 7693266 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 5930585 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 13623851 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3647692922 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 5143522218 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 8791215140 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 1144250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 423500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 370171500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 4041786922 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1806000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 419977000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 5553277967 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 10388587139 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 1144250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 423500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 370171500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 4041786922 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1806000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 419977000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 5553277967 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 10388587139 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 6844749 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12329934488 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 2547499 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154880876489 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 167220203225 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1069838998 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 16519194406 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 17589033404 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 6844749 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13399773486 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 2547499 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 171400070895 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 184809236629 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000576 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000460 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015037 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036596 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000477 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010807 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030339 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.017311 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.831882 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.853466 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.841174 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.785495 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.785904 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.785673 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.569570 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.565711 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.567444 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000576 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000460 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015037 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.245983 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000477 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010807 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.242507 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.097077 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000576 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000460 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015037 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.245983 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000477 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010807 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.242507 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.097077 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 88019.230769 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 211750 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 61572.105788 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 62624.185603 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 112875 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 63201.956358 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 64978.710593 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 63169.691897 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10018.441012 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10083.003150 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10046.641734 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10004.247074 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10034.830795 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10017.537500 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 57556.376578 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 66635.430152 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 62541.992246 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 88019.230769 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 211750 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 61572.105788 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 58014.137163 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 112875 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63201.956358 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 66510.305611 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 62637.695892 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 88019.230769 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 211750 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 61572.105788 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 58014.137163 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 112875 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63201.956358 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 66510.305611 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 62637.695892 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -1235,67 +1276,67 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 136617428 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2707473 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2707472 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 767886 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 767886 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 581363 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 33341 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 18047 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 51388 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 258982 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 258982 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 785116 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1073701 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 13590 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 55763 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1192186 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4801848 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 14637 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 72416 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 8009257 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 25105344 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 34847157 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 17404 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 88060 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 38129856 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 47787842 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 20208 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 124384 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 146120255 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 146120255 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 4810056 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4893985918 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1769514129 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1514543493 # Layer occupancy (ticks) +system.toL2Bus.throughput 58740655 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2741580 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2741579 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 769165 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 769165 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 583255 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 35242 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 18671 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 53913 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 259438 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 259438 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 800468 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1073661 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 13619 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 56672 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1230417 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4820854 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 15509 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 76068 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 8087268 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 25596864 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 34696353 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 17380 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 90204 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 39355008 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 48247560 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 23124 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 134188 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 148160681 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 148160681 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 4896624 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4922304939 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 1803966688 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 1516604948 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 9260456 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 9296947 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 33892454 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 34267946 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 2685747678 # Layer occupancy (ticks) -system.toL2Bus.respLayer4.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 3237154790 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 9609448 # Layer occupancy (ticks) -system.toL2Bus.respLayer6.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 41592193 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 46298079 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 7278155 # Transaction distribution -system.iobus.trans_dist::ReadResp 7278155 # Transaction distribution -system.iobus.trans_dist::WriteReq 7945 # Transaction distribution -system.iobus.trans_dist::WriteResp 7945 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30446 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8022 # Packet count per connected master and slave (bytes) +system.toL2Bus.respLayer6.occupancy 2771620829 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 3258153300 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer8.occupancy 9753444 # Layer occupancy (ticks) +system.toL2Bus.respLayer8.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer9.occupancy 42798427 # Layer occupancy (ticks) +system.toL2Bus.respLayer9.utilization 0.0 # Layer utilization (%) +system.iobus.throughput 47398269 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16322887 # Transaction distribution +system.iobus.trans_dist::ReadResp 16322887 # Transaction distribution +system.iobus.trans_dist::WriteReq 8066 # Transaction distribution +system.iobus.trans_dist::WriteResp 8066 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30842 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8846 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 724 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1030 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 494 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 738 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -1312,17 +1353,17 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382504 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12189696 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::total 12189696 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 14572200 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40164 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16044 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2384274 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 32661906 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40560 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 17692 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1448 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2060 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 271 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 393 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1339,27 +1380,27 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2389767 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 48758784 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::total 48758784 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 51148551 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 51148551 # Total data (bytes) -system.iobus.reqLayer0.occupancy 21348000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size_system.bridge.master::total 2392545 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 123503073 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 123503073 # Total data (bytes) +system.iobus.reqLayer0.occupancy 21645000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 4017000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 4429000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 368000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 521000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 297000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 441000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) -system.iobus.reqLayer7.utilization 0.1 # Layer utilization (%) +system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) @@ -1390,44 +1431,86 @@ system.iobus.reqLayer22.occupancy 8000 # La system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 6094848000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374559000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.2 # Layer utilization (%) -system.iobus.respLayer1.occupancy 16664463058 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) -system.cpu0.branchPred.lookups 5998612 # Number of BP lookups -system.cpu0.branchPred.condPredicted 4575425 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 295221 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 3794321 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 2910648 # Number of BTB hits +system.iobus.respLayer0.occupancy 2376208000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) +system.iobus.respLayer1.occupancy 41458010805 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) +system.cpu0.branchPred.lookups 6118154 # Number of BP lookups +system.cpu0.branchPred.condPredicted 4670367 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 295970 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 3816631 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 2949053 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 76.710642 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 672923 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 29222 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 77.268486 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 684315 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 28445 # Number of incorrect RAS predictions. +system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 8906772 # DTB read hits -system.cpu0.dtb.read_misses 28714 # DTB read misses -system.cpu0.dtb.write_hits 5141355 # DTB write hits -system.cpu0.dtb.write_misses 5491 # DTB write misses +system.cpu0.dtb.read_hits 8969635 # DTB read hits +system.cpu0.dtb.read_misses 28952 # DTB read misses +system.cpu0.dtb.write_hits 5211846 # DTB write hits +system.cpu0.dtb.write_misses 5698 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1825 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 924 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 308 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 1738 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1053 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 275 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 586 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 8935486 # DTB read accesses -system.cpu0.dtb.write_accesses 5146846 # DTB write accesses +system.cpu0.dtb.perms_faults 590 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 8998587 # DTB read accesses +system.cpu0.dtb.write_accesses 5217544 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14048127 # DTB hits -system.cpu0.dtb.misses 34205 # DTB misses -system.cpu0.dtb.accesses 14082332 # DTB accesses -system.cpu0.itb.inst_hits 4217878 # ITB inst hits -system.cpu0.itb.inst_misses 5102 # ITB inst misses +system.cpu0.dtb.hits 14181481 # DTB hits +system.cpu0.dtb.misses 34650 # DTB misses +system.cpu0.dtb.accesses 14216131 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.itb.inst_hits 4279077 # ITB inst hits +system.cpu0.itb.inst_misses 5117 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -1436,545 +1519,549 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1349 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1212 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1453 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1385 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 4222980 # ITB inst accesses -system.cpu0.itb.hits 4217878 # DTB hits -system.cpu0.itb.misses 5102 # DTB misses -system.cpu0.itb.accesses 4222980 # DTB accesses -system.cpu0.numCycles 69399845 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 4284194 # ITB inst accesses +system.cpu0.itb.hits 4279077 # DTB hits +system.cpu0.itb.misses 5117 # DTB misses +system.cpu0.itb.accesses 4284194 # DTB accesses +system.cpu0.numCycles 70223968 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 11707943 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 32011744 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 5998612 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3583571 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 7516048 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1450698 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 61322 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 19616707 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 4844 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 46699 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 1334001 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 291 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 4216315 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 157019 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2077 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 41328581 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.001115 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.381687 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 11927082 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 32438478 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 6118154 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3633368 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 7610656 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1458202 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 60559 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 20342851 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 5497 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 47160 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 1383184 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 317 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 4277582 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 158526 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2073 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 42423154 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.988026 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.369139 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 33820062 81.83% 81.83% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 563590 1.36% 83.20% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 816833 1.98% 85.17% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 678550 1.64% 86.81% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 773451 1.87% 88.69% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 557877 1.35% 90.04% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 667950 1.62% 91.65% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 351268 0.85% 92.50% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3099000 7.50% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 34819772 82.08% 82.08% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 571665 1.35% 83.42% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 825898 1.95% 85.37% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 684492 1.61% 86.99% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 779946 1.84% 88.82% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 566234 1.33% 90.16% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 677676 1.60% 91.76% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 358556 0.85% 92.60% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3138915 7.40% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 41328581 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.086436 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.461265 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 12211654 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 20807916 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 6822131 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 509652 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 977228 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 934234 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 64577 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 40012411 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 212282 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 977228 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 12781253 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 5974864 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 12788176 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 6710782 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 2096278 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 38908722 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 1870 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 435924 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1167673 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 74 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 39248766 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 175739111 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 161807828 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 3998 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 30938690 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 8310075 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 411292 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 370393 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5377655 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7648768 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5690459 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1124911 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1238842 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 36825251 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 895403 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 37248866 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 80758 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6273186 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 13119240 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 256527 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 41328581 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.901286 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.515261 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 42423154 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.087123 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.461929 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 12476093 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 21540045 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 6871897 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 553157 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 981962 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 949644 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 64975 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 40551006 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 213850 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 981962 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 13051542 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 5910563 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 13528575 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6803012 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 2147500 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 39435352 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 334 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 441883 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1170709 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 119 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 39847910 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 180543493 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 163844376 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 4138 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 31495709 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 8352200 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 460642 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 417076 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5513022 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7756413 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5773431 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1120554 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1217575 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 37342460 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 905810 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 37712626 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 83166 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6296628 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 13228023 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 256791 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 42423154 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.888963 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.506683 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 26256934 63.53% 63.53% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 5686623 13.76% 77.29% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3113893 7.53% 84.83% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2469463 5.98% 90.80% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2128203 5.15% 95.95% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 923425 2.23% 98.19% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 509489 1.23% 99.42% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 185211 0.45% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 55340 0.13% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 27070740 63.81% 63.81% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5892236 13.89% 77.70% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3160742 7.45% 85.15% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2473733 5.83% 90.98% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2116122 4.99% 95.97% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 945480 2.23% 98.20% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 519157 1.22% 99.42% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 188675 0.44% 99.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 56269 0.13% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 41328581 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 42423154 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 26660 2.48% 2.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 451 0.04% 2.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 843359 78.54% 81.06% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 203361 18.94% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 27921 2.59% 2.59% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 464 0.04% 2.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 839960 77.98% 80.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 208811 19.39% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 52279 0.14% 0.14% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 22336119 59.96% 60.10% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 46932 0.13% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 10 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 6 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 700 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9364529 25.14% 85.37% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5448283 14.63% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 14551 0.04% 0.04% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 22686320 60.16% 60.19% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 48095 0.13% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 12 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 10 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 680 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 11 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9430202 25.01% 85.33% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5532744 14.67% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 37248866 # Type of FU issued -system.cpu0.iq.rate 0.536728 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1073831 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.028829 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 117006401 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 44001611 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 34345325 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 8483 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 4644 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 3871 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 38265951 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 4467 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 306869 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 37712626 # Type of FU issued +system.cpu0.iq.rate 0.537034 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1077156 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.028562 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 119034571 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 44552771 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 34849273 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 8516 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 4702 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 3893 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 38770775 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 4456 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 316259 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1369766 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2413 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 12945 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 538318 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1371122 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2677 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 13108 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 538058 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2192768 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5933 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2149551 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5893 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 977228 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 4326370 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 99368 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 37837801 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 83554 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7648768 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5690459 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 571361 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 39650 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 5884 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 12945 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 150463 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 117241 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 267704 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 36870822 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9222297 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 378044 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 981962 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 4290254 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 101346 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 38366333 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 82356 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7756413 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5773431 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 579216 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 40773 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 5894 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 13108 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 150282 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 117544 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 267826 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 37333576 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9286892 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 379050 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 117147 # number of nop insts executed -system.cpu0.iew.exec_refs 14623543 # number of memory reference insts executed -system.cpu0.iew.exec_branches 4855012 # Number of branches executed -system.cpu0.iew.exec_stores 5401246 # Number of stores executed -system.cpu0.iew.exec_rate 0.531281 # Inst execution rate -system.cpu0.iew.wb_sent 36677243 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 34349196 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 18314277 # num instructions producing a value -system.cpu0.iew.wb_consumers 35200184 # num instructions consuming a value +system.cpu0.iew.exec_nop 118063 # number of nop insts executed +system.cpu0.iew.exec_refs 14771553 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4961106 # Number of branches executed +system.cpu0.iew.exec_stores 5484661 # Number of stores executed +system.cpu0.iew.exec_rate 0.531636 # Inst execution rate +system.cpu0.iew.wb_sent 37138785 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 34853166 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 18592793 # num instructions producing a value +system.cpu0.iew.wb_consumers 35689861 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.494946 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.520289 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.496314 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.520954 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6083137 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 638876 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 231723 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 40351353 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.775579 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.741147 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6112781 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 649019 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 232084 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 41441192 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.767334 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.727698 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 28712298 71.16% 71.16% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 5699883 14.13% 85.28% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1888088 4.68% 89.96% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 980743 2.43% 92.39% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 789976 1.96% 94.35% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 505077 1.25% 95.60% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 395357 0.98% 96.58% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 219519 0.54% 97.12% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1160412 2.88% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 29493448 71.17% 71.17% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 5926009 14.30% 85.47% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1935659 4.67% 90.14% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1007052 2.43% 92.57% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 761622 1.84% 94.41% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 520069 1.25% 95.66% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 411110 0.99% 96.65% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 222523 0.54% 97.19% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1163700 2.81% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 40351353 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 23685352 # Number of instructions committed -system.cpu0.commit.committedOps 31295648 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 41441192 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 24076968 # Number of instructions committed +system.cpu0.commit.committedOps 31799237 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 11431143 # Number of memory references committed -system.cpu0.commit.loads 6279002 # Number of loads committed -system.cpu0.commit.membars 229688 # Number of memory barriers committed -system.cpu0.commit.branches 4246153 # Number of branches committed +system.cpu0.commit.refs 11620664 # Number of memory references committed +system.cpu0.commit.loads 6385291 # Number of loads committed +system.cpu0.commit.membars 231891 # Number of memory barriers committed +system.cpu0.commit.branches 4352331 # Number of branches committed system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 27651273 # Number of committed integer instructions. -system.cpu0.commit.function_calls 489419 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1160412 # number cycles where commit BW limit reached +system.cpu0.commit.int_insts 28144226 # Number of committed integer instructions. +system.cpu0.commit.function_calls 499126 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1163700 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 75718589 # The number of ROB reads -system.cpu0.rob.rob_writes 75736714 # The number of ROB writes -system.cpu0.timesIdled 363087 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 28071264 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2140090760 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 23604610 # Number of Instructions Simulated -system.cpu0.committedOps 31214906 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 23604610 # Number of Instructions Simulated -system.cpu0.cpi 2.940097 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.940097 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.340125 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.340125 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 171854579 # number of integer regfile reads -system.cpu0.int_regfile_writes 34094081 # number of integer regfile writes -system.cpu0.fp_regfile_reads 3288 # number of floating regfile reads -system.cpu0.fp_regfile_writes 904 # number of floating regfile writes -system.cpu0.misc_regfile_reads 13200315 # number of misc regfile reads -system.cpu0.misc_regfile_writes 451289 # number of misc regfile writes -system.cpu0.icache.tags.replacements 392190 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.931857 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 3792228 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 392702 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 9.656758 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 7054061250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 510.931857 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.997914 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.997914 # Average percentage of cache occupancy +system.cpu0.rob.rob_reads 77320455 # The number of ROB reads +system.cpu0.rob.rob_writes 76807713 # The number of ROB writes +system.cpu0.timesIdled 366523 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 27800814 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5141023759 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 23996226 # Number of Instructions Simulated +system.cpu0.committedOps 31718495 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 23996226 # Number of Instructions Simulated +system.cpu0.cpi 2.926459 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.926459 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.341710 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.341710 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 174280890 # number of integer regfile reads +system.cpu0.int_regfile_writes 34606104 # number of integer regfile writes +system.cpu0.fp_regfile_reads 3371 # number of floating regfile reads +system.cpu0.fp_regfile_writes 930 # number of floating regfile writes +system.cpu0.misc_regfile_reads 79193882 # number of misc regfile reads +system.cpu0.misc_regfile_writes 501030 # number of misc regfile writes +system.cpu0.icache.tags.replacements 399855 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.561575 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 3845551 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 400367 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 9.605065 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 7054920250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.561575 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999144 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999144 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 210 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 170 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 133 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 209 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 168 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 4608911 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 4608911 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 3792228 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 3792228 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 3792228 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 3792228 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 3792228 # number of overall hits -system.cpu0.icache.overall_hits::total 3792228 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 423961 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 423961 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 423961 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 423961 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 423961 # number of overall misses -system.cpu0.icache.overall_misses::total 423961 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5895815248 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5895815248 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5895815248 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5895815248 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5895815248 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5895815248 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 4216189 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 4216189 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 4216189 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 4216189 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 4216189 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 4216189 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100556 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.100556 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100556 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.100556 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100556 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.100556 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13906.503777 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13906.503777 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13906.503777 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13906.503777 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13906.503777 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13906.503777 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 3717 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 4677842 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 4677842 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 3845551 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 3845551 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 3845551 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 3845551 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 3845551 # number of overall hits +system.cpu0.icache.overall_hits::total 3845551 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 431900 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 431900 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 431900 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 431900 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 431900 # number of overall misses +system.cpu0.icache.overall_misses::total 431900 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5980648802 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5980648802 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5980648802 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5980648802 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5980648802 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5980648802 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 4277451 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 4277451 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 4277451 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 4277451 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 4277451 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 4277451 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100971 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.100971 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100971 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.100971 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100971 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.100971 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13847.299843 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13847.299843 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13847.299843 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13847.299843 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13847.299843 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13847.299843 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 3472 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 174 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 151 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 21.362069 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 22.993377 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 31238 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 31238 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 31238 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 31238 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 31238 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 31238 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 392723 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 392723 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 392723 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 392723 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 392723 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 392723 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4798060362 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4798060362 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4798060362 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4798060362 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4798060362 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4798060362 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8923500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8923500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8923500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 8923500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093146 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093146 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093146 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.093146 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093146 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.093146 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12217.416250 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12217.416250 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12217.416250 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12217.416250 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12217.416250 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12217.416250 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 31508 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 31508 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 31508 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 31508 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 31508 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 31508 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 400392 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 400392 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 400392 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 400392 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 400392 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 400392 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4871658304 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4871658304 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4871658304 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4871658304 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4871658304 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4871658304 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 9448000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 9448000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 9448000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 9448000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093605 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093605 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093605 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.093605 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093605 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.093605 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12167.221883 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12167.221883 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12167.221883 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12167.221883 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12167.221883 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12167.221883 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 276315 # number of replacements -system.cpu0.dcache.tags.tagsinuse 459.475838 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 9261350 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 276827 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 33.455371 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 43491250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 459.475838 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.897414 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.897414 # Average percentage of cache occupancy +system.cpu0.dcache.tags.replacements 275331 # number of replacements +system.cpu0.dcache.tags.tagsinuse 480.265935 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 9430413 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 275843 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 34.187610 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 43744250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 480.265935 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.938019 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.938019 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 179 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 314 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 192 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 45150578 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 45150578 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 5781234 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5781234 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3158881 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3158881 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139214 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 139214 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137082 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 137082 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 8940115 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 8940115 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 8940115 # number of overall hits -system.cpu0.dcache.overall_hits::total 8940115 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 391237 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 391237 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1585894 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1585894 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8707 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 8707 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7466 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7466 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1977131 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1977131 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1977131 # number of overall misses -system.cpu0.dcache.overall_misses::total 1977131 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5519617945 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5519617945 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 79664471073 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 79664471073 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 90084987 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 90084987 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 45897132 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 45897132 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 85184089018 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 85184089018 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 85184089018 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 85184089018 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6172471 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6172471 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4744775 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4744775 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 147921 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 147921 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144548 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 144548 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 10917246 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 10917246 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 10917246 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 10917246 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063384 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.063384 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.334240 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.334240 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.058863 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.058863 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051651 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051651 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.181102 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.181102 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.181102 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.181102 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14108.118468 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14108.118468 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50233.162540 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 50233.162540 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10346.271621 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10346.271621 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6147.486204 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6147.486204 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 43084.696471 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 43084.696471 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 43084.696471 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 43084.696471 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 10884 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 8688 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 601 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 128 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 18.109817 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 67.875000 # average number of cycles each access was blocked +system.cpu0.dcache.tags.tag_accesses 45818436 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 45818436 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 5876487 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5876487 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3229447 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3229447 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139508 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 139508 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137243 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 137243 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 9105934 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 9105934 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 9105934 # number of overall hits +system.cpu0.dcache.overall_hits::total 9105934 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 392643 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 392643 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1584583 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1584583 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8921 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 8921 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7758 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7758 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1977226 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1977226 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1977226 # number of overall misses +system.cpu0.dcache.overall_misses::total 1977226 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5519657990 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5519657990 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 80059065889 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 80059065889 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 91816480 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 91816480 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 49938268 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 49938268 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 85578723879 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 85578723879 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 85578723879 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 85578723879 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6269130 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6269130 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4814030 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4814030 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 148429 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 148429 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 145001 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 145001 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 11083160 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 11083160 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 11083160 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 11083160 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.062631 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.062631 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.329159 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.329159 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.060103 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.060103 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053503 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053503 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.178399 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.178399 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.178399 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.178399 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14057.701245 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14057.701245 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50523.744032 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 50523.744032 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10292.173523 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10292.173523 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6437.002836 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6437.002836 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 43282.216539 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 43282.216539 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 43282.216539 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 43282.216539 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 9306 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 7994 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 611 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 137 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 15.230769 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 58.350365 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 256502 # number of writebacks -system.cpu0.dcache.writebacks::total 256502 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 202469 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 202469 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1455378 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1455378 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 427 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 427 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1657847 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1657847 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1657847 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1657847 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188768 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 188768 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130516 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 130516 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8280 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8280 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7466 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7466 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 319284 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 319284 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 319284 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 319284 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2415025620 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2415025620 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5290299960 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5290299960 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 68915513 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 68915513 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 30963868 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 30963868 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7705325580 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 7705325580 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7705325580 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 7705325580 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13504357282 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13504357282 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1131166881 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1131166881 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14635524163 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14635524163 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030582 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030582 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027507 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027507 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.055976 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.055976 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051651 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051651 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029246 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.029246 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029246 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.029246 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12793.617668 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12793.617668 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40533.727359 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40533.727359 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8323.129589 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8323.129589 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4147.316903 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4147.316903 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24133.140339 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24133.140339 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24133.140339 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24133.140339 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 255436 # number of writebacks +system.cpu0.dcache.writebacks::total 255436 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 203336 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 203336 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1453472 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1453472 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 484 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 484 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1656808 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1656808 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1656808 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1656808 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189307 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 189307 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131111 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 131111 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8437 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8437 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7758 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7758 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 320418 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 320418 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 320418 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 320418 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2405173678 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2405173678 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5317055578 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5317055578 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69940520 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 69940520 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 34423732 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 34423732 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7722229256 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 7722229256 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7722229256 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 7722229256 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13428836532 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13428836532 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1202345879 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1202345879 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14631182411 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14631182411 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030197 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030197 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027235 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027235 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056842 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056842 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053503 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053503 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028910 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.028910 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028910 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.028910 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12705.149192 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12705.149192 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40553.848098 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40553.848098 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8289.738059 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8289.738059 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4437.191544 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4437.191544 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24100.485166 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24100.485166 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24100.485166 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24100.485166 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1982,38 +2069,80 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 8777296 # Number of BP lookups -system.cpu1.branchPred.condPredicted 7163659 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 407085 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 5785994 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 4951432 # Number of BTB hits +system.cpu1.branchPred.lookups 9295999 # Number of BP lookups +system.cpu1.branchPred.condPredicted 7633656 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 416141 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 5924050 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 5051274 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 85.576169 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 773226 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 42749 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 85.267241 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 796895 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 43453 # Number of incorrect RAS predictions. +system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 42697243 # DTB read hits -system.cpu1.dtb.read_misses 36228 # DTB read misses -system.cpu1.dtb.write_hits 6821056 # DTB write hits -system.cpu1.dtb.write_misses 10680 # DTB write misses +system.cpu1.dtb.read_hits 42971577 # DTB read hits +system.cpu1.dtb.read_misses 38230 # DTB read misses +system.cpu1.dtb.write_hits 6978417 # DTB write hits +system.cpu1.dtb.write_misses 10824 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2016 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 2677 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 313 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 1922 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 2766 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 281 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 642 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 42733471 # DTB read accesses -system.cpu1.dtb.write_accesses 6831736 # DTB write accesses +system.cpu1.dtb.perms_faults 681 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 43009807 # DTB read accesses +system.cpu1.dtb.write_accesses 6989241 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 49518299 # DTB hits -system.cpu1.dtb.misses 46908 # DTB misses -system.cpu1.dtb.accesses 49565207 # DTB accesses -system.cpu1.itb.inst_hits 7578630 # ITB inst hits -system.cpu1.itb.inst_misses 5358 # ITB inst misses +system.cpu1.dtb.hits 49949994 # DTB hits +system.cpu1.dtb.misses 49054 # DTB misses +system.cpu1.dtb.accesses 49999048 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.itb.inst_hits 7718441 # ITB inst hits +system.cpu1.itb.inst_misses 5545 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -2022,114 +2151,114 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1531 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1355 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1501 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1449 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 7583988 # ITB inst accesses -system.cpu1.itb.hits 7578630 # DTB hits -system.cpu1.itb.misses 5358 # DTB misses -system.cpu1.itb.accesses 7583988 # DTB accesses -system.cpu1.numCycles 409868912 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 7723986 # ITB inst accesses +system.cpu1.itb.hits 7718441 # DTB hits +system.cpu1.itb.misses 5545 # DTB misses +system.cpu1.itb.accesses 7723986 # DTB accesses +system.cpu1.numCycles 413843853 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 18867977 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 60276924 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 8777296 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 5724658 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 13120224 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3305222 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 63128 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 78446194 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 5050 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 41923 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 1438516 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 233 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 7576833 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 547191 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2712 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 114243922 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.645142 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.969298 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 19379988 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 61315433 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 9295999 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 5848169 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 13365504 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3344948 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 69502 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 81000911 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 5955 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 40728 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 1501346 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 201 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 7716683 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 552961 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2911 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 117651923 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.637947 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.959423 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 101131185 88.52% 88.52% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 796172 0.70% 89.22% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 937688 0.82% 90.04% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1689020 1.48% 91.52% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1395475 1.22% 92.74% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 568258 0.50% 93.24% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1928403 1.69% 94.93% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 410429 0.36% 95.28% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 5387292 4.72% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 104293797 88.65% 88.65% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 816533 0.69% 89.34% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 959642 0.82% 90.16% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1712278 1.46% 91.61% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1420540 1.21% 92.82% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 586826 0.50% 93.32% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1954913 1.66% 94.98% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 421869 0.36% 95.34% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 5485525 4.66% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 114243922 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.021415 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.147064 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 20194584 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 79395702 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 11966487 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 522966 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2164183 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1104463 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 98170 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 69803405 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 327162 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 2164183 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 21384110 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 34428627 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 40773355 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 11205851 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 4287796 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 65891244 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 18827 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 669159 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 3045569 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 1057 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 69207054 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 302452168 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 280640301 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 6501 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 49057788 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 20149266 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 444930 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 388060 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 7871220 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 12589854 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 7931577 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1030582 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1486229 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 60667262 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1158299 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 87712047 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 93594 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 13406861 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 35899906 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 277508 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 114243922 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.767761 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.513174 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 117651923 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.022463 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.148161 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 20970716 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 81766548 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 11917801 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 808551 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2188307 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1138241 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 101191 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 71099803 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 336135 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 2188307 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 22164827 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 33899952 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 43340583 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 11475244 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 4583010 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 67141114 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 152 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 681863 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 3070840 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 445 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 70764915 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 313106059 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 286755701 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 6517 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 50418755 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 20346160 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 765693 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 705478 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 8425217 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 12844634 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 8117566 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1057819 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1511606 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 61861483 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1182497 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 88912346 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 94590 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 13560397 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 36234299 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 282991 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 117651923 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.755724 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.498826 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 84413448 73.89% 73.89% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 8278708 7.25% 81.14% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4125885 3.61% 84.75% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3695285 3.23% 87.98% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 10373691 9.08% 97.06% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1966586 1.72% 98.78% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1039954 0.91% 99.69% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 274624 0.24% 99.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 75741 0.07% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 86792358 73.77% 73.77% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 9289300 7.90% 81.67% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4170595 3.54% 85.21% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3605495 3.06% 88.28% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 10372617 8.82% 97.09% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1993778 1.69% 98.79% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1066938 0.91% 99.69% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 282351 0.24% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 78491 0.07% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 114243922 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 117651923 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 32139 0.41% 0.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 997 0.01% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 32498 0.41% 0.41% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 992 0.01% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.42% # attempts to use FU when none available @@ -2157,406 +2286,405 @@ system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.42% # at system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 7551678 95.88% 96.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 291209 3.70% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 7572169 95.70% 96.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 306556 3.87% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 314062 0.36% 0.36% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 36599204 41.73% 42.08% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 59264 0.07% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 9 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 1 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 7 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1508 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 43568617 49.67% 91.83% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7169368 8.17% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 14270 0.02% 0.02% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 37625981 42.32% 42.33% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 61252 0.07% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 9 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 6 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1700 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 43860086 49.33% 91.73% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7349035 8.27% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 87712047 # Type of FU issued -system.cpu1.iq.rate 0.214000 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 7876023 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.089794 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 297668917 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 75240910 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 53134013 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 15426 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 7990 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6798 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 95265766 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 8242 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 342419 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 88912346 # Type of FU issued +system.cpu1.iq.rate 0.214845 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 7912215 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.088989 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 303516932 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 76613298 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 54268341 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 15366 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 8022 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6803 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 96802135 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 8156 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 354682 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2834348 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 3679 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 17028 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1091492 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2862502 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 4198 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 17495 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1113245 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 31919677 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 675013 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 31965664 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 675731 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2164183 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 26656099 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 359793 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 61930029 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 112185 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 12589854 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 7931577 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 869499 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 63855 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3879 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 17028 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 201052 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 154389 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 355441 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 85989380 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 43067298 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1722667 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 2188307 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 26389520 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 363046 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 63147070 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 115346 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 12844634 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 8117566 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 886491 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 65999 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3974 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 17495 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 203953 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 158404 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 362357 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 87176512 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 43353711 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1735834 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 104468 # number of nop insts executed -system.cpu1.iew.exec_refs 50174734 # number of memory reference insts executed -system.cpu1.iew.exec_branches 6912361 # Number of branches executed -system.cpu1.iew.exec_stores 7107436 # Number of stores executed -system.cpu1.iew.exec_rate 0.209797 # Inst execution rate -system.cpu1.iew.wb_sent 85230326 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 53140811 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 29705560 # num instructions producing a value -system.cpu1.iew.wb_consumers 52974804 # num instructions consuming a value +system.cpu1.iew.exec_nop 103090 # number of nop insts executed +system.cpu1.iew.exec_refs 50638153 # number of memory reference insts executed +system.cpu1.iew.exec_branches 7380246 # Number of branches executed +system.cpu1.iew.exec_stores 7284442 # Number of stores executed +system.cpu1.iew.exec_rate 0.210651 # Inst execution rate +system.cpu1.iew.wb_sent 86413088 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 54275144 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 30296614 # num instructions producing a value +system.cpu1.iew.wb_consumers 53882453 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.129653 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.560749 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.131149 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.562272 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 13285222 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 880791 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 310591 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 112079739 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.429663 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.397726 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 13436842 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 899506 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 316660 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 115463616 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.426258 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.378914 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 95362610 85.08% 85.08% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 8223786 7.34% 92.42% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2087568 1.86% 94.28% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1250330 1.12% 95.40% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1251085 1.12% 96.52% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 572828 0.51% 97.03% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 991388 0.88% 97.91% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 531334 0.47% 98.39% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1808810 1.61% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 97442898 84.39% 84.39% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 9592965 8.31% 92.70% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2168696 1.88% 94.58% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1301481 1.13% 95.71% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 990246 0.86% 96.56% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 587576 0.51% 97.07% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 1009945 0.87% 97.95% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 534541 0.46% 98.41% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1835268 1.59% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 112079739 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 38065286 # Number of instructions committed -system.cpu1.commit.committedOps 48156538 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 115463616 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 38874177 # Number of instructions committed +system.cpu1.commit.committedOps 49217265 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 16595591 # Number of memory references committed -system.cpu1.commit.loads 9755506 # Number of loads committed -system.cpu1.commit.membars 190120 # Number of memory barriers committed -system.cpu1.commit.branches 5967745 # Number of branches committed +system.cpu1.commit.refs 16986453 # Number of memory references committed +system.cpu1.commit.loads 9982132 # Number of loads committed +system.cpu1.commit.membars 195521 # Number of memory barriers committed +system.cpu1.commit.branches 6425226 # Number of branches committed system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 42691339 # Number of committed integer instructions. -system.cpu1.commit.function_calls 534627 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1808810 # number cycles where commit BW limit reached +system.cpu1.commit.int_insts 43929395 # Number of committed integer instructions. +system.cpu1.commit.function_calls 553319 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1835268 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 170668638 # The number of ROB reads -system.cpu1.rob.rob_writes 125130415 # The number of ROB writes -system.cpu1.timesIdled 1414400 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 295624990 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 1799026779 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 37995647 # Number of Instructions Simulated -system.cpu1.committedOps 48086899 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 37995647 # Number of Instructions Simulated -system.cpu1.cpi 10.787260 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 10.787260 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.092702 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.092702 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 384897666 # number of integer regfile reads -system.cpu1.int_regfile_writes 55271640 # number of integer regfile writes -system.cpu1.fp_regfile_reads 5031 # number of floating regfile reads -system.cpu1.fp_regfile_writes 2324 # number of floating regfile writes -system.cpu1.misc_regfile_reads 18630847 # number of misc regfile reads -system.cpu1.misc_regfile_writes 405526 # number of misc regfile writes -system.cpu1.icache.tags.replacements 595825 # number of replacements -system.cpu1.icache.tags.tagsinuse 480.685801 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 6935518 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 596337 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 11.630199 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 74918873000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 480.685801 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.938839 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.938839 # Average percentage of cache occupancy +system.cpu1.rob.rob_reads 175215898 # The number of ROB reads +system.cpu1.rob.rob_writes 127579322 # The number of ROB writes +system.cpu1.timesIdled 1429072 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 296191930 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 4796799037 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 38804538 # Number of Instructions Simulated +system.cpu1.committedOps 49147626 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 38804538 # Number of Instructions Simulated +system.cpu1.cpi 10.664831 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 10.664831 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.093766 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.093766 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 391691607 # number of integer regfile reads +system.cpu1.int_regfile_writes 56383706 # number of integer regfile writes +system.cpu1.fp_regfile_reads 5043 # number of floating regfile reads +system.cpu1.fp_regfile_writes 2316 # number of floating regfile writes +system.cpu1.misc_regfile_reads 202850334 # number of misc regfile reads +system.cpu1.misc_regfile_writes 723182 # number of misc regfile writes +system.cpu1.icache.tags.replacements 614906 # number of replacements +system.cpu1.icache.tags.tagsinuse 498.718219 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 7054617 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 615418 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 11.463131 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 74929846000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.718219 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974059 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.974059 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 510 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 8173146 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 8173146 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 6935518 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 6935518 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 6935518 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 6935518 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 6935518 # number of overall hits -system.cpu1.icache.overall_hits::total 6935518 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 641267 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 641267 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 641267 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 641267 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 641267 # number of overall misses -system.cpu1.icache.overall_misses::total 641267 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8704460293 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 8704460293 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 8704460293 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 8704460293 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 8704460293 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 8704460293 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 7576785 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 7576785 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 7576785 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 7576785 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 7576785 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 7576785 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.084636 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.084636 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.084636 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.084636 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.084636 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.084636 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13573.847232 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13573.847232 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13573.847232 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13573.847232 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13573.847232 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13573.847232 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 2595 # number of cycles access was blocked +system.cpu1.icache.tags.tag_accesses 8332076 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 8332076 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 7054617 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 7054617 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 7054617 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 7054617 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 7054617 # number of overall hits +system.cpu1.icache.overall_hits::total 7054617 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 662013 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 662013 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 662013 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 662013 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 662013 # number of overall misses +system.cpu1.icache.overall_misses::total 662013 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8999563943 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 8999563943 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 8999563943 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 8999563943 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 8999563943 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 8999563943 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 7716630 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 7716630 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 7716630 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 7716630 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 7716630 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 7716630 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.085790 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.085790 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.085790 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.085790 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.085790 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.085790 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13594.240510 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13594.240510 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13594.240510 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13594.240510 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13594.240510 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13594.240510 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 3570 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 176 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 201 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.744318 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 17.761194 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 44906 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 44906 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 44906 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 44906 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 44906 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 44906 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 596361 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 596361 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 596361 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 596361 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 596361 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 596361 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7105400062 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 7105400062 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7105400062 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 7105400062 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7105400062 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 7105400062 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3356250 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3356250 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3356250 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 3356250 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.078709 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.078709 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.078709 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.078709 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.078709 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.078709 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11914.595458 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11914.595458 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11914.595458 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11914.595458 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11914.595458 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11914.595458 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 46567 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 46567 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 46567 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 46567 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 46567 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 46567 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 615446 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 615446 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 615446 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 615446 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 615446 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 615446 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7343690408 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 7343690408 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7343690408 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 7343690408 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7343690408 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 7343690408 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3568500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3568500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3568500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 3568500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.079756 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.079756 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.079756 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.079756 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.079756 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.079756 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11932.306665 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11932.306665 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11932.306665 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11932.306665 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11932.306665 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11932.306665 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 360794 # number of replacements -system.cpu1.dcache.tags.tagsinuse 473.291027 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 12676660 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 361148 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 35.101011 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 70967078000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 473.291027 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.924397 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.924397 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 354 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 58866831 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 58866831 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 8309635 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 8309635 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4139080 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4139080 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 97568 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 97568 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 94890 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 94890 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 12448715 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 12448715 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 12448715 # number of overall hits -system.cpu1.dcache.overall_hits::total 12448715 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 397211 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 397211 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1557491 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1557491 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13987 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 13987 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10584 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10584 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 1954702 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 1954702 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 1954702 # number of overall misses -system.cpu1.dcache.overall_misses::total 1954702 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6036826508 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 6036826508 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 80166814063 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 80166814063 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 129072992 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 129072992 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 53027415 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 53027415 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 86203640571 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 86203640571 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 86203640571 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 86203640571 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 8706846 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 8706846 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 5696571 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 5696571 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 111555 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 111555 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105474 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 105474 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 14403417 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 14403417 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 14403417 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 14403417 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045621 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.045621 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.273409 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.273409 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.125382 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.125382 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100347 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100347 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135711 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.135711 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135711 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.135711 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15198.034566 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15198.034566 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 51471.767133 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 51471.767133 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9228.068349 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9228.068349 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5010.148810 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5010.148810 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 44100.656044 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 44100.656044 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 44100.656044 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 44100.656044 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 29197 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 19426 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 3289 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 168 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.877166 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 115.630952 # average number of cycles each access was blocked +system.cpu1.dcache.tags.replacements 363287 # number of replacements +system.cpu1.dcache.tags.tagsinuse 485.536511 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 13021437 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 363669 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 35.805738 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 70976822000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 485.536511 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.948313 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.948313 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 382 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 382 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.746094 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 60298440 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 60298440 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 8515057 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 8515057 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4269820 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4269820 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 99795 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 99795 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 97086 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 97086 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 12784877 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 12784877 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 12784877 # number of overall hits +system.cpu1.dcache.overall_hits::total 12784877 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 402462 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 402462 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1568055 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1568055 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14174 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 14174 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10915 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10915 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 1970517 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 1970517 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 1970517 # number of overall misses +system.cpu1.dcache.overall_misses::total 1970517 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6127843210 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 6127843210 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 79461121233 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 79461121233 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 130724743 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 130724743 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 58221587 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 58221587 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 85588964443 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 85588964443 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 85588964443 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 85588964443 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 8917519 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 8917519 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 5837875 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 5837875 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 113969 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 113969 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 108001 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 108001 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 14755394 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 14755394 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 14755394 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 14755394 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045132 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.045132 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.268600 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.268600 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.124367 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.124367 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.101064 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.101064 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.133546 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.133546 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.133546 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.133546 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15225.892656 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15225.892656 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 50674.957979 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 50674.957979 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9222.854734 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9222.854734 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5334.089510 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5334.089510 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 43434.775971 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 43434.775971 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 43434.775971 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 43434.775971 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 28687 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 20050 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 3274 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 174 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.762065 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 115.229885 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 324862 # number of writebacks -system.cpu1.dcache.writebacks::total 324862 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 168849 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 168849 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1395866 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 1395866 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1456 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1456 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1564715 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1564715 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1564715 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1564715 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 228362 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 228362 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161625 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 161625 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12531 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12531 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10581 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10581 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 389987 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 389987 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 389987 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 389987 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2843265804 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2843265804 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 7240277216 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 7240277216 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 88160756 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 88160756 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31863585 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31863585 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 10083543020 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 10083543020 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 10083543020 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 10083543020 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168925167755 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168925167755 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25834747063 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25834747063 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 194759914818 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 194759914818 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026228 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026228 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028372 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028372 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112330 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112330 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100319 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100319 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027076 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.027076 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027076 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.027076 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12450.695843 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12450.695843 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 44796.765451 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 44796.765451 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7035.412657 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7035.412657 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3011.396371 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3011.396371 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 25856.100383 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 25856.100383 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 25856.100383 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 25856.100383 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 327819 # number of writebacks +system.cpu1.dcache.writebacks::total 327819 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 171130 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 171130 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1404670 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1404670 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1454 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1454 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1575800 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1575800 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1575800 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1575800 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 231332 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 231332 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 163385 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 163385 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12720 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12720 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10915 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10915 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 394717 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 394717 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 394717 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 394717 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2884558137 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2884558137 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 7099464771 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 7099464771 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89380256 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89380256 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 36390413 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 36390413 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9984022908 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 9984022908 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9984022908 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 9984022908 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169231255506 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169231255506 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25855700445 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25855700445 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 195086955951 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 195086955951 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025941 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025941 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027987 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027987 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.111609 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.111609 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.101064 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.101064 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026751 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026751 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026751 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026751 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12469.343355 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12469.343355 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 43452.365707 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 43452.365707 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7026.749686 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7026.749686 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3333.981951 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3333.981951 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 25294.129485 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 25294.129485 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 25294.129485 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 25294.129485 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -2580,18 +2708,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 612762276058 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 612762276058 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 612762276058 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 612762276058 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1519279146805 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1519279146805 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1519279146805 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1519279146805 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 41714 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 42657 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 48863 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 50405 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini index 276d3e895..9bc002187 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini @@ -14,6 +14,7 @@ children=bridge cf0 clk_domain cpu cpu_clk_domain intrctrl iobus iocache membus atags_addr=256 boot_loader=/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain dtb_filename= @@ -22,9 +23,16 @@ enable_context_switch_stats_dump=false eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 +have_generic_timer=false +have_large_asid_64=false +have_lpae=false +have_security=false +have_virtualization=false +highest_el_is_64=false init_param=0 kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 +load_offset=0 machine_type=RealView_PBX mem_mode=timing mem_ranges=0:134217727 @@ -33,7 +41,9 @@ multi_proc=true num_work_ids=16 panic_on_oops=true panic_on_panic=true +phys_addr_range_64=40 readfile=tests/halt.sh +reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -86,7 +96,7 @@ voltage_domain=system.voltage_domain [system.cpu] type=DerivO3CPU -children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer +children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer LFSTSize=1024 LQEntries=32 LSQCheckLoads=true @@ -112,6 +122,7 @@ dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 fetchBufferSize=64 @@ -130,6 +141,7 @@ interrupts=system.cpu.interrupts isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -224,10 +236,35 @@ hit_latency=2 sequential_access=false size=32768 +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[5] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -235,6 +272,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -589,24 +627,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[4] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -614,6 +688,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -662,7 +737,7 @@ system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port [system.cpu.tracer] type=ExeTracer diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr index 41742298b..9dee17aa2 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr @@ -11,5 +11,3 @@ warn: instruction 'mcr dccimvac' unimplemented warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented warn: LCD dual screen mode not supported -warn: instruction 'mcr icialluis' unimplemented -warn: instruction 'mcr bpiallis' unimplemented diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout index d1ec33d4f..9a2da36f9 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout @@ -1,12 +1,14 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 23 2014 00:04:18 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 18:42:01 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 + 0: system.cpu.isa: ISA system set to: 0x6dd8800 0x6dd8800 info: Using bootloader at address 0x80000000 +info: Using kernel entry physical address at 0x8000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2525131633500 because m5_exit instruction encountered +Exiting @ tick 2526146947500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 6bfde3aab..bbb1c38b2 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,136 +1,136 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.525132 # Number of seconds simulated -sim_ticks 2525131633500 # Number of ticks simulated -final_tick 2525131633500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.526147 # Number of seconds simulated +sim_ticks 2526146947500 # Number of ticks simulated +final_tick 2526146947500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 76415 # Simulator instruction rate (inst/s) -host_op_rate 98325 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3199664494 # Simulator tick rate (ticks/s) -host_mem_usage 402400 # Number of bytes of host memory used -host_seconds 789.19 # Real time elapsed on the host -sim_insts 60305678 # Number of instructions simulated -sim_ops 77596684 # Number of ops (including micro ops) simulated +host_inst_rate 69975 # Simulator instruction rate (inst/s) +host_op_rate 90038 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2931166527 # Simulator tick rate (ticks/s) +host_mem_usage 424336 # Number of bytes of host memory used +host_seconds 861.82 # Real time elapsed on the host +sim_insts 60306154 # Number of instructions simulated +sim_ops 77597242 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 2688 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3328 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 796928 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9094736 # Number of bytes read from this memory -system.physmem.bytes_read::total 129432144 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 796928 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 796928 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3784384 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 796736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9093720 # Number of bytes read from this memory +system.physmem.bytes_read::total 129431576 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 796736 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 796736 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3782528 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6800456 # Number of bytes written to this memory +system.physmem.bytes_written::total 6798600 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 42 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 52 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12452 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142139 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096843 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59131 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 12449 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142125 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096836 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59102 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813149 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47339181 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1064 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 813120 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47320155 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1317 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 315599 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3601688 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51257583 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 315599 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 315599 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1498688 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1194422 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2693110 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1498688 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47339181 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1064 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 315396 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3599838 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51236756 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 315396 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 315396 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1497351 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1193942 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2691292 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1497351 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47320155 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1317 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 315599 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4796110 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53950692 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15096843 # Number of read requests accepted -system.physmem.writeReqs 813149 # Number of write requests accepted -system.physmem.readBursts 15096843 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 813149 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 963738752 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 2459200 # Total number of bytes read from write queue -system.physmem.bytesWritten 6902144 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 129432144 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6800456 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 38425 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 705284 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4682 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 943580 # Per bank write bursts -system.physmem.perBankRdBursts::1 943152 # Per bank write bursts -system.physmem.perBankRdBursts::2 939288 # Per bank write bursts -system.physmem.perBankRdBursts::3 939310 # Per bank write bursts -system.physmem.perBankRdBursts::4 943113 # Per bank write bursts -system.physmem.perBankRdBursts::5 943139 # Per bank write bursts -system.physmem.perBankRdBursts::6 939134 # Per bank write bursts -system.physmem.perBankRdBursts::7 938551 # Per bank write bursts -system.physmem.perBankRdBursts::8 944000 # Per bank write bursts -system.physmem.perBankRdBursts::9 943392 # Per bank write bursts -system.physmem.perBankRdBursts::10 938425 # Per bank write bursts -system.physmem.perBankRdBursts::11 937973 # Per bank write bursts -system.physmem.perBankRdBursts::12 943928 # Per bank write bursts -system.physmem.perBankRdBursts::13 943534 # Per bank write bursts -system.physmem.perBankRdBursts::14 939230 # Per bank write bursts -system.physmem.perBankRdBursts::15 938669 # Per bank write bursts -system.physmem.perBankWrBursts::0 6703 # Per bank write bursts -system.physmem.perBankWrBursts::1 6464 # Per bank write bursts -system.physmem.perBankWrBursts::2 6595 # Per bank write bursts -system.physmem.perBankWrBursts::3 6634 # Per bank write bursts -system.physmem.perBankWrBursts::4 6559 # Per bank write bursts -system.physmem.perBankWrBursts::5 6792 # Per bank write bursts -system.physmem.perBankWrBursts::6 6793 # Per bank write bursts -system.physmem.perBankWrBursts::7 6730 # Per bank write bursts -system.physmem.perBankWrBursts::8 7130 # Per bank write bursts -system.physmem.perBankWrBursts::9 6877 # Per bank write bursts -system.physmem.perBankWrBursts::10 6539 # Per bank write bursts -system.physmem.perBankWrBursts::11 6181 # Per bank write bursts -system.physmem.perBankWrBursts::12 7151 # Per bank write bursts -system.physmem.perBankWrBursts::13 6766 # Per bank write bursts -system.physmem.perBankWrBursts::14 7035 # Per bank write bursts -system.physmem.perBankWrBursts::15 6897 # Per bank write bursts +system.physmem.bw_total::cpu.inst 315396 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4793780 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53928049 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15096836 # Number of read requests accepted +system.physmem.writeReqs 813120 # Number of write requests accepted +system.physmem.readBursts 15096836 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 813120 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 963731584 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 2465920 # Total number of bytes read from write queue +system.physmem.bytesWritten 6899264 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 129431576 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6798600 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 38530 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 705302 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4683 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 943582 # Per bank write bursts +system.physmem.perBankRdBursts::1 943071 # Per bank write bursts +system.physmem.perBankRdBursts::2 939289 # Per bank write bursts +system.physmem.perBankRdBursts::3 939279 # Per bank write bursts +system.physmem.perBankRdBursts::4 943119 # Per bank write bursts +system.physmem.perBankRdBursts::5 943242 # Per bank write bursts +system.physmem.perBankRdBursts::6 939090 # Per bank write bursts +system.physmem.perBankRdBursts::7 938633 # Per bank write bursts +system.physmem.perBankRdBursts::8 943981 # Per bank write bursts +system.physmem.perBankRdBursts::9 943506 # Per bank write bursts +system.physmem.perBankRdBursts::10 938534 # Per bank write bursts +system.physmem.perBankRdBursts::11 937721 # Per bank write bursts +system.physmem.perBankRdBursts::12 943933 # Per bank write bursts +system.physmem.perBankRdBursts::13 943406 # Per bank write bursts +system.physmem.perBankRdBursts::14 939034 # Per bank write bursts +system.physmem.perBankRdBursts::15 938886 # Per bank write bursts +system.physmem.perBankWrBursts::0 6687 # Per bank write bursts +system.physmem.perBankWrBursts::1 6452 # Per bank write bursts +system.physmem.perBankWrBursts::2 6617 # Per bank write bursts +system.physmem.perBankWrBursts::3 6618 # Per bank write bursts +system.physmem.perBankWrBursts::4 6551 # Per bank write bursts +system.physmem.perBankWrBursts::5 6799 # Per bank write bursts +system.physmem.perBankWrBursts::6 6798 # Per bank write bursts +system.physmem.perBankWrBursts::7 6724 # Per bank write bursts +system.physmem.perBankWrBursts::8 7121 # Per bank write bursts +system.physmem.perBankWrBursts::9 6870 # Per bank write bursts +system.physmem.perBankWrBursts::10 6536 # Per bank write bursts +system.physmem.perBankWrBursts::11 6184 # Per bank write bursts +system.physmem.perBankWrBursts::12 7152 # Per bank write bursts +system.physmem.perBankWrBursts::13 6752 # Per bank write bursts +system.physmem.perBankWrBursts::14 7039 # Per bank write bursts +system.physmem.perBankWrBursts::15 6901 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2525130505500 # Total gap between requests +system.physmem.totGap 2526145872500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 36 # Read request sizes (log2) +system.physmem.readPktSize::2 38 # Read request sizes (log2) system.physmem.readPktSize::3 14942208 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 154599 # Read request sizes (log2) +system.physmem.readPktSize::6 154590 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 754018 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 59131 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1173486 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1117689 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1073548 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3627714 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2609756 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2597217 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2603662 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 53378 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 57682 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 21065 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 20906 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 20772 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 20512 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 20369 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 20252 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 20160 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 238 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59102 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1174955 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1121426 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1077218 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3628637 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2607777 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2593781 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2599800 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 53131 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 57465 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 21079 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 20890 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 20765 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 20515 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 20363 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 20256 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 20150 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 94 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -145,616 +145,621 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 4766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5445 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4889 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5098 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4856 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4880 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4887 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4810 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4807 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4811 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4797 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4789 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4789 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4794 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4797 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4825 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4820 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4809 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5448 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4902 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4875 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4866 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4857 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4818 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4808 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4790 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4794 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4798 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4790 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4786 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4809 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4807 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4795 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 86134 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 11268.950798 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 1000.903149 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 16775.480046 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-71 23607 27.41% 27.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-135 14081 16.35% 43.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-199 2628 3.05% 46.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-263 2075 2.41% 49.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-327 1317 1.53% 50.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-391 1250 1.45% 52.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-455 847 0.98% 53.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-519 989 1.15% 54.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-583 557 0.65% 54.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-647 603 0.70% 55.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-711 514 0.60% 56.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-775 583 0.68% 56.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-839 284 0.33% 57.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-903 264 0.31% 57.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-967 155 0.18% 57.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1031 634 0.74% 58.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1095 90 0.10% 58.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1159 143 0.17% 58.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1223 77 0.09% 58.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1287 121 0.14% 59.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1351 52 0.06% 59.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1415 516 0.60% 59.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1479 33 0.04% 59.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1543 269 0.31% 60.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1607 22 0.03% 60.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1671 94 0.11% 60.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1735 18 0.02% 60.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1799 142 0.16% 60.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1863 22 0.03% 60.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1927 57 0.07% 60.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1991 13 0.02% 60.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2055 390 0.45% 60.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2119 6 0.01% 60.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2183 32 0.04% 60.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2247 13 0.02% 60.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2311 120 0.14% 61.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2375 5 0.01% 61.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2439 22 0.03% 61.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2503 8 0.01% 61.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2567 107 0.12% 61.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2631 7 0.01% 61.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2695 24 0.03% 61.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2759 11 0.01% 61.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2823 86 0.10% 61.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2887 7 0.01% 61.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2951 27 0.03% 61.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 86110 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 11271.974916 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 1003.850407 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 16772.129499 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 23407 27.18% 27.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 14160 16.44% 43.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 2694 3.13% 46.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 2155 2.50% 49.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 1262 1.47% 50.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 1178 1.37% 52.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 892 1.04% 53.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 1078 1.25% 54.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 591 0.69% 55.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 609 0.71% 55.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 535 0.62% 56.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-775 547 0.64% 57.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-839 279 0.32% 57.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-903 297 0.34% 57.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 152 0.18% 57.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 456 0.53% 58.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 120 0.14% 58.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1159 137 0.16% 58.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1223 61 0.07% 58.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1287 169 0.20% 58.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1351 52 0.06% 59.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1415 508 0.59% 59.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1479 23 0.03% 59.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1543 260 0.30% 59.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1607 13 0.02% 59.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1671 93 0.11% 60.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1735 18 0.02% 60.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1799 141 0.16% 60.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1863 16 0.02% 60.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1927 46 0.05% 60.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1991 16 0.02% 60.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2055 376 0.44% 60.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2119 11 0.01% 60.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2183 34 0.04% 60.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2247 13 0.02% 60.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2311 70 0.08% 60.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2375 7 0.01% 60.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2439 29 0.03% 60.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2503 6 0.01% 60.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2567 165 0.19% 61.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2631 6 0.01% 61.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2695 16 0.02% 61.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2759 8 0.01% 61.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2823 175 0.20% 61.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2887 13 0.02% 61.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2951 17 0.02% 61.45% # Bytes accessed per row activation system.physmem.bytesPerActivate::3008-3015 4 0.00% 61.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3079 358 0.42% 61.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3143 7 0.01% 61.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3207 18 0.02% 61.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3271 8 0.01% 61.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3335 154 0.18% 62.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3399 9 0.01% 62.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3463 15 0.02% 62.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3527 8 0.01% 62.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3591 31 0.04% 62.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3655 4 0.00% 62.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3719 11 0.01% 62.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3783 7 0.01% 62.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3847 39 0.05% 62.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3911 9 0.01% 62.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3975 15 0.02% 62.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4039 10 0.01% 62.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4103 368 0.43% 62.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4167 4 0.00% 62.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4231 15 0.02% 62.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4295 8 0.01% 62.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4359 165 0.19% 62.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4423 14 0.02% 62.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4487 12 0.01% 62.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4551 8 0.01% 62.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4615 92 0.11% 63.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4679 3 0.00% 63.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4743 8 0.01% 63.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4807 2 0.00% 63.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4871 95 0.11% 63.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4935 2 0.00% 63.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4999 16 0.02% 63.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5063 5 0.01% 63.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5127 379 0.44% 63.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5191 5 0.01% 63.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5255 10 0.01% 63.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5319 5 0.01% 63.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5383 88 0.10% 63.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5447 11 0.01% 63.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5511 21 0.02% 63.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5575 3 0.00% 63.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5639 146 0.17% 63.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5703 2 0.00% 63.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5767 8 0.01% 64.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5831 2 0.00% 64.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5895 64 0.07% 64.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5959 1 0.00% 64.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6023 13 0.02% 64.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6087 11 0.01% 64.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6151 283 0.33% 64.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6215 1 0.00% 64.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6279 8 0.01% 64.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6343 2 0.00% 64.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6407 88 0.10% 64.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6471 4 0.00% 64.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6535 11 0.01% 64.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6599 6 0.01% 64.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6663 153 0.18% 64.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6727 1 0.00% 64.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6791 14 0.02% 64.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6855 7 0.01% 64.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6919 78 0.09% 64.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6983 2 0.00% 64.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7047 9 0.01% 64.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7111 4 0.00% 64.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7175 368 0.43% 65.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7239 2 0.00% 65.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7303 11 0.01% 65.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7367 12 0.01% 65.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7431 136 0.16% 65.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7495 5 0.01% 65.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3079 306 0.36% 61.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3143 11 0.01% 61.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3207 15 0.02% 61.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3271 9 0.01% 61.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3335 94 0.11% 61.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3399 11 0.01% 61.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3463 22 0.03% 61.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3527 5 0.01% 62.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3591 99 0.11% 62.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3655 9 0.01% 62.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3719 12 0.01% 62.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3783 8 0.01% 62.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3847 93 0.11% 62.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3911 7 0.01% 62.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3975 21 0.02% 62.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4039 5 0.01% 62.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4103 365 0.42% 62.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4167 6 0.01% 62.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4231 12 0.01% 62.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4295 7 0.01% 62.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4359 91 0.11% 62.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4423 13 0.02% 62.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4487 7 0.01% 62.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4551 5 0.01% 62.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4615 21 0.02% 62.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4679 3 0.00% 62.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4743 11 0.01% 62.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4807 9 0.01% 62.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4871 161 0.19% 63.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4935 5 0.01% 63.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4999 16 0.02% 63.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5063 7 0.01% 63.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5127 409 0.47% 63.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5191 11 0.01% 63.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5255 9 0.01% 63.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5319 13 0.02% 63.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5383 56 0.07% 63.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5447 5 0.01% 63.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5511 15 0.02% 63.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5575 8 0.01% 63.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5639 79 0.09% 63.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5703 2 0.00% 63.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5767 10 0.01% 63.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5831 9 0.01% 63.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5895 142 0.16% 64.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5959 3 0.00% 64.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6023 18 0.02% 64.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6087 9 0.01% 64.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6151 348 0.40% 64.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6215 6 0.01% 64.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6279 7 0.01% 64.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6343 3 0.00% 64.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6407 23 0.03% 64.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6471 1 0.00% 64.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6535 7 0.01% 64.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6599 4 0.00% 64.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6663 95 0.11% 64.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6791 17 0.02% 64.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6855 3 0.00% 64.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6919 100 0.12% 64.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7047 11 0.01% 64.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7111 7 0.01% 64.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7175 484 0.56% 65.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7239 2 0.00% 65.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7303 7 0.01% 65.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7367 12 0.01% 65.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7431 86 0.10% 65.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7495 3 0.00% 65.50% # Bytes accessed per row activation system.physmem.bytesPerActivate::7552-7559 9 0.01% 65.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7623 1 0.00% 65.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7687 88 0.10% 65.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7751 2 0.00% 65.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7815 9 0.01% 65.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7879 5 0.01% 65.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7943 84 0.10% 65.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8007 1 0.00% 65.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8071 11 0.01% 65.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7623 2 0.00% 65.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7687 27 0.03% 65.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7815 10 0.01% 65.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7879 1 0.00% 65.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7943 155 0.18% 65.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8007 1 0.00% 65.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8071 8 0.01% 65.75% # Bytes accessed per row activation system.physmem.bytesPerActivate::8128-8135 1 0.00% 65.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8199 389 0.45% 66.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8256-8263 1 0.00% 66.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8320-8327 2 0.00% 66.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8455 79 0.09% 66.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8640-8647 1 0.00% 66.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8711 78 0.09% 66.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8832-8839 1 0.00% 66.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8896-8903 1 0.00% 66.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8967 130 0.15% 66.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9088-9095 1 0.00% 66.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9223 355 0.41% 66.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9344-9351 2 0.00% 66.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9479 73 0.08% 67.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9536-9543 1 0.00% 67.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9600-9607 4 0.00% 67.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9664-9671 1 0.00% 67.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9735 140 0.16% 67.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9792-9799 2 0.00% 67.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9920-9927 1 0.00% 67.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9991 79 0.09% 67.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10112-10119 4 0.00% 67.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10247 272 0.32% 67.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10432-10439 1 0.00% 67.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10503 15 0.02% 67.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10560-10567 1 0.00% 67.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10624-10631 1 0.00% 67.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10759 132 0.15% 67.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10944-10951 3 0.00% 67.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11015 75 0.09% 67.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11271 373 0.43% 68.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11392-11399 1 0.00% 68.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11527 86 0.10% 68.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11584-11591 2 0.00% 68.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11648-11655 1 0.00% 68.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11712-11719 2 0.00% 68.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11783 77 0.09% 68.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11904-11911 2 0.00% 68.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11968-11975 1 0.00% 68.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12039 144 0.17% 68.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12096-12103 1 0.00% 68.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12160-12167 4 0.00% 68.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12295 340 0.39% 69.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12352-12359 1 0.00% 69.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12416-12423 2 0.00% 69.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12480-12487 1 0.00% 69.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12551 26 0.03% 69.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12807 18 0.02% 69.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12864-12871 1 0.00% 69.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12928-12935 1 0.00% 69.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12992-12999 2 0.00% 69.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13063 146 0.17% 69.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13120-13127 1 0.00% 69.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13184-13191 2 0.00% 69.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13319 339 0.39% 69.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13575 74 0.09% 69.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13831 78 0.09% 69.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13888-13895 1 0.00% 69.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13952-13959 1 0.00% 69.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14087 87 0.10% 70.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14144-14151 2 0.00% 70.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14215 4 0.00% 70.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14343 340 0.39% 70.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14599 79 0.09% 70.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14720-14727 4 0.00% 70.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14855 86 0.10% 70.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14912-14919 2 0.00% 70.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14976-14983 1 0.00% 70.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15111 13 0.02% 70.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15232-15239 2 0.00% 70.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15296-15303 1 0.00% 70.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15367 405 0.47% 71.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15424-15431 1 0.00% 71.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15552-15559 1 0.00% 71.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15623 83 0.10% 71.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15680-15687 1 0.00% 71.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15879 89 0.10% 71.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16064-16071 1 0.00% 71.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16135 86 0.10% 71.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16256-16263 12 0.01% 71.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16391 642 0.75% 72.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16647 86 0.10% 72.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16704-16711 2 0.00% 72.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16768-16775 1 0.00% 72.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16903 84 0.10% 72.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17088-17095 1 0.00% 72.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17159 92 0.11% 72.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17280-17287 4 0.00% 72.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17344-17351 1 0.00% 72.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17415 410 0.48% 72.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17472-17479 2 0.00% 72.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17536-17543 3 0.00% 72.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17671 15 0.02% 72.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17728-17735 1 0.00% 72.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17792-17799 5 0.01% 72.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17856-17863 1 0.00% 72.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17927 86 0.10% 73.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17984-17991 1 0.00% 73.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18048-18055 1 0.00% 73.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18112-18119 2 0.00% 73.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18183 83 0.10% 73.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18304-18311 3 0.00% 73.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18439 331 0.38% 73.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18496-18503 1 0.00% 73.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18560-18567 1 0.00% 73.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18695 89 0.10% 73.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18880-18887 2 0.00% 73.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18944-18951 83 0.10% 73.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19136-19143 1 0.00% 73.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19207 74 0.09% 73.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19328-19335 3 0.00% 73.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19463 326 0.38% 74.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19520-19527 1 0.00% 74.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19584-19591 3 0.00% 74.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19648-19655 1 0.00% 74.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19719 138 0.16% 74.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19840-19847 1 0.00% 74.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19968-19975 15 0.02% 74.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20231 23 0.03% 74.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20288-20295 1 0.00% 74.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20352-20359 3 0.00% 74.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20487 336 0.39% 74.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20608-20615 1 0.00% 74.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20672-20679 2 0.00% 74.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20736-20743 143 0.17% 75.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20864-20871 3 0.00% 75.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-20999 73 0.08% 75.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21184-21191 1 0.00% 75.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21248-21255 89 0.10% 75.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21312-21319 1 0.00% 75.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21376-21383 3 0.00% 75.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21440-21447 1 0.00% 75.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21511 367 0.43% 75.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21568-21575 1 0.00% 75.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21632-21639 1 0.00% 75.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21767 76 0.09% 75.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21824-21831 1 0.00% 75.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21888-21895 5 0.01% 75.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22023 129 0.15% 75.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22144-22151 1 0.00% 75.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22279 14 0.02% 75.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22336-22343 1 0.00% 75.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22400-22407 3 0.00% 75.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22464-22471 2 0.00% 75.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22535 268 0.31% 76.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22720-22727 2 0.00% 76.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22791 78 0.09% 76.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22848-22855 1 0.00% 76.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22912-22919 1 0.00% 76.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22976-22983 2 0.00% 76.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23040-23047 143 0.17% 76.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23104-23111 1 0.00% 76.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23168-23175 1 0.00% 76.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23296-23303 77 0.09% 76.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23360-23367 3 0.00% 76.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23424-23431 2 0.00% 76.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23559 350 0.41% 76.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23680-23687 1 0.00% 76.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23808-23815 126 0.15% 77.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23936-23943 1 0.00% 77.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24000-24007 2 0.00% 77.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24071 74 0.09% 77.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24192-24199 2 0.00% 77.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24256-24263 1 0.00% 77.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24327 82 0.10% 77.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24448-24455 3 0.00% 77.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24583 270 0.31% 77.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24839 79 0.09% 77.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25024-25031 1 0.00% 77.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25088-25095 77 0.09% 77.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8199 378 0.44% 66.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8256-8263 1 0.00% 66.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8455 152 0.18% 66.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8711 21 0.02% 66.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8832-8839 2 0.00% 66.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8967 72 0.08% 66.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9024-9031 2 0.00% 66.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9088-9095 5 0.01% 66.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9152-9159 1 0.00% 66.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9223 466 0.54% 67.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9344-9351 1 0.00% 67.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9479 96 0.11% 67.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9536-9543 1 0.00% 67.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9735 85 0.10% 67.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9920-9927 1 0.00% 67.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9991 17 0.02% 67.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10112-10119 2 0.00% 67.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10247 345 0.40% 67.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10304-10311 1 0.00% 67.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10368-10375 1 0.00% 67.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10432-10439 1 0.00% 67.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10503 83 0.10% 67.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10759 68 0.08% 67.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10944-10951 1 0.00% 67.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11015 39 0.05% 67.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11136-11143 4 0.00% 67.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11271 396 0.46% 68.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11328-11335 2 0.00% 68.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11456-11463 1 0.00% 68.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11527 156 0.18% 68.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11584-11591 2 0.00% 68.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11783 8 0.01% 68.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11968-11975 1 0.00% 68.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12039 83 0.10% 68.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12160-12167 2 0.00% 68.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12224-12231 1 0.00% 68.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12295 336 0.39% 69.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12352-12359 1 0.00% 69.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12416-12423 1 0.00% 69.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12480-12487 1 0.00% 69.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12551 83 0.10% 69.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12672-12679 2 0.00% 69.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12736-12743 1 0.00% 69.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12807 81 0.09% 69.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12864-12871 1 0.00% 69.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12928-12935 2 0.00% 69.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13063 70 0.08% 69.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13184-13191 3 0.00% 69.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13248-13255 1 0.00% 69.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13319 277 0.32% 69.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13376-13383 1 0.00% 69.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13440-13447 3 0.00% 69.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13575 151 0.18% 69.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13696-13703 1 0.00% 69.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13831 132 0.15% 69.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14087 32 0.04% 70.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14215 2 0.00% 70.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14343 338 0.39% 70.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14464-14471 1 0.00% 70.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14528-14535 1 0.00% 70.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14599 77 0.09% 70.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14720-14727 2 0.00% 70.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14784-14791 1 0.00% 70.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14855 81 0.09% 70.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14919 1 0.00% 70.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15111 72 0.08% 70.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15239 2 0.00% 70.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15367 269 0.31% 71.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15424-15431 2 0.00% 71.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15488-15495 1 0.00% 71.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15623 83 0.10% 71.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15680-15687 1 0.00% 71.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15744-15751 3 0.00% 71.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15808-15815 1 0.00% 71.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15879 157 0.18% 71.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16000-16007 3 0.00% 71.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16135 129 0.15% 71.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16192-16199 1 0.00% 71.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16256-16263 7 0.01% 71.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16320-16327 2 0.00% 71.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16391 524 0.61% 72.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16512-16519 3 0.00% 72.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16647 130 0.15% 72.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16768-16775 2 0.00% 72.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16832-16839 3 0.00% 72.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16896-16903 155 0.18% 72.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16960-16967 3 0.00% 72.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17024-17031 1 0.00% 72.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17159 86 0.10% 72.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17216-17223 1 0.00% 72.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17280-17287 1 0.00% 72.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17344-17351 1 0.00% 72.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17415 268 0.31% 72.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17472-17479 3 0.00% 72.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17536-17543 1 0.00% 72.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17671 70 0.08% 72.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17927 80 0.09% 73.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17984-17991 2 0.00% 73.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18048-18055 2 0.00% 73.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18183 82 0.10% 73.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18240-18247 1 0.00% 73.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18304-18311 2 0.00% 73.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18439 328 0.38% 73.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18560-18567 1 0.00% 73.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18624-18631 1 0.00% 73.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18688-18695 35 0.04% 73.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18816-18823 1 0.00% 73.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18944-18951 133 0.15% 73.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19008-19015 1 0.00% 73.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19072-19079 2 0.00% 73.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19207 154 0.18% 73.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19328-19335 3 0.00% 73.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19392-19399 1 0.00% 73.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19463 281 0.33% 74.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19712-19719 67 0.08% 74.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19840-19847 1 0.00% 74.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19968-19975 79 0.09% 74.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20032-20039 1 0.00% 74.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20160-20167 1 0.00% 74.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20224-20231 87 0.10% 74.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20352-20359 4 0.00% 74.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20416-20423 1 0.00% 74.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20487 327 0.38% 74.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20608-20615 1 0.00% 74.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20736-20743 77 0.09% 74.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20992-20999 10 0.01% 74.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21056-21063 1 0.00% 74.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21120-21127 1 0.00% 74.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21184-21191 2 0.00% 74.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21248-21255 151 0.18% 75.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21376-21383 4 0.00% 75.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21440-21447 1 0.00% 75.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21511 401 0.47% 75.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21568-21575 1 0.00% 75.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21632-21639 1 0.00% 75.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21760-21767 39 0.05% 75.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21824-21831 2 0.00% 75.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21888-21895 1 0.00% 75.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22016-22023 65 0.08% 75.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22144-22151 2 0.00% 75.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22272-22279 85 0.10% 75.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22336-22343 2 0.00% 75.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22400-22407 4 0.00% 75.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22464-22471 1 0.00% 75.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22535 336 0.39% 76.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22592-22599 1 0.00% 76.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22656-22663 1 0.00% 76.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22784-22791 18 0.02% 76.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22912-22919 3 0.00% 76.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23040-23047 81 0.09% 76.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23104-23111 2 0.00% 76.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23168-23175 1 0.00% 76.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23232-23239 2 0.00% 76.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23296-23303 92 0.11% 76.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23360-23367 1 0.00% 76.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23424-23431 4 0.00% 76.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23488-23495 1 0.00% 76.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23559 463 0.54% 77.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23680-23687 1 0.00% 77.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23808-23815 70 0.08% 77.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23936-23943 1 0.00% 77.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24000-24007 1 0.00% 77.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24064-24071 19 0.02% 77.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24192-24199 1 0.00% 77.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24327 148 0.17% 77.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24384-24391 1 0.00% 77.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24448-24455 5 0.01% 77.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24583 262 0.30% 77.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24640-24647 1 0.00% 77.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24704-24711 3 0.00% 77.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24768-24775 2 0.00% 77.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24832-24839 150 0.17% 77.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24896-24903 1 0.00% 77.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24960-24967 2 0.00% 77.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25088-25095 20 0.02% 77.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25152-25159 1 0.00% 77.82% # Bytes accessed per row activation system.physmem.bytesPerActivate::25216-25223 2 0.00% 77.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25280-25287 1 0.00% 77.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25344-25351 133 0.15% 77.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25472-25479 2 0.00% 77.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25607 355 0.41% 78.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25728-25735 1 0.00% 78.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25856-25863 72 0.08% 78.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25984-25991 2 0.00% 78.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26112-26119 138 0.16% 78.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26176-26183 1 0.00% 78.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26240-26247 1 0.00% 78.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26304-26311 2 0.00% 78.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26375 79 0.09% 78.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26432-26439 1 0.00% 78.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26496-26503 2 0.00% 78.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26560-26567 1 0.00% 78.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26631 269 0.31% 79.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26688-26695 1 0.00% 79.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26752-26759 1 0.00% 79.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26816-26823 1 0.00% 79.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26880-26887 14 0.02% 79.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27008-27015 4 0.00% 79.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27072-27079 1 0.00% 79.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27143 130 0.15% 79.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27200-27207 1 0.00% 79.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27399 74 0.09% 79.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27520-27527 3 0.00% 79.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27584-27591 1 0.00% 79.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27655 367 0.43% 79.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27840-27847 1 0.00% 79.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27911 85 0.10% 79.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27968-27975 2 0.00% 79.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28032-28039 2 0.00% 79.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28096-28103 1 0.00% 79.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28160-28167 75 0.09% 79.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28288-28295 2 0.00% 79.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28352-28359 2 0.00% 79.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28423 143 0.17% 80.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28480-28487 2 0.00% 80.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28544-28551 4 0.00% 80.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28608-28615 1 0.00% 80.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28679 337 0.39% 80.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28736-28743 1 0.00% 80.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28864-28871 2 0.00% 80.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28935 26 0.03% 80.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28992-28999 1 0.00% 80.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29191 17 0.02% 80.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29248-29255 2 0.00% 80.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29312-29319 1 0.00% 80.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29447 139 0.16% 80.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29504-29511 3 0.00% 80.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29568-29575 4 0.00% 80.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25344-25351 73 0.08% 77.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25472-25479 2 0.00% 77.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25607 464 0.54% 78.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25728-25735 1 0.00% 78.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25792-25799 1 0.00% 78.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25856-25863 93 0.11% 78.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25984-25991 3 0.00% 78.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26048-26055 1 0.00% 78.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26112-26119 84 0.10% 78.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26176-26183 1 0.00% 78.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26240-26247 1 0.00% 78.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26304-26311 1 0.00% 78.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26375 18 0.02% 78.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26432-26439 1 0.00% 78.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26496-26503 5 0.01% 78.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26631 339 0.39% 79.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26880-26887 80 0.09% 79.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27008-27015 3 0.00% 79.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27136-27143 63 0.07% 79.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27200-27207 2 0.00% 79.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27399 47 0.05% 79.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27520-27527 2 0.00% 79.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27584-27591 2 0.00% 79.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27655 394 0.46% 79.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27776-27783 2 0.00% 79.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27840-27847 1 0.00% 79.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27911 150 0.17% 79.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28032-28039 1 0.00% 79.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28096-28103 1 0.00% 79.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28160-28167 8 0.01% 79.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28288-28295 2 0.00% 79.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28352-28359 1 0.00% 79.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28423 82 0.10% 80.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28480-28487 1 0.00% 80.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28544-28551 5 0.01% 80.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28608-28615 1 0.00% 80.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28679 329 0.38% 80.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28736-28743 2 0.00% 80.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28800-28807 3 0.00% 80.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28935 83 0.10% 80.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28992-28999 1 0.00% 80.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29120-29127 2 0.00% 80.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29191 82 0.10% 80.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29248-29255 1 0.00% 80.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29312-29319 2 0.00% 80.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29447 72 0.08% 80.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29504-29511 2 0.00% 80.74% # Bytes accessed per row activation system.physmem.bytesPerActivate::29632-29639 1 0.00% 80.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29703 329 0.38% 81.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29824-29831 2 0.00% 81.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29888-29895 2 0.00% 81.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-29959 70 0.08% 81.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30208-30215 79 0.09% 81.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30336-30343 1 0.00% 81.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30471 92 0.11% 81.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30592-30599 4 0.00% 81.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30656-30663 1 0.00% 81.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30727 327 0.38% 81.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30848-30855 4 0.00% 81.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30912-30919 2 0.00% 81.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-30983 84 0.10% 81.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31239 89 0.10% 82.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31360-31367 1 0.00% 82.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31424-31431 1 0.00% 82.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31488-31495 19 0.02% 82.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31552-31559 2 0.00% 82.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31616-31623 5 0.01% 82.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31680-31687 1 0.00% 82.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31751 406 0.47% 82.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31872-31879 1 0.00% 82.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32000-32007 83 0.10% 82.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32064-32071 1 0.00% 82.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32128-32135 2 0.00% 82.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32256-32263 82 0.10% 82.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32320-32327 1 0.00% 82.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32448-32455 2 0.00% 82.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32512-32519 93 0.11% 82.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32576-32583 1 0.00% 82.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32775 645 0.75% 83.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32832-32839 2 0.00% 83.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32896-32903 1 0.00% 83.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33031 83 0.10% 83.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33088-33095 1 0.00% 83.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33152-33159 1 0.00% 83.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33216-33223 2 0.00% 83.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33287 82 0.10% 83.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33408-33415 4 0.00% 83.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33472-33479 1 0.00% 83.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33543 95 0.11% 83.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33664-33671 1 0.00% 83.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33799 411 0.48% 84.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33984-33991 1 0.00% 84.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34048-34055 13 0.02% 84.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34112-34119 1 0.00% 84.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34304-34311 83 0.10% 84.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34432-34439 2 0.00% 84.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34560-34567 86 0.10% 84.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34688-34695 1 0.00% 84.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34823 328 0.38% 84.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35072-35079 86 0.10% 85.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35136-35143 1 0.00% 85.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35200-35207 1 0.00% 85.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35328-35335 76 0.09% 85.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35456-35463 3 0.00% 85.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35584-35591 72 0.08% 85.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35712-35719 1 0.00% 85.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35847 328 0.38% 85.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36096-36103 138 0.16% 85.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36224-36231 1 0.00% 85.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36352-36359 15 0.02% 85.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36480-36487 3 0.00% 85.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36608-36615 25 0.03% 85.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36864-36871 337 0.39% 86.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36992-36999 2 0.00% 86.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37120-37127 141 0.16% 86.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37184-37191 1 0.00% 86.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37376-37383 73 0.08% 86.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37504-37511 3 0.00% 86.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37568-37575 1 0.00% 86.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37632-37639 82 0.10% 86.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37895 365 0.42% 86.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37952-37959 1 0.00% 86.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38016-38023 2 0.00% 86.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38144-38151 75 0.09% 87.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38336-38343 1 0.00% 87.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38400-38407 129 0.15% 87.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38464-38471 1 0.00% 87.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38528-38535 2 0.00% 87.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38592-38599 1 0.00% 87.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38656-38663 14 0.02% 87.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38720-38727 1 0.00% 87.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38912-38919 267 0.31% 87.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38976-38983 1 0.00% 87.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39104-39111 1 0.00% 87.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39168-39175 77 0.09% 87.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39232-39239 1 0.00% 87.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39296-39303 1 0.00% 87.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39424-39431 140 0.16% 87.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39552-39559 2 0.00% 87.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39680-39687 70 0.08% 87.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39808-39815 1 0.00% 87.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39936-39943 351 0.41% 88.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40064-40071 1 0.00% 88.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40192-40199 129 0.15% 88.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40448-40455 76 0.09% 88.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40576-40583 2 0.00% 88.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40640-40647 1 0.00% 88.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40704-40711 80 0.09% 88.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40832-40839 2 0.00% 88.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40960-40967 269 0.31% 88.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41152-41159 2 0.00% 88.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41216-41223 77 0.09% 89.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41408-41415 1 0.00% 89.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41472-41479 75 0.09% 89.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41600-41607 2 0.00% 89.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41728-41735 131 0.15% 89.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41856-41863 3 0.00% 89.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-41991 349 0.41% 89.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42112-42119 2 0.00% 89.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42240-42247 70 0.08% 89.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42496-42503 140 0.16% 89.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42624-42631 2 0.00% 89.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42688-42695 1 0.00% 89.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42752-42759 77 0.09% 90.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42816-42823 1 0.00% 90.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43008-43015 267 0.31% 90.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43136-43143 3 0.00% 90.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43200-43207 1 0.00% 90.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43264-43271 14 0.02% 90.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43328-43335 1 0.00% 90.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43520-43527 127 0.15% 90.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43648-43655 1 0.00% 90.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43776-43783 80 0.09% 90.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43840-43847 2 0.00% 90.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43904-43911 2 0.00% 90.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44032-44039 364 0.42% 91.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44096-44103 1 0.00% 91.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44160-44167 1 0.00% 91.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44224-44231 1 0.00% 91.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44288-44295 83 0.10% 91.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44352-44359 1 0.00% 91.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44416-44423 1 0.00% 91.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44544-44551 73 0.08% 91.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44672-44679 2 0.00% 91.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44800-44807 144 0.17% 91.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44864-44871 2 0.00% 91.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45056-45063 337 0.39% 91.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45184-45191 1 0.00% 91.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45248-45255 1 0.00% 91.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45312-45319 24 0.03% 91.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45440-45447 3 0.00% 91.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45568-45575 16 0.02% 91.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45696-45703 3 0.00% 91.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45824-45831 144 0.17% 92.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45888-45895 2 0.00% 92.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46087 327 0.38% 92.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46144-46151 1 0.00% 92.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46272-46279 1 0.00% 92.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46336-46343 69 0.08% 92.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46464-46471 1 0.00% 92.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46592-46599 79 0.09% 92.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46720-46727 2 0.00% 92.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46848-46855 89 0.10% 92.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46912-46919 1 0.00% 92.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46976-46983 1 0.00% 92.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47104-47111 334 0.39% 93.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47232-47239 2 0.00% 93.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47296-47303 3 0.00% 93.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47360-47367 78 0.09% 93.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47616-47623 88 0.10% 93.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47744-47751 4 0.00% 93.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47872-47879 24 0.03% 93.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47936-47943 1 0.00% 93.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48000-48007 1 0.00% 93.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48135 398 0.46% 93.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48384-48391 83 0.10% 93.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48640-48647 77 0.09% 93.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48768-48775 72 0.08% 94.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48903 83 0.10% 94.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48960-48967 1 0.00% 94.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49024-49031 3 0.00% 94.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49088-49095 1 0.00% 94.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49159 5012 5.82% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29703 276 0.32% 81.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29824-29831 3 0.00% 81.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29888-29895 1 0.00% 81.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-29959 155 0.18% 81.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30016-30023 1 0.00% 81.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30080-30087 2 0.00% 81.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30144-30151 1 0.00% 81.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30215 130 0.15% 81.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30272-30279 1 0.00% 81.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30471 35 0.04% 81.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30592-30599 7 0.01% 81.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30656-30663 2 0.00% 81.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30727 330 0.38% 81.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30784-30791 2 0.00% 81.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30848-30855 1 0.00% 81.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-30983 79 0.09% 81.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31040-31047 1 0.00% 81.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31104-31111 2 0.00% 81.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31239 75 0.09% 82.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31296-31303 1 0.00% 82.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31360-31367 1 0.00% 82.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31495 72 0.08% 82.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31552-31559 2 0.00% 82.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31616-31623 3 0.00% 82.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31680-31687 1 0.00% 82.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31751 264 0.31% 82.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31872-31879 1 0.00% 82.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32007 85 0.10% 82.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32064-32071 2 0.00% 82.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32128-32135 1 0.00% 82.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32263 158 0.18% 82.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32320-32327 1 0.00% 82.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32384-32391 1 0.00% 82.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32448-32455 1 0.00% 82.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32519 132 0.15% 82.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32576-32583 2 0.00% 82.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32640-32647 1 0.00% 82.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32775 526 0.61% 83.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32896-32903 2 0.00% 83.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33031 130 0.15% 83.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33216-33223 1 0.00% 83.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33287 160 0.19% 83.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33408-33415 2 0.00% 83.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33472-33479 1 0.00% 83.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33543 90 0.10% 83.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33600-33607 4 0.00% 83.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33799 276 0.32% 84.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33856-33863 1 0.00% 84.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33920-33927 2 0.00% 84.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34048-34055 69 0.08% 84.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34112-34119 1 0.00% 84.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34304-34311 76 0.09% 84.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34432-34439 3 0.00% 84.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34560-34567 78 0.09% 84.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34688-34695 1 0.00% 84.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34752-34759 1 0.00% 84.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34823 329 0.38% 84.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34944-34951 1 0.00% 84.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35072-35079 37 0.04% 84.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35200-35207 1 0.00% 84.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35328-35335 132 0.15% 85.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35456-35463 1 0.00% 85.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35584-35591 157 0.18% 85.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35712-35719 3 0.00% 85.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35847 272 0.32% 85.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36032-36039 1 0.00% 85.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36096-36103 68 0.08% 85.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36224-36231 2 0.00% 85.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36352-36359 82 0.10% 85.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36480-36487 3 0.00% 85.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36608-36615 85 0.10% 85.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36800-36807 2 0.00% 85.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36871 328 0.38% 86.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37120-37127 78 0.09% 86.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37184-37191 2 0.00% 86.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37248-37255 1 0.00% 86.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37312-37319 1 0.00% 86.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37376-37383 7 0.01% 86.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37504-37511 1 0.00% 86.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37632-37639 154 0.18% 86.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37895 389 0.45% 87.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38016-38023 2 0.00% 87.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38151 41 0.05% 87.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38272-38279 2 0.00% 87.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38336-38343 1 0.00% 87.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38400-38407 63 0.07% 87.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38528-38535 4 0.00% 87.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38656-38663 83 0.10% 87.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38919 332 0.39% 87.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39040-39047 1 0.00% 87.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39168-39175 17 0.02% 87.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39424-39431 81 0.09% 87.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39552-39559 2 0.00% 87.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39680-39687 95 0.11% 87.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39936-39943 463 0.54% 88.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40192-40199 69 0.08% 88.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40320-40327 4 0.00% 88.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40384-40391 1 0.00% 88.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40448-40455 15 0.02% 88.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40576-40583 4 0.00% 88.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40640-40647 1 0.00% 88.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40704-40711 149 0.17% 88.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40967 257 0.30% 88.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41152-41159 1 0.00% 88.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41223 145 0.17% 89.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41344-41351 1 0.00% 89.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41408-41415 1 0.00% 89.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41472-41479 16 0.02% 89.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41536-41543 1 0.00% 89.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41600-41607 2 0.00% 89.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41728-41735 72 0.08% 89.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-41991 458 0.53% 89.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42176-42183 1 0.00% 89.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42240-42247 90 0.10% 89.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42304-42311 2 0.00% 89.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42432-42439 1 0.00% 89.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42503 82 0.10% 89.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42624-42631 4 0.00% 89.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42688-42695 1 0.00% 89.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42759 17 0.02% 90.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42816-42823 1 0.00% 90.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42880-42887 2 0.00% 90.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43015 331 0.38% 90.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43200-43207 1 0.00% 90.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43271 81 0.09% 90.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43328-43335 1 0.00% 90.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43527 64 0.07% 90.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43648-43655 4 0.00% 90.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43712-43719 1 0.00% 90.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43776-43783 37 0.04% 90.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43840-43847 1 0.00% 90.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 395 0.46% 91.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44096-44103 1 0.00% 91.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44295 150 0.17% 91.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44352-44359 2 0.00% 91.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44551 10 0.01% 91.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44608-44615 2 0.00% 91.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44672-44679 4 0.00% 91.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44807 81 0.09% 91.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44864-44871 2 0.00% 91.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 328 0.38% 91.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45319 82 0.10% 91.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45376-45383 2 0.00% 91.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45440-45447 2 0.00% 91.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 83 0.10% 91.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45696-45703 3 0.00% 91.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 69 0.08% 92.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45952-45959 1 0.00% 92.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 277 0.32% 92.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46208-46215 3 0.00% 92.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46343 151 0.18% 92.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46599 129 0.15% 92.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46656-46663 1 0.00% 92.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46720-46727 2 0.00% 92.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46784-46791 1 0.00% 92.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 36 0.04% 92.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46912-46919 1 0.00% 92.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46976-46983 2 0.00% 92.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 330 0.38% 93.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47168-47175 1 0.00% 93.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47296-47303 1 0.00% 93.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 81 0.09% 93.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47488-47495 1 0.00% 93.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47552-47559 1 0.00% 93.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 82 0.10% 93.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47744-47751 1 0.00% 93.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47808-47815 2 0.00% 93.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 74 0.09% 93.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47936-47943 1 0.00% 93.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48000-48007 1 0.00% 93.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 266 0.31% 93.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48256-48263 1 0.00% 93.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 83 0.10% 93.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48512-48519 1 0.00% 93.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 154 0.18% 93.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48704-48711 2 0.00% 93.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48768-48775 62 0.07% 94.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 129 0.15% 94.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48960-48967 2 0.00% 94.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49024-49031 2 0.00% 94.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 4 0.00% 94.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 4946 5.74% 99.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::49216-49223 1 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49408-49415 1 0.00% 99.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::49600-49607 1 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49664-49671 1 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49728-49735 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49856-49863 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49920-49927 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50240-50247 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50368-50375 2 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50496-50503 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50560-50567 2 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50624-50631 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50688-50695 2 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50752-50759 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50944-50951 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51008-51015 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51072-51079 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51136-51143 3 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51200-51207 3 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51264-51271 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51392-51399 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51456-51463 2 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51520-51527 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51840-51847 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49664-49671 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49920-49927 2 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50048-50055 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50176-50183 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50432-50439 4 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50496-50503 2 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50560-50567 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50624-50631 2 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50688-50695 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50816-50823 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50880-50887 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51136-51143 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51200-51207 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51264-51271 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51456-51463 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51584-51591 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51712-51719 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51904-51911 1 0.00% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::51968-51975 2 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 86134 # Bytes accessed per row activation -system.physmem.totQLat 365453646000 # Total ticks spent queuing -system.physmem.totMemAccLat 458164497250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 75292090000 # Total ticks spent in databus transfers -system.physmem.totBankLat 17418761250 # Total ticks spent accessing banks -system.physmem.avgQLat 24269.06 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1156.75 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::52160-52167 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::52288-52295 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 86110 # Bytes accessed per row activation +system.physmem.totQLat 365142496500 # Total ticks spent queuing +system.physmem.totMemAccLat 457904364000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 75291530000 # Total ticks spent in databus transfers +system.physmem.totBankLat 17470337500 # Total ticks spent accessing banks +system.physmem.avgQLat 24248.58 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1160.18 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30425.81 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 381.66 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 30408.76 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 381.50 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.73 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 51.26 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 51.24 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.69 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 3.00 # Data bus utilization in percentage system.physmem.busUtilRead 2.98 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing -system.physmem.avgWrQLen 12.83 # Average write queue length when enqueuing -system.physmem.readRowHits 14986798 # Number of row buffer hits during reads -system.physmem.writeRowHits 93332 # Number of row buffer hits during writes +system.physmem.avgWrQLen 13.37 # Average write queue length when enqueuing +system.physmem.readRowHits 14986658 # Number of row buffer hits during reads +system.physmem.writeRowHits 93339 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 86.53 # Row buffer hit rate for writes -system.physmem.avgGap 158713.50 # Average gap between requests +system.physmem.writeRowHitRate 86.57 # Row buffer hit rate for writes +system.physmem.avgGap 158777.68 # Average gap between requests system.physmem.pageHitRate 99.43 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 1.72 # Percentage of time for which DRAM has all the banks in precharge state +system.physmem.prechargeAllPercent 2.54 # Percentage of time for which DRAM has all the banks in precharge state system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -767,50 +772,50 @@ system.realview.nvmem.bw_inst_read::cpu.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54900302 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16149434 # Transaction distribution -system.membus.trans_dist::ReadResp 16149434 # Transaction distribution +system.membus.throughput 54877277 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16149448 # Transaction distribution +system.membus.trans_dist::ReadResp 16149448 # Transaction distribution system.membus.trans_dist::WriteReq 763332 # Transaction distribution system.membus.trans_dist::WriteResp 763332 # Transaction distribution -system.membus.trans_dist::Writeback 59131 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4679 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4682 # Transaction distribution -system.membus.trans_dist::ReadExReq 131448 # Transaction distribution -system.membus.trans_dist::ReadExResp 131448 # Transaction distribution +system.membus.trans_dist::Writeback 59102 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4681 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4683 # Transaction distribution +system.membus.trans_dist::ReadExReq 131427 # Transaction distribution +system.membus.trans_dist::ReadExResp 131427 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382942 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3760 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885801 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272507 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885760 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272466 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29884416 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 29884416 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34156923 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 34156882 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390301 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7520 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16694936 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19092825 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16692512 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19090401 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119537664 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 119537664 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 138630489 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 138630489 # Total data (bytes) +system.membus.tot_pkt_size::total 138628065 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 138628065 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1486873500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1486850000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3694000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3609000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17363465500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17361408000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4733669250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4731178629 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 33737503451 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 33737119450 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -818,7 +823,7 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 48285786 # Throughput (bytes/s) +system.iobus.throughput 48266379 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 16125522 # Transaction distribution system.iobus.trans_dist::ReadResp 16125522 # Transaction distribution system.iobus.trans_dist::WriteReq 8157 # Transaction distribution @@ -928,41 +933,83 @@ system.iobus.reqLayer25.occupancy 14942208000 # La system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) system.iobus.respLayer0.occupancy 2374785000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 40921719549 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 40921538550 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 14384927 # Number of BP lookups -system.cpu.branchPred.condPredicted 11469310 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 704177 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9471049 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7661571 # Number of BTB hits +system.cpu.branchPred.lookups 14756776 # Number of BP lookups +system.cpu.branchPred.condPredicted 11839520 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 705876 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9493937 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7667614 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.894640 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1398227 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72610 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 80.763270 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1398139 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 72469 # Number of incorrect RAS predictions. +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51182106 # DTB read hits -system.cpu.dtb.read_misses 64421 # DTB read misses -system.cpu.dtb.write_hits 11699698 # DTB write hits -system.cpu.dtb.write_misses 15824 # DTB write misses +system.cpu.dtb.read_hits 51181584 # DTB read hits +system.cpu.dtb.read_misses 65031 # DTB read misses +system.cpu.dtb.write_hits 11699885 # DTB write hits +system.cpu.dtb.write_misses 15694 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3567 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2374 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 404 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 3476 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2524 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 396 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1314 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51246527 # DTB read accesses -system.cpu.dtb.write_accesses 11715522 # DTB write accesses +system.cpu.dtb.perms_faults 1369 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51246615 # DTB read accesses +system.cpu.dtb.write_accesses 11715579 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 62881804 # DTB hits -system.cpu.dtb.misses 80245 # DTB misses -system.cpu.dtb.accesses 62962049 # DTB accesses -system.cpu.itb.inst_hits 11522583 # ITB inst hits -system.cpu.itb.inst_misses 11276 # ITB inst misses +system.cpu.dtb.hits 62881469 # DTB hits +system.cpu.dtb.misses 80725 # DTB misses +system.cpu.dtb.accesses 62962194 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.inst_hits 11524718 # ITB inst hits +system.cpu.itb.inst_misses 11477 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -971,114 +1018,114 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2480 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2510 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 3012 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2880 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 11533859 # ITB inst accesses -system.cpu.itb.hits 11522583 # DTB hits -system.cpu.itb.misses 11276 # DTB misses -system.cpu.itb.accesses 11533859 # DTB accesses -system.cpu.numCycles 474898657 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 11536195 # ITB inst accesses +system.cpu.itb.hits 11524718 # DTB hits +system.cpu.itb.misses 11477 # DTB misses +system.cpu.itb.accesses 11536195 # DTB accesses +system.cpu.numCycles 477111575 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 29752889 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 90273347 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14384927 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9059798 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 20146705 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4653497 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 122274 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 96010555 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2615 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 88482 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 2690288 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 446 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11519088 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 708911 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5337 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 152021113 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.740504 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.094585 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 29753545 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 90325732 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14756776 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9065753 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 20157040 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4656007 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 125616 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 98208682 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2521 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 87096 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 2698608 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 449 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11521342 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 709389 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5491 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 154241572 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.730167 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.081671 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 131890125 86.76% 86.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1304050 0.86% 87.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1713045 1.13% 88.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2295968 1.51% 90.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2102742 1.38% 91.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1107769 0.73% 92.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2555355 1.68% 94.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 744146 0.49% 94.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8307913 5.46% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 134100120 86.94% 86.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1306005 0.85% 87.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1712076 1.11% 88.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2296227 1.49% 90.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2110153 1.37% 91.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1105630 0.72% 92.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2555237 1.66% 94.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 745864 0.48% 94.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8310260 5.39% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 152021113 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.030291 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.190090 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 31508438 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 98138099 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18373215 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 963804 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3037557 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1957081 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 171807 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 107274658 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 567663 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3037557 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 33258738 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 39476292 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52673596 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 17529662 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6045268 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102285915 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 20597 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1004806 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4066044 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 644 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 106018919 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 466959682 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 432092489 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10446 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78387358 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27631560 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 830464 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 736820 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12181979 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 19715902 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13307123 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1978281 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2470778 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 95109477 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1982753 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 122906700 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 167286 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 18927569 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 47237054 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 500451 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 152021113 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.808484 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.527863 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 154241572 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.030929 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.189318 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31783151 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 100076545 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18079225 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1264474 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3038177 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1958594 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 172374 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 107306930 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 570435 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3038177 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 33521222 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 38625715 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 55163536 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 17589404 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6303518 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102301164 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 457 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 997569 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4061695 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 772 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 106380900 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 473930729 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 432790417 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 10427 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78723244 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 27657655 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1170957 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1077143 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12622955 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 19717794 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13303938 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1949827 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2475969 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 95121483 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1987498 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 122914150 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 166701 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 18940781 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 47245549 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 505193 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 154241572 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.796894 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.515720 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 108300469 71.24% 71.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13447891 8.85% 80.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 6945073 4.57% 84.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5857007 3.85% 88.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12370739 8.14% 96.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2808869 1.85% 98.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1695394 1.12% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 467391 0.31% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 128280 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 109895599 71.25% 71.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 14389173 9.33% 80.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 6873802 4.46% 85.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5671511 3.68% 88.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12312296 7.98% 96.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2806335 1.82% 98.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1696199 1.10% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 468469 0.30% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 128188 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 152021113 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 154241572 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 61937 0.70% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 6 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 62148 0.70% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.70% # attempts to use FU when none available @@ -1106,437 +1153,436 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8370529 94.64% 95.34% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 412377 4.66% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8367826 94.63% 95.33% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 412812 4.67% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 363666 0.30% 0.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 57620183 46.88% 47.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93128 0.08% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 24 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 6 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 20 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 20 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52507579 42.72% 89.98% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12319960 10.02% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 28518 0.02% 0.02% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 57963749 47.16% 47.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93288 0.08% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 22 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 18 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 19 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52506877 42.72% 89.98% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12319545 10.02% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 122906700 # Type of FU issued -system.cpu.iq.rate 0.258806 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8844849 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071964 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 406902990 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 116036304 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85470220 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23531 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12536 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10316 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 131375312 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12571 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 623425 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 122914150 # Type of FU issued +system.cpu.iq.rate 0.257621 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8842790 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071943 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 409136453 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 116066186 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85476047 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23300 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12528 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10301 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 131716001 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12421 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 624558 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4061911 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6363 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30197 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1575391 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4063711 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6653 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30079 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1572166 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107753 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 681273 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107729 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 680356 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3037557 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 30701555 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 434229 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 97313991 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 205819 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 19715902 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13307123 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1410230 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 113324 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3566 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30197 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 350181 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 268988 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 619169 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 120829627 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 51869148 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2077073 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3038177 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 30160267 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 434164 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 97330281 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 206491 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 19717794 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13303938 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1415153 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 113233 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3362 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30079 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 350155 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 270547 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 620702 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 120836027 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 51869099 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2078123 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 221761 # number of nop insts executed -system.cpu.iew.exec_refs 64080783 # number of memory reference insts executed -system.cpu.iew.exec_branches 11475005 # Number of branches executed -system.cpu.iew.exec_stores 12211635 # Number of stores executed -system.cpu.iew.exec_rate 0.254432 # Inst execution rate -system.cpu.iew.wb_sent 119890224 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85480536 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47031033 # num instructions producing a value -system.cpu.iew.wb_consumers 87879900 # num instructions consuming a value +system.cpu.iew.exec_nop 221300 # number of nop insts executed +system.cpu.iew.exec_refs 64080526 # number of memory reference insts executed +system.cpu.iew.exec_branches 11821026 # Number of branches executed +system.cpu.iew.exec_stores 12211427 # Number of stores executed +system.cpu.iew.exec_rate 0.253266 # Inst execution rate +system.cpu.iew.wb_sent 119895169 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85486348 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47016858 # num instructions producing a value +system.cpu.iew.wb_consumers 87565512 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.179997 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.535174 # average fanout of values written-back +system.cpu.iew.wb_rate 0.179175 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.536934 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 18664214 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1482302 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 534875 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 148983556 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.521850 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.510275 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 18677700 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1482305 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 536038 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 151203395 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.514192 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.490223 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 121547303 81.58% 81.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13306218 8.93% 90.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3902162 2.62% 93.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2119528 1.42% 94.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1937783 1.30% 95.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 976082 0.66% 96.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1595601 1.07% 97.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 718241 0.48% 98.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2880638 1.93% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 122740077 81.18% 81.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 14637973 9.68% 90.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3917047 2.59% 93.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2134429 1.41% 94.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1622101 1.07% 95.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 972992 0.64% 96.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1598831 1.06% 97.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 713641 0.47% 98.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2866304 1.90% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 148983556 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60456059 # Number of instructions committed -system.cpu.commit.committedOps 77747065 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 151203395 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60456535 # Number of instructions committed +system.cpu.commit.committedOps 77747623 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27385723 # Number of memory references committed -system.cpu.commit.loads 15653991 # Number of loads committed +system.cpu.commit.refs 27385855 # Number of memory references committed +system.cpu.commit.loads 15654083 # Number of loads committed system.cpu.commit.membars 403571 # Number of memory barriers committed -system.cpu.commit.branches 9961071 # Number of branches committed +system.cpu.commit.branches 10305769 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68852511 # Number of committed integer instructions. -system.cpu.commit.function_calls 991207 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2880638 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 69188185 # Number of committed integer instructions. +system.cpu.commit.function_calls 991209 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2866304 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 240665808 # The number of ROB reads -system.cpu.rob.rob_writes 195946920 # The number of ROB writes -system.cpu.timesIdled 1776652 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 322877544 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4575281578 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60305678 # Number of Instructions Simulated -system.cpu.committedOps 77596684 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60305678 # Number of Instructions Simulated -system.cpu.cpi 7.874858 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.874858 # CPI: Total CPI of All Threads -system.cpu.ipc 0.126986 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.126986 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 547244882 # number of integer regfile reads -system.cpu.int_regfile_writes 87532645 # number of integer regfile writes -system.cpu.fp_regfile_reads 8511 # number of floating regfile reads -system.cpu.fp_regfile_writes 2972 # number of floating regfile writes -system.cpu.misc_regfile_reads 30145050 # number of misc regfile reads -system.cpu.misc_regfile_writes 831837 # number of misc regfile writes -system.cpu.toL2Bus.throughput 58898886 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2658060 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2658059 # Transaction distribution +system.cpu.rob.rob_reads 242914035 # The number of ROB reads +system.cpu.rob.rob_writes 195975439 # The number of ROB writes +system.cpu.timesIdled 1776357 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 322870003 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4575099289 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60306154 # Number of Instructions Simulated +system.cpu.committedOps 77597242 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60306154 # Number of Instructions Simulated +system.cpu.cpi 7.911491 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.911491 # CPI: Total CPI of All Threads +system.cpu.ipc 0.126398 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.126398 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 548607871 # number of integer regfile reads +system.cpu.int_regfile_writes 87541390 # number of integer regfile writes +system.cpu.fp_regfile_reads 8324 # number of floating regfile reads +system.cpu.fp_regfile_writes 2920 # number of floating regfile writes +system.cpu.misc_regfile_reads 268241142 # number of misc regfile reads +system.cpu.misc_regfile_writes 1173227 # number of misc regfile writes +system.cpu.toL2Bus.throughput 58865094 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2658464 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2658463 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 763332 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 763332 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 607897 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2956 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 13 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2969 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 246128 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 246128 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1961789 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5796637 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30578 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 127052 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7916056 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62740736 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85535129 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 41644 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 210260 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 148527769 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 148527769 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 199672 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3129078659 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::Writeback 607582 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2966 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 12 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2978 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 246158 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 246158 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1961995 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5795878 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31363 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128647 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7917883 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62746624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85500065 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 43624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 215596 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 148505909 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 148505909 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 195968 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3128804200 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1474541718 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1474711974 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2550360089 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2550008218 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 20171491 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 20466481 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 74593037 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 74842560 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 980798 # number of replacements -system.cpu.icache.tags.tagsinuse 511.579102 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 10457750 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 981310 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 10.656928 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 6918450250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.579102 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999178 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999178 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 980909 # number of replacements +system.cpu.icache.tags.tagsinuse 511.574447 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 10459956 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 981421 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 10.657970 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 6918965000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.574447 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999169 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999169 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 225 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 150 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 221 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 155 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 12500309 # Number of tag accesses -system.cpu.icache.tags.data_accesses 12500309 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 10457750 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 10457750 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 10457750 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 10457750 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 10457750 # number of overall hits -system.cpu.icache.overall_hits::total 10457750 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1061214 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1061214 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1061214 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1061214 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1061214 # number of overall misses -system.cpu.icache.overall_misses::total 1061214 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14272429649 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14272429649 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14272429649 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14272429649 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14272429649 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14272429649 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11518964 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11518964 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11518964 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11518964 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11518964 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11518964 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092128 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.092128 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.092128 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.092128 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.092128 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.092128 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13449.153186 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13449.153186 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13449.153186 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13449.153186 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13449.153186 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13449.153186 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 5990 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 12502670 # Number of tag accesses +system.cpu.icache.tags.data_accesses 12502670 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 10459956 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 10459956 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 10459956 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 10459956 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 10459956 # number of overall hits +system.cpu.icache.overall_hits::total 10459956 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1061258 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1061258 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1061258 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1061258 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1061258 # number of overall misses +system.cpu.icache.overall_misses::total 1061258 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14277146640 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14277146640 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14277146640 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14277146640 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14277146640 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14277146640 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11521214 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11521214 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11521214 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11521214 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11521214 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11521214 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092113 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.092113 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.092113 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.092113 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.092113 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.092113 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13453.040297 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13453.040297 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13453.040297 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13453.040297 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13453.040297 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13453.040297 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 6445 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 322 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 336 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 18.602484 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 19.181548 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79868 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 79868 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 79868 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 79868 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 79868 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 79868 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 981346 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 981346 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 981346 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 981346 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 981346 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 981346 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11584683024 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11584683024 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11584683024 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11584683024 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11584683024 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11584683024 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 8658250 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 8658250 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 8658250 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 8658250 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.085194 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.085194 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.085194 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.085194 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.085194 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.085194 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11804.891469 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11804.891469 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11804.891469 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11804.891469 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11804.891469 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11804.891469 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79801 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 79801 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 79801 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 79801 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 79801 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 79801 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 981457 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 981457 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 981457 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 981457 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 981457 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 981457 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11591245017 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11591245017 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11591245017 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11591245017 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11591245017 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11591245017 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 8870000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 8870000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 8870000 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 8870000 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.085187 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.085187 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.085187 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.085187 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.085187 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.085187 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11810.242341 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11810.242341 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11810.242341 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11810.242341 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11810.242341 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11810.242341 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 64371 # number of replacements -system.cpu.l2cache.tags.tagsinuse 51362.964424 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1886397 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 129765 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 14.537025 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 2489982729000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 36926.272860 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 27.936805 # Average occupied blocks per requestor +system.cpu.l2cache.tags.replacements 64359 # number of replacements +system.cpu.l2cache.tags.tagsinuse 51360.491961 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1887854 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 129751 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 14.549822 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 2490800967500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 36938.900442 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 39.947099 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000373 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 8173.687928 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 6235.066458 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.563450 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000426 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 8146.352593 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 6235.291454 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.563643 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000610 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.124721 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.095140 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.783737 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 19 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65375 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 18 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 355 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3055 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6962 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54965 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000290 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997543 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 18784884 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 18784884 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 52523 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10409 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 967861 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 387146 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1417939 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 607897 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 607897 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 41 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 41 # number of UpgradeReq hits +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.124303 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.095143 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.783699 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 28 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 65364 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 28 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 357 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3045 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6929 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54997 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000427 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997375 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 18795937 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 18795937 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 53847 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10904 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 967954 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 386879 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1419584 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 607582 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 607582 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 43 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 43 # number of UpgradeReq hits system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 10 # number of SCUpgradeReq hits system.cpu.l2cache.SCUpgradeReq_hits::total 10 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 112916 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 112916 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 52523 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 10409 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 967861 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 500062 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1530855 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 52523 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 10409 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 967861 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 500062 # number of overall hits -system.cpu.l2cache.overall_hits::total 1530855 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 42 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_hits::cpu.data 112973 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 112973 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 53847 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 10904 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 967954 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 499852 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1532557 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 53847 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 10904 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 967954 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 499852 # number of overall hits +system.cpu.l2cache.overall_hits::total 1532557 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 52 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 12345 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 10721 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 23110 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 2915 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 2915 # number of UpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 133212 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 133212 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 42 # number of demand (read+write) misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 12341 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 10725 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 23120 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 2923 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 2923 # number of UpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 133185 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 133185 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 52 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 12345 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 143933 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 156322 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 42 # number of overall misses +system.cpu.l2cache.demand_misses::cpu.inst 12341 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 143910 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 156305 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 52 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 12345 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 143933 # number of overall misses -system.cpu.l2cache.overall_misses::total 156322 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 3605250 # number of ReadReq miss cycles +system.cpu.l2cache.overall_misses::cpu.inst 12341 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 143910 # number of overall misses +system.cpu.l2cache.overall_misses::total 156305 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 4042250 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 158000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 903018500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 812779249 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1719560999 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 510978 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 510978 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10116159486 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 10116159486 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 3605250 # number of demand (read+write) miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 908634500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 819979999 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1732814749 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 583475 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 583475 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9837869742 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 9837869742 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 4042250 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 158000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 903018500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10928938735 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 11835720485 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 3605250 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 908634500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10657849741 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 11570684491 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 4042250 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 158000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 903018500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10928938735 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 11835720485 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 52565 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10411 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 980206 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 397867 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1441049 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 607897 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 607897 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2956 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2956 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 13 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::total 13 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 246128 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 246128 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 52565 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 10411 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 980206 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 643995 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1687177 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 52565 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 10411 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 980206 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 643995 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1687177 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000799 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000192 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012594 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026946 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.016037 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986130 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986130 # miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.230769 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.230769 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541231 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.541231 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000799 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000192 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012594 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.223500 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.092653 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000799 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000192 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012594 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.223500 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.092653 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 85839.285714 # average ReadReq miss latency +system.cpu.l2cache.overall_miss_latency::cpu.inst 908634500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10657849741 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 11570684491 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 53899 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10906 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 980295 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 397604 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1442704 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 607582 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 607582 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2966 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2966 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 12 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::total 12 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 246158 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 246158 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 53899 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 10906 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 980295 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 643762 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1688862 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 53899 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 10906 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 980295 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 643762 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1688862 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000965 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000183 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012589 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026974 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.016025 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.985502 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.985502 # miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.166667 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.166667 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541055 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.541055 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000965 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000183 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012589 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.223545 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.092550 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000965 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000183 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012589 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.223545 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.092550 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 77735.576923 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 79000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73148.521669 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75811.887790 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 74407.658979 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 175.292624 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 175.292624 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75940.301820 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75940.301820 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 85839.285714 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73627.299246 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76455.011562 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 74948.734818 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 199.615121 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 199.615121 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73866.199212 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73866.199212 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 77735.576923 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 79000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73148.521669 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75930.736766 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75713.722221 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 85839.285714 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73627.299246 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74059.132381 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 74026.323477 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 77735.576923 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 79000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73148.521669 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75930.736766 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75713.722221 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73627.299246 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74059.132381 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 74026.323477 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1545,109 +1591,109 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 59131 # number of writebacks -system.cpu.l2cache.writebacks::total 59131 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 11 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 66 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 66 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 77 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 66 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 77 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 42 # number of ReadReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 59102 # number of writebacks +system.cpu.l2cache.writebacks::total 59102 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 13 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 65 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 78 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 13 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 65 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 78 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 13 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 65 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 78 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 52 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12334 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10655 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 23033 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2915 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 2915 # number of UpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133212 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 133212 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 42 # number of demand (read+write) MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12328 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10660 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 23042 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2923 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 2923 # number of UpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133185 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 133185 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 52 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 12334 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 143867 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 156245 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 42 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 12328 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 143845 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 156227 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 52 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 12334 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 143867 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 156245 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 3085750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.inst 12328 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 143845 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 156227 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 3398750 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 133500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 747187750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 675762749 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1426169749 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29153914 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29153914 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 30003 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 30003 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8455143514 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8455143514 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 3085750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 752714750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 682165499 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1438412499 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29232923 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29232923 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 20002 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 20002 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8179067758 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8179067758 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 3398750 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 133500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 747187750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9130906263 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9881313263 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 3085750 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 752714750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8861233257 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9617480257 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 3398750 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 133500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 747187750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9130906263 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9881313263 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 6187249 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166935059000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166941246249 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 17442653817 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 17442653817 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 6187249 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184377712817 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184383900066 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000799 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000192 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012583 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026780 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015983 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986130 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986130 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.230769 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.230769 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541231 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541231 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000799 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000192 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012583 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223398 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.092607 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000799 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000192 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012583 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223398 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.092607 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 73470.238095 # average ReadReq mshr miss latency +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 752714750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8861233257 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9617480257 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 6336999 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166935139250 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166941476249 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 17447345437 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 17447345437 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 6336999 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184382484687 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184388821686 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000965 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000183 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012576 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026811 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015971 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.985502 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.985502 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.166667 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.166667 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541055 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541055 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000965 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000183 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012576 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223444 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.092504 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000965 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000183 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012576 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223444 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.092504 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 65360.576923 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 66750 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60579.515972 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63422.125669 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61918.540746 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001.342710 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.342710 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61057.328845 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63993.011163 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62425.679151 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63471.335270 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63471.335270 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 73470.238095 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61411.328288 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61411.328288 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 65360.576923 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 66750 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60579.515972 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63467.690735 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63242.428641 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 73470.238095 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61057.328845 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61602.650471 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61560.935414 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 65360.576923 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 66750 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60579.515972 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63467.690735 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63242.428641 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61057.328845 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61602.650471 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61560.935414 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1657,13 +1703,13 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 643483 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.993331 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 21507621 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 643995 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 33.397186 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 42430250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.993331 # Average occupied blocks per requestor +system.cpu.dcache.tags.replacements 643250 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.993295 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 21507454 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 643762 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 33.409015 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 42602250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.993295 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999987 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -1671,154 +1717,154 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 192 system.cpu.dcache.tags.age_task_id_blocks_1024::1 302 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 101519243 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 101519243 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 13755484 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13755484 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7258628 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7258628 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 242811 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 242811 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247593 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 247593 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21014112 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21014112 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21014112 # number of overall hits -system.cpu.dcache.overall_hits::total 21014112 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 737297 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 737297 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2963410 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2963410 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13576 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13576 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 13 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 13 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3700707 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3700707 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3700707 # number of overall misses -system.cpu.dcache.overall_misses::total 3700707 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10005137822 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10005137822 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 141347559382 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 141347559382 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 185728250 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 185728250 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 206503 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 206503 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 151352697204 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 151352697204 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 151352697204 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 151352697204 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14492781 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 14492781 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10222038 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10222038 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256387 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 256387 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 101513406 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 101513406 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 13755166 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13755166 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7258873 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7258873 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 242710 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 242710 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247594 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247594 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21014039 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21014039 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21014039 # number of overall hits +system.cpu.dcache.overall_hits::total 21014039 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 736315 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 736315 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2963189 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2963189 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13552 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13552 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 12 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 12 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3699504 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3699504 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3699504 # number of overall misses +system.cpu.dcache.overall_misses::total 3699504 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10015008577 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10015008577 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 140227660304 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 140227660304 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 186052000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 186052000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 181002 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 181002 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 150242668881 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 150242668881 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 150242668881 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 150242668881 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14491481 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14491481 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10222062 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10222062 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256262 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 256262 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 247606 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 247606 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24714819 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24714819 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24714819 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24714819 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050873 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.050873 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289904 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.289904 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052951 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052951 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000053 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000053 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.149736 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.149736 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.149736 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.149736 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13570.023779 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13570.023779 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47697.604915 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 47697.604915 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13680.631261 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13680.631261 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15884.846154 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15884.846154 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 40898.319484 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 40898.319484 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 40898.319484 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 40898.319484 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 32831 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 27415 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2635 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 279 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.459583 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 98.261649 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 24713543 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24713543 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24713543 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24713543 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050810 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.050810 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289882 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.289882 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052883 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052883 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000048 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000048 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.149695 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.149695 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.149695 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.149695 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13601.527304 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13601.527304 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47323.225182 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 47323.225182 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13728.748524 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13728.748524 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15083.500000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15083.500000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 40611.570870 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 40611.570870 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 40611.570870 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 40611.570870 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 31857 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 27549 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2688 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 281 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.851562 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 98.039146 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 607897 # number of writebacks -system.cpu.dcache.writebacks::total 607897 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351582 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 351582 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714405 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2714405 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1345 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1345 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3065987 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3065987 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3065987 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3065987 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385715 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 385715 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249005 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 249005 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12231 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12231 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 13 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 13 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 634720 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 634720 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 634720 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 634720 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4972029375 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4972029375 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11600619783 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11600619783 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 146011500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 146011500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 180497 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 180497 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16572649158 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16572649158 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16572649158 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 16572649158 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182328280000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182328280000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26841536765 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26841536765 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209169816765 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 209169816765 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026614 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026614 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024360 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024360 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047705 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047705 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000053 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000053 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025682 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025682 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12890.422657 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12890.422657 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46587.898970 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46587.898970 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11937.821928 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11937.821928 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13884.384615 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13884.384615 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26110.173239 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26110.173239 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26110.173239 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26110.173239 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 607582 # number of writebacks +system.cpu.dcache.writebacks::total 607582 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 350850 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 350850 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714158 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2714158 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1320 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1320 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3065008 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3065008 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3065008 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3065008 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385465 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385465 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249031 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 249031 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12232 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12232 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 12 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 634496 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634496 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634496 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634496 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4975619608 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4975619608 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11323354786 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11323354786 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 146514250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 146514250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 156998 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 156998 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16298974394 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16298974394 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16298974394 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16298974394 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182328293250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182328293250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26845365872 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26845365872 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209173659122 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 209173659122 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026599 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026599 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024362 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024362 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047732 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047732 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000048 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000048 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025674 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025674 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025674 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025674 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12908.096995 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12908.096995 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45469.659544 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45469.659544 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11977.947188 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11977.947188 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13083.166667 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13083.166667 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25688.064848 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25688.064848 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25688.064848 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25688.064848 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1842,16 +1888,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1499067779549 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1499067779549 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1499067779549 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1499067779549 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1499072952550 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1499072952550 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1499072952550 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1499072952550 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83033 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 83032 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini index bf231cd78..b551f2cf3 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini @@ -14,6 +14,7 @@ children=bridge cf0 clk_domain cpu0 cpu1 cpu2 cpu_clk_domain intrctrl iobus ioca atags_addr=256 boot_loader=/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain dtb_filename= @@ -22,9 +23,16 @@ enable_context_switch_stats_dump=false eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 +have_generic_timer=false +have_large_asid_64=false +have_lpae=false +have_security=false +have_virtualization=false +highest_el_is_64=false init_param=0 kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 +load_offset=0 machine_type=RealView_PBX mem_mode=atomic mem_ranges=0:134217727 @@ -33,7 +41,9 @@ multi_proc=true num_work_ids=16 panic_on_oops=true panic_on_panic=true +phys_addr_range_64=40 readfile=tests/halt.sh +reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -86,13 +96,14 @@ voltage_domain=system.voltage_domain [system.cpu0] type=AtomicSimpleCPU -children=dcache dtb icache interrupts isa itb tracer +children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu0.dstage2_mmu dtb=system.cpu0.dtb eventq_index=0 fastmem=false @@ -100,6 +111,7 @@ function_trace=false function_trace_start=0 interrupts=system.cpu0.interrupts isa=system.cpu0.isa +istage2_mmu=system.cpu0.istage2_mmu itb=system.cpu0.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -157,10 +169,35 @@ hit_latency=2 sequential_access=false size=32768 +[system.cpu0.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb +tlb=system.cpu0.dtb + +[system.cpu0.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu0.dstage2_mmu.stage2_tlb.walker + +[system.cpu0.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[5] + [system.cpu0.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu0.dtb.walker @@ -168,6 +205,7 @@ walker=system.cpu0.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[3] @@ -215,24 +253,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu0.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb +tlb=system.cpu0.itb + +[system.cpu0.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu0.istage2_mmu.stage2_tlb.walker + +[system.cpu0.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[4] [system.cpu0.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu0.itb.walker @@ -240,6 +314,7 @@ walker=system.cpu0.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[2] @@ -250,19 +325,21 @@ eventq_index=0 [system.cpu1] type=TimingSimpleCPU -children=dtb isa itb tracer +children=dstage2_mmu dtb isa istage2_mmu itb tracer checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu1.dstage2_mmu dtb=system.cpu1.dtb eventq_index=0 function_trace=false function_trace_start=0 interrupts=Null isa=system.cpu1.isa +istage2_mmu=system.cpu1.istage2_mmu itb=system.cpu1.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -277,10 +354,34 @@ system=system tracer=system.cpu1.tracer workload= +[system.cpu1.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb +tlb=system.cpu1.dtb + +[system.cpu1.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu1.dstage2_mmu.stage2_tlb.walker + +[system.cpu1.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system + [system.cpu1.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu1.dtb.walker @@ -288,6 +389,7 @@ walker=system.cpu1.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system @@ -295,24 +397,59 @@ sys=system type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu1.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb +tlb=system.cpu1.itb + +[system.cpu1.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu1.istage2_mmu.stage2_tlb.walker + +[system.cpu1.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system [system.cpu1.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu1.itb.walker @@ -320,6 +457,7 @@ walker=system.cpu1.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system @@ -329,7 +467,7 @@ eventq_index=0 [system.cpu2] type=DerivO3CPU -children=branchPred dtb fuPool isa itb tracer +children=branchPred dstage2_mmu dtb fuPool isa istage2_mmu itb tracer LFSTSize=1024 LQEntries=32 LSQCheckLoads=true @@ -355,6 +493,7 @@ dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu2.dstage2_mmu dtb=system.cpu2.dtb eventq_index=0 fetchBufferSize=64 @@ -373,6 +512,7 @@ interrupts=Null isa=system.cpu2.isa issueToExecuteDelay=1 issueWidth=8 +istage2_mmu=system.cpu2.istage2_mmu itb=system.cpu2.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -430,10 +570,34 @@ localPredictorSize=2048 numThreads=1 predType=tournament +[system.cpu2.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu2.dstage2_mmu.stage2_tlb +tlb=system.cpu2.dtb + +[system.cpu2.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu2.dstage2_mmu.stage2_tlb.walker + +[system.cpu2.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system + [system.cpu2.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu2.dtb.walker @@ -441,6 +605,7 @@ walker=system.cpu2.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system @@ -755,24 +920,59 @@ opLat=3 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu2.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu2.istage2_mmu.stage2_tlb +tlb=system.cpu2.itb + +[system.cpu2.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu2.istage2_mmu.stage2_tlb.walker + +[system.cpu2.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system [system.cpu2.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu2.itb.walker @@ -780,6 +980,7 @@ walker=system.cpu2.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system @@ -1418,7 +1619,7 @@ system=system use_default_range=false width=8 master=system.l2c.cpu_side -slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port +slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port [system.vncserver] type=VncServer diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr index d17b0e3b6..41d09e09d 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr @@ -11,8 +11,16 @@ warn: instruction 'mcr dccimvac' unimplemented warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented warn: LCD dual screen mode not supported -warn: instruction 'mcr icialluis' unimplemented -warn: instruction 'mcr bpiallis' unimplemented +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout index 05714643f..21d388ebd 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout @@ -1,8 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 23 2014 00:23:40 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 19:05:28 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full Global frequency set at 1000000000000 ticks per second + 0: system.cpu0.isa: ISA system set to: 0x5606400 0x5606400 + 0: system.cpu1.isa: ISA system set to: 0x5606400 0x5606400 + 0: system.cpu2.isa: ISA system set to: 0x5606400 0x5606400 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index f17311f85..6f0228b0e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -1,172 +1,168 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.403659 # Number of seconds simulated -sim_ticks 2403658742000 # Number of ticks simulated -final_tick 2403658742000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.403670 # Number of seconds simulated +sim_ticks 2403669993000 # Number of ticks simulated +final_tick 2403669993000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 228698 # Simulator instruction rate (inst/s) -host_op_rate 293732 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9112018126 # Simulator tick rate (ticks/s) -host_mem_usage 403420 # Number of bytes of host memory used -host_seconds 263.79 # Real time elapsed on the host -sim_insts 60328128 # Number of instructions simulated -sim_ops 77483556 # Number of ops (including micro ops) simulated +host_inst_rate 205695 # Simulator instruction rate (inst/s) +host_op_rate 264190 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8195476126 # Simulator tick rate (ticks/s) +host_mem_usage 425360 # Number of bytes of host memory used +host_seconds 293.29 # Real time elapsed on the host +sim_insts 60328724 # Number of instructions simulated +sim_ops 77484808 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 512480 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 7049296 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 512584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 7062488 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 64128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 674944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 186496 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1353888 # Number of bytes read from this memory -system.physmem.bytes_read::total 124661072 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 512480 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 64128 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 186496 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 763104 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3743872 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1298256 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 159304 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2.data 1558256 # Number of bytes written to this memory -system.physmem.bytes_written::total 6759688 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 64448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 676736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 704 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 184896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1338016 # Number of bytes read from this memory +system.physmem.bytes_read::total 124659200 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 512584 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 64448 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 184896 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 761928 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3742720 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1298604 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 159300 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2.data 1557912 # Number of bytes written to this memory +system.physmem.bytes_written::total 6758536 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14352384 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 14210 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 110179 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 14221 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 110387 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1002 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10546 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 7 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 2914 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 21162 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14512409 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 58498 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 324564 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 39826 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2.data 389564 # Number of write requests responded to by this memory -system.physmem.num_writes::total 812452 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47768458 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu1.inst 1007 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10574 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 11 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 2889 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 20914 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14512391 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 58480 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 324651 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 39825 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2.data 389478 # Number of write requests responded to by this memory +system.physmem.num_writes::total 812434 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47768235 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 53 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 213208 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 2932736 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 213251 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 2938210 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 26679 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 280799 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 186 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.itb.walker 27 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 77588 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 563261 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51863049 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 213208 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 26679 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 77588 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 317476 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1557572 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 540117 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 66276 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2.data 648285 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2812249 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1557572 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47768458 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 26812 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 281543 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 293 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 76922 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 556655 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51862028 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 213251 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 26812 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 76922 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 316985 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1557086 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 540259 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 66274 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2.data 648139 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2811757 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1557086 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47768235 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 53 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 213208 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3472852 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 213251 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3478469 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 26679 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 347074 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 186 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.itb.walker 27 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 77588 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1211546 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54675299 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 13477345 # Number of read requests accepted -system.physmem.writeReqs 446482 # Number of write requests accepted -system.physmem.readBursts 13477345 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 446482 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 862550080 # Total number of bytes read from DRAM +system.physmem.bw_total::cpu1.inst 26812 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 347816 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 293 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 76922 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1204794 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54673785 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 13478692 # Number of read requests accepted +system.physmem.writeReqs 446310 # Number of write requests accepted +system.physmem.readBursts 13478692 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 446310 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 862636288 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 2865536 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 109813728 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 2811448 # Total written bytes from the system interface side +system.physmem.bytesWritten 2859584 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 109811232 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 2805660 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 401707 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 2370 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 837716 # Per bank write bursts -system.physmem.perBankRdBursts::1 837382 # Per bank write bursts -system.physmem.perBankRdBursts::2 837561 # Per bank write bursts -system.physmem.perBankRdBursts::3 838016 # Per bank write bursts -system.physmem.perBankRdBursts::4 839132 # Per bank write bursts -system.physmem.perBankRdBursts::5 839847 # Per bank write bursts -system.physmem.perBankRdBursts::6 839973 # Per bank write bursts -system.physmem.perBankRdBursts::7 841200 # Per bank write bursts -system.physmem.perBankRdBursts::8 842679 # Per bank write bursts -system.physmem.perBankRdBursts::9 845377 # Per bank write bursts -system.physmem.perBankRdBursts::10 845421 # Per bank write bursts -system.physmem.perBankRdBursts::11 845910 # Per bank write bursts -system.physmem.perBankRdBursts::12 847235 # Per bank write bursts -system.physmem.perBankRdBursts::13 846991 # Per bank write bursts -system.physmem.perBankRdBursts::14 846262 # Per bank write bursts -system.physmem.perBankRdBursts::15 846643 # Per bank write bursts -system.physmem.perBankWrBursts::0 2727 # Per bank write bursts -system.physmem.perBankWrBursts::1 2580 # Per bank write bursts -system.physmem.perBankWrBursts::2 2569 # Per bank write bursts -system.physmem.perBankWrBursts::3 3046 # Per bank write bursts -system.physmem.perBankWrBursts::4 3472 # Per bank write bursts +system.physmem.mergedWrBursts 401628 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 2353 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 837730 # Per bank write bursts +system.physmem.perBankRdBursts::1 837377 # Per bank write bursts +system.physmem.perBankRdBursts::2 837570 # Per bank write bursts +system.physmem.perBankRdBursts::3 838005 # Per bank write bursts +system.physmem.perBankRdBursts::4 839135 # Per bank write bursts +system.physmem.perBankRdBursts::5 839829 # Per bank write bursts +system.physmem.perBankRdBursts::6 839954 # Per bank write bursts +system.physmem.perBankRdBursts::7 841188 # Per bank write bursts +system.physmem.perBankRdBursts::8 842692 # Per bank write bursts +system.physmem.perBankRdBursts::9 845268 # Per bank write bursts +system.physmem.perBankRdBursts::10 845422 # Per bank write bursts +system.physmem.perBankRdBursts::11 845904 # Per bank write bursts +system.physmem.perBankRdBursts::12 847097 # Per bank write bursts +system.physmem.perBankRdBursts::13 848027 # Per bank write bursts +system.physmem.perBankRdBursts::14 846853 # Per bank write bursts +system.physmem.perBankRdBursts::15 846641 # Per bank write bursts +system.physmem.perBankWrBursts::0 2732 # Per bank write bursts +system.physmem.perBankWrBursts::1 2567 # Per bank write bursts +system.physmem.perBankWrBursts::2 2586 # Per bank write bursts +system.physmem.perBankWrBursts::3 3040 # Per bank write bursts +system.physmem.perBankWrBursts::4 3458 # Per bank write bursts system.physmem.perBankWrBursts::5 3199 # Per bank write bursts -system.physmem.perBankWrBursts::6 2543 # Per bank write bursts -system.physmem.perBankWrBursts::7 2318 # Per bank write bursts -system.physmem.perBankWrBursts::8 2233 # Per bank write bursts -system.physmem.perBankWrBursts::9 2426 # Per bank write bursts -system.physmem.perBankWrBursts::10 2368 # Per bank write bursts -system.physmem.perBankWrBursts::11 2824 # Per bank write bursts -system.physmem.perBankWrBursts::12 3814 # Per bank write bursts -system.physmem.perBankWrBursts::13 3447 # Per bank write bursts -system.physmem.perBankWrBursts::14 2652 # Per bank write bursts -system.physmem.perBankWrBursts::15 2556 # Per bank write bursts +system.physmem.perBankWrBursts::6 2529 # Per bank write bursts +system.physmem.perBankWrBursts::7 2312 # Per bank write bursts +system.physmem.perBankWrBursts::8 2235 # Per bank write bursts +system.physmem.perBankWrBursts::9 2402 # Per bank write bursts +system.physmem.perBankWrBursts::10 2375 # Per bank write bursts +system.physmem.perBankWrBursts::11 2809 # Per bank write bursts +system.physmem.perBankWrBursts::12 3726 # Per bank write bursts +system.physmem.perBankWrBursts::13 3500 # Per bank write bursts +system.physmem.perBankWrBursts::14 2647 # Per bank write bursts +system.physmem.perBankWrBursts::15 2564 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2402623562000 # Total gap between requests +system.physmem.totGap 2402634752000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 8 # Read request sizes (log2) -system.physmem.readPktSize::3 13441712 # Read request sizes (log2) +system.physmem.readPktSize::3 13443296 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 35625 # Read request sizes (log2) +system.physmem.readPktSize::6 35388 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 429390 # Write request sizes (log2) +system.physmem.writePktSize::2 429303 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 17092 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 971418 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 948778 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 943230 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3279616 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2365953 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2365403 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2381873 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 45829 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 51923 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 17633 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 17632 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 17623 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 17610 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 17603 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 17598 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 17596 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 27 # What read queue length does an incoming req see +system.physmem.writePktSize::6 17007 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 975684 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 953327 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 947696 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3279847 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2361574 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2361279 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2377764 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 45945 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 51807 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 17784 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 17782 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 17747 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 17627 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 17611 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 17604 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 17597 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 17 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -182,30 +178,30 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2024 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2445 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2034 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2289 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2015 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2021 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1991 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1984 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1977 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1972 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1965 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1966 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1953 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1955 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1967 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1970 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 1961 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 1947 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 2054 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2021 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2411 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2033 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2279 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 2013 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 2034 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1987 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1980 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1972 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1967 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1961 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1951 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1954 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1961 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1959 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 1951 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 1942 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 2052 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 23 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see @@ -214,312 +210,317 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 48550 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 17825.239135 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 3190.498487 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 18342.849091 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-71 8610 17.73% 17.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-135 4856 10.00% 27.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-199 981 2.02% 29.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-263 733 1.51% 31.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-327 427 0.88% 32.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-391 370 0.76% 32.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-455 272 0.56% 33.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-519 308 0.63% 34.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-583 164 0.34% 34.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-647 164 0.34% 34.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-711 166 0.34% 35.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-775 231 0.48% 35.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-839 82 0.17% 35.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-903 88 0.18% 35.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-967 37 0.08% 36.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1031 306 0.63% 36.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1095 22 0.05% 36.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1159 33 0.07% 36.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1223 21 0.04% 36.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1287 99 0.20% 37.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1351 20 0.04% 37.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1415 170 0.35% 37.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1479 13 0.03% 37.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1543 137 0.28% 37.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1607 12 0.02% 37.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1671 29 0.06% 37.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1735 10 0.02% 37.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1799 139 0.29% 38.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1863 7 0.01% 38.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1927 11 0.02% 38.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1991 8 0.02% 38.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2055 378 0.78% 38.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2119 6 0.01% 38.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2183 7 0.01% 38.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2247 7 0.01% 38.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2311 70 0.14% 39.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2375 6 0.01% 39.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2439 4 0.01% 39.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2503 3 0.01% 39.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2567 71 0.15% 39.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2631 5 0.01% 39.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2695 4 0.01% 39.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2759 4 0.01% 39.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2823 9 0.02% 39.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2887 7 0.01% 39.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2951 7 0.01% 39.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3015 5 0.01% 39.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3079 411 0.85% 40.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3143 5 0.01% 40.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3207 4 0.01% 40.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3271 1 0.00% 40.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3335 132 0.27% 40.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3399 3 0.01% 40.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3463 6 0.01% 40.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3527 7 0.01% 40.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3591 67 0.14% 40.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3655 5 0.01% 40.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3719 5 0.01% 40.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3783 3 0.01% 40.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3847 73 0.15% 40.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3911 4 0.01% 40.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3975 6 0.01% 40.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4103 384 0.79% 41.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4167 7 0.01% 41.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4231 7 0.01% 41.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4295 3 0.01% 41.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4359 131 0.27% 41.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4423 8 0.02% 42.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4487 2 0.00% 42.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4551 2 0.00% 42.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4615 68 0.14% 42.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4679 2 0.00% 42.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4743 2 0.00% 42.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4807 5 0.01% 42.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4871 34 0.07% 42.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4935 2 0.00% 42.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4999 6 0.01% 42.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5063 4 0.01% 42.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5127 263 0.54% 42.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5191 1 0.00% 42.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5255 3 0.01% 42.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5319 5 0.01% 42.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5383 131 0.27% 43.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5447 4 0.01% 43.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5511 9 0.02% 43.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5575 3 0.01% 43.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5639 70 0.14% 43.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5703 3 0.01% 43.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5767 4 0.01% 43.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5831 5 0.01% 43.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5895 103 0.21% 43.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5959 1 0.00% 43.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6023 4 0.01% 43.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6087 9 0.02% 43.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6151 323 0.67% 44.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6215 3 0.01% 44.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6343 1 0.00% 44.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6407 4 0.01% 44.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6535 7 0.01% 44.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6663 82 0.17% 44.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6727 1 0.00% 44.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6791 8 0.02% 44.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6855 4 0.01% 44.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6919 3 0.01% 44.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7047 4 0.01% 44.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7111 2 0.00% 44.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7175 292 0.60% 45.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7303 2 0.00% 45.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7367 14 0.03% 45.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7431 4 0.01% 45.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7687 128 0.26% 45.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7943 65 0.13% 45.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8071 1 0.00% 45.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8199 415 0.85% 46.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8455 65 0.13% 46.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8711 128 0.26% 46.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9223 291 0.60% 47.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9479 1 0.00% 47.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9735 81 0.17% 47.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9991 3 0.01% 47.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10247 320 0.66% 48.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10503 64 0.13% 48.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10759 64 0.13% 48.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11015 128 0.26% 48.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11271 256 0.53% 49.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11527 32 0.07% 49.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11783 64 0.13% 49.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12039 128 0.26% 49.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12295 375 0.77% 50.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12551 68 0.14% 50.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12608-12615 1 0.00% 50.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12807 65 0.13% 50.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13063 125 0.26% 50.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13120-13127 1 0.00% 51.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13319 408 0.84% 51.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13575 1 0.00% 51.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13831 64 0.13% 51.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14087 64 0.13% 52.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14343 364 0.75% 52.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14400-14407 1 0.00% 52.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14599 128 0.26% 53.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14855 98 0.20% 53.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15111 70 0.14% 53.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15367 256 0.53% 53.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15623 65 0.13% 54.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16135 71 0.15% 54.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16391 644 1.33% 55.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16647 73 0.15% 55.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16832-16839 1 0.00% 55.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17159 65 0.13% 55.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17415 256 0.53% 56.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17671 68 0.14% 56.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17927 96 0.20% 56.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18183 128 0.26% 57.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18439 364 0.75% 57.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18695 64 0.13% 57.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18944-18951 64 0.13% 58.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19008-19015 1 0.00% 58.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19207 1 0.00% 58.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19463 407 0.84% 58.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19719 125 0.26% 59.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19968-19975 65 0.13% 59.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20231 70 0.14% 59.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20288-20295 1 0.00% 59.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20487 376 0.77% 60.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20736-20743 127 0.26% 60.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-20999 64 0.13% 60.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21248-21255 29 0.06% 60.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21511 256 0.53% 61.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21767 128 0.26% 61.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22023 64 0.13% 61.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22279 65 0.13% 61.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22535 320 0.66% 62.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22791 3 0.01% 62.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23040-23047 82 0.17% 62.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23559 292 0.60% 63.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24071 129 0.27% 63.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24327 64 0.13% 63.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24583 414 0.85% 64.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24839 65 0.13% 64.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25088-25095 129 0.27% 64.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25607 291 0.60% 65.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25728-25735 1 0.00% 65.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26112-26119 80 0.16% 65.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26375 4 0.01% 65.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26631 320 0.66% 66.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26880-26887 65 0.13% 66.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27143 64 0.13% 66.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27399 128 0.26% 66.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27655 256 0.53% 67.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27911 32 0.07% 67.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28160-28167 65 0.13% 67.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28423 128 0.26% 67.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28679 377 0.78% 68.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28935 68 0.14% 68.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29120-29127 1 0.00% 68.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29191 65 0.13% 68.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29447 125 0.26% 69.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29703 410 0.84% 69.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-29959 1 0.00% 69.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30208-30215 64 0.13% 70.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30471 65 0.13% 70.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30727 363 0.75% 70.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-30983 129 0.27% 71.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31239 96 0.20% 71.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31488-31495 68 0.14% 71.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31751 256 0.53% 72.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32000-32007 64 0.13% 72.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32128-32135 1 0.00% 72.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32512-32519 72 0.15% 72.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32775 642 1.32% 73.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33031 72 0.15% 73.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33408-33415 1 0.00% 73.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33543 63 0.13% 73.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33799 256 0.53% 74.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34048-34055 68 0.14% 74.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34304-34311 96 0.20% 74.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34560-34567 128 0.26% 75.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34823 363 0.75% 75.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35072-35079 64 0.13% 75.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35328-35335 64 0.13% 76.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35584-35591 1 0.00% 76.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35847 410 0.84% 76.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36096-36103 125 0.26% 77.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36352-36359 65 0.13% 77.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36608-36615 68 0.14% 77.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36864-36871 376 0.77% 78.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37120-37127 128 0.26% 78.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37376-37383 65 0.13% 78.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37632-37639 32 0.07% 78.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37895 256 0.53% 79.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38144-38151 128 0.26% 79.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38400-38407 64 0.13% 79.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38656-38663 65 0.13% 79.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38912-38919 320 0.66% 80.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39168-39175 4 0.01% 80.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39424-39431 80 0.16% 80.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39808-39815 1 0.00% 80.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39936-39943 292 0.60% 81.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40448-40455 129 0.27% 81.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40704-40711 65 0.13% 81.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40960-40967 413 0.85% 82.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41216-41223 64 0.13% 82.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41472-41479 129 0.27% 82.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-41991 292 0.60% 83.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42496-42503 82 0.17% 83.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42752-42759 3 0.01% 83.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43008-43015 320 0.66% 84.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43264-43271 65 0.13% 84.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43520-43527 65 0.13% 84.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43776-43783 128 0.26% 84.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44032-44039 256 0.53% 85.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44160-44167 1 0.00% 85.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44288-44295 29 0.06% 85.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44544-44551 64 0.13% 85.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44800-44807 127 0.26% 85.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45056-45063 375 0.77% 86.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45248-45255 1 0.00% 86.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45312-45319 70 0.14% 86.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45376-45383 1 0.00% 86.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45568-45575 64 0.13% 86.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45824-45831 125 0.26% 87.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46087 406 0.84% 87.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46528-46535 1 0.00% 87.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46592-46599 64 0.13% 88.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46848-46855 64 0.13% 88.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47104-47111 364 0.75% 88.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47360-47367 128 0.26% 89.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47616-47623 96 0.20% 89.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47872-47879 69 0.14% 89.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48135 258 0.53% 90.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48384-48391 67 0.14% 90.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48903 71 0.15% 90.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48960-48967 1 0.00% 90.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49088-49095 2 0.00% 90.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49159 4686 9.65% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 48550 # Bytes accessed per row activation -system.physmem.totQLat 326412969750 # Total ticks spent queuing -system.physmem.totMemAccLat 407861489750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 67386725000 # Total ticks spent in databus transfers -system.physmem.totBankLat 14061795000 # Total ticks spent accessing banks -system.physmem.avgQLat 24219.38 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1043.37 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::samples 48746 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 17755.207812 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 3162.737998 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 18340.275925 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 8642 17.73% 17.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 4876 10.00% 27.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 980 2.01% 29.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 745 1.53% 31.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 418 0.86% 32.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 375 0.77% 32.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 281 0.58% 33.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 311 0.64% 34.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 181 0.37% 34.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 171 0.35% 34.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 151 0.31% 35.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-775 290 0.59% 35.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-839 88 0.18% 35.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-903 76 0.16% 36.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 42 0.09% 36.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 366 0.75% 36.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 30 0.06% 36.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1159 31 0.06% 37.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1223 22 0.05% 37.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1287 117 0.24% 37.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1351 19 0.04% 37.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1415 158 0.32% 37.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1479 20 0.04% 37.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1543 128 0.26% 37.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1607 11 0.02% 38.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1671 28 0.06% 38.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1735 10 0.02% 38.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1799 148 0.30% 38.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1863 9 0.02% 38.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1927 16 0.03% 38.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1991 10 0.02% 38.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2055 383 0.79% 39.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2119 3 0.01% 39.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2183 7 0.01% 39.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2247 5 0.01% 39.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2311 66 0.14% 39.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2375 1 0.00% 39.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2439 3 0.01% 39.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2503 4 0.01% 39.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2567 69 0.14% 39.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2631 2 0.00% 39.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2695 6 0.01% 39.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2759 3 0.01% 39.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2823 75 0.15% 39.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2887 2 0.00% 39.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2951 8 0.02% 39.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3015 2 0.00% 39.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3079 346 0.71% 40.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3143 5 0.01% 40.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3207 4 0.01% 40.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3271 4 0.01% 40.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3335 130 0.27% 40.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3399 5 0.01% 40.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3463 2 0.00% 40.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3527 3 0.01% 40.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3591 69 0.14% 40.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3655 1 0.00% 40.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3719 8 0.02% 40.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3783 5 0.01% 40.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3847 77 0.16% 41.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3911 8 0.02% 41.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3975 4 0.01% 41.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4039 6 0.01% 41.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4103 331 0.68% 41.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4167 5 0.01% 41.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4231 3 0.01% 41.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4295 5 0.01% 41.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4359 190 0.39% 42.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4423 12 0.02% 42.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4487 4 0.01% 42.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4551 3 0.01% 42.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4615 36 0.07% 42.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4679 4 0.01% 42.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4743 2 0.00% 42.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4807 4 0.01% 42.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4871 136 0.28% 42.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4935 1 0.00% 42.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5063 2 0.00% 42.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5127 260 0.53% 43.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5191 1 0.00% 43.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5255 3 0.01% 43.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5319 4 0.01% 43.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5383 67 0.14% 43.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5447 4 0.01% 43.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5511 3 0.01% 43.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5575 3 0.01% 43.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5639 70 0.14% 43.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5767 2 0.00% 43.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5831 4 0.01% 43.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5895 103 0.21% 43.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5959 1 0.00% 43.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6023 1 0.00% 43.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6087 9 0.02% 43.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6151 324 0.66% 44.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6279 6 0.01% 44.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6343 1 0.00% 44.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6407 4 0.01% 44.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6471 4 0.01% 44.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6535 5 0.01% 44.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6599 2 0.00% 44.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6663 69 0.14% 44.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6727 2 0.00% 44.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6791 7 0.01% 44.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6855 1 0.00% 44.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6919 3 0.01% 44.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6983 3 0.01% 44.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7047 2 0.00% 44.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7111 1 0.00% 44.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7175 295 0.61% 45.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7239 2 0.00% 45.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7303 2 0.00% 45.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7367 10 0.02% 45.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7559 2 0.00% 45.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7687 128 0.26% 45.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7943 1 0.00% 45.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8199 539 1.11% 46.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8455 1 0.00% 46.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8711 128 0.26% 46.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9223 294 0.60% 47.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9479 1 0.00% 47.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9600-9607 1 0.00% 47.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9735 65 0.13% 47.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9991 1 0.00% 47.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10247 320 0.66% 48.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10503 64 0.13% 48.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10759 64 0.13% 48.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11015 64 0.13% 48.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11271 256 0.53% 49.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11527 129 0.26% 49.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11783 31 0.06% 49.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12039 181 0.37% 49.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12295 323 0.66% 50.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12551 68 0.14% 50.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12807 64 0.13% 50.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12864-12871 1 0.00% 50.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13063 126 0.26% 51.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13248-13255 1 0.00% 51.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13319 342 0.70% 51.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13575 68 0.14% 51.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13831 65 0.13% 52.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13888-13895 1 0.00% 52.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14087 64 0.13% 52.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14343 368 0.75% 53.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14599 128 0.26% 53.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14855 90 0.18% 53.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15111 84 0.17% 53.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15367 265 0.54% 54.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15623 64 0.13% 54.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16135 70 0.14% 54.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16391 644 1.32% 55.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16647 70 0.14% 55.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17159 65 0.13% 56.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17415 266 0.55% 56.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17671 82 0.17% 56.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17927 88 0.18% 56.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17984-17991 1 0.00% 56.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18183 127 0.26% 57.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18439 370 0.76% 57.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18688-18695 64 0.13% 58.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18944-18951 65 0.13% 58.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19207 69 0.14% 58.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19463 339 0.70% 59.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19712-19719 125 0.26% 59.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19904-19911 1 0.00% 59.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19968-19975 64 0.13% 59.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20224-20231 70 0.14% 59.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20487 325 0.67% 60.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20736-20743 182 0.37% 60.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20992-20999 30 0.06% 60.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21248-21255 127 0.26% 60.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21312-21319 1 0.00% 60.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21511 256 0.53% 61.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21632-21639 1 0.00% 61.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21760-21767 65 0.13% 61.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22016-22023 64 0.13% 61.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22272-22279 65 0.13% 61.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22535 320 0.66% 62.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23040-23047 66 0.14% 62.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23559 292 0.60% 63.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23808-23815 1 0.00% 63.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24064-24071 129 0.26% 63.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24384-24391 1 0.00% 63.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24583 538 1.10% 64.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25088-25095 129 0.26% 64.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25344-25351 1 0.00% 64.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25607 292 0.60% 65.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26112-26119 65 0.13% 65.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26631 320 0.66% 66.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26880-26887 65 0.13% 66.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27136-27143 64 0.13% 66.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27399 64 0.13% 66.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27655 257 0.53% 67.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27911 128 0.26% 67.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28032-28039 1 0.00% 67.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28160-28167 31 0.06% 67.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28423 182 0.37% 67.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28679 324 0.66% 68.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28935 69 0.14% 68.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29191 64 0.13% 68.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29447 126 0.26% 69.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29703 341 0.70% 69.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-29959 69 0.14% 69.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30215 64 0.13% 70.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30471 64 0.13% 70.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30656-30663 1 0.00% 70.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30727 368 0.75% 70.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-30983 128 0.26% 71.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31104-31111 1 0.00% 71.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31239 88 0.18% 71.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31495 82 0.17% 71.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31552-31559 1 0.00% 71.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31751 266 0.55% 72.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32007 64 0.13% 72.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32519 69 0.14% 72.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32775 642 1.32% 73.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33031 69 0.14% 73.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33287 1 0.00% 73.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33543 64 0.13% 74.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33799 265 0.54% 74.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33984-33991 1 0.00% 74.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34048-34055 82 0.17% 74.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34240-34247 1 0.00% 74.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34304-34311 88 0.18% 74.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34432-34439 1 0.00% 74.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34560-34567 128 0.26% 75.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34823 367 0.75% 75.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34880-34887 1 0.00% 75.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35072-35079 64 0.13% 76.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35328-35335 64 0.13% 76.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35456-35463 1 0.00% 76.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35584-35591 69 0.14% 76.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35847 341 0.70% 77.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36096-36103 126 0.26% 77.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36352-36359 64 0.13% 77.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36608-36615 69 0.14% 77.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36871 323 0.66% 78.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37120-37127 182 0.37% 78.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37376-37383 31 0.06% 78.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37504-37511 1 0.00% 78.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37632-37639 129 0.26% 78.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37895 256 0.53% 79.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38151 64 0.13% 79.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38400-38407 64 0.13% 79.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38656-38663 65 0.13% 79.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38919 320 0.66% 80.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39424-39431 65 0.13% 80.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39936-39943 292 0.60% 81.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40448-40455 129 0.26% 81.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40967 537 1.10% 82.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41152-41159 1 0.00% 82.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41472-41479 129 0.26% 82.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-41991 293 0.60% 83.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42503 66 0.14% 83.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43015 320 0.66% 84.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43271 65 0.13% 84.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43527 65 0.13% 84.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43776-43783 64 0.13% 84.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43904-43911 1 0.00% 84.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 255 0.52% 85.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44224-44231 2 0.00% 85.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44295 127 0.26% 85.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44551 30 0.06% 85.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44807 181 0.37% 85.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 323 0.66% 86.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45319 69 0.14% 86.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 64 0.13% 86.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 125 0.26% 87.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 338 0.69% 87.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46343 70 0.14% 87.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46599 65 0.13% 88.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 64 0.13% 88.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 369 0.76% 88.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 127 0.26% 89.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47552-47559 1 0.00% 89.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 90 0.18% 89.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 82 0.17% 89.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 266 0.55% 90.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 67 0.14% 90.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 69 0.14% 90.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48960-48967 2 0.00% 90.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 4685 9.61% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 48746 # Bytes accessed per row activation +system.physmem.totQLat 326451020750 # Total ticks spent queuing +system.physmem.totMemAccLat 407972275750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 67393460000 # Total ticks spent in databus transfers +system.physmem.totBankLat 14127795000 # Total ticks spent accessing banks +system.physmem.avgQLat 24219.78 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1048.16 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30262.75 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 358.85 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 30267.94 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 358.88 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.19 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 45.69 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 45.68 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 1.17 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 2.81 # Data bus utilization in percentage system.physmem.busUtilRead 2.80 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.17 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.37 # Average write queue length when enqueuing -system.physmem.readRowHits 13434104 # Number of row buffer hits during reads -system.physmem.writeRowHits 39465 # Number of row buffer hits during writes +system.physmem.avgWrQLen 0.38 # Average write queue length when enqueuing +system.physmem.readRowHits 13435238 # Number of row buffer hits during reads +system.physmem.writeRowHits 39389 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.68 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 88.14 # Row buffer hit rate for writes -system.physmem.avgGap 172554.83 # Average gap between requests +system.physmem.writeRowHitRate 88.15 # Row buffer hit rate for writes +system.physmem.avgGap 172541.07 # Average gap between requests system.physmem.pageHitRate 99.64 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.75 # Percentage of time for which DRAM has all the banks in precharge state +system.physmem.prechargeAllPercent 0.88 # Percentage of time for which DRAM has all the banks in precharge state system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory @@ -532,336 +533,322 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 8 system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 55672581 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 13813538 # Transaction distribution -system.membus.trans_dist::ReadResp 13813538 # Transaction distribution -system.membus.trans_dist::WriteReq 432230 # Transaction distribution -system.membus.trans_dist::WriteResp 432230 # Transaction distribution -system.membus.trans_dist::Writeback 17092 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2370 # Transaction distribution -system.membus.trans_dist::UpgradeResp 2370 # Transaction distribution -system.membus.trans_dist::ReadExReq 28046 # Transaction distribution -system.membus.trans_dist::ReadExResp 28046 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 733938 # Packet count per connected master and slave (bytes) +system.membus.throughput 55671057 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 13813895 # Transaction distribution +system.membus.trans_dist::ReadResp 13813895 # Transaction distribution +system.membus.trans_dist::WriteReq 432143 # Transaction distribution +system.membus.trans_dist::WriteResp 432143 # Transaction distribution +system.membus.trans_dist::Writeback 17007 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2353 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2353 # Transaction distribution +system.membus.trans_dist::ReadExReq 27827 # Transaction distribution +system.membus.trans_dist::ReadExResp 27827 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 731520 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 220 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 951878 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1686036 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 26883424 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 26883424 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 28569460 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 737821 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 951111 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1682851 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 26886592 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 26886592 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 28569443 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 735400 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 440 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 5091480 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 5829741 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 107533696 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 107533696 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 113363437 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 133817886 # Total data (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 5070524 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 5806364 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 107546368 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 107546368 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 113352732 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 133814850 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 418359500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 416796500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 204500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 205000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 14607428500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 14608293500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 1598779620 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1594356888 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 30355600750 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 30359701500 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 63253 # number of replacements -system.l2c.tags.tagsinuse 50392.264505 # Cycle average of tags in use -system.l2c.tags.total_refs 1749443 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 128649 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.598574 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2375574111000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 36861.205107 # Average occupied blocks per requestor +system.l2c.tags.replacements 63223 # number of replacements +system.l2c.tags.tagsinuse 50383.450720 # Cycle average of tags in use +system.l2c.tags.total_refs 1749716 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 128619 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.603869 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2375590593500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 36838.052028 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000018 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000124 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5227.235315 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3840.097341 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5233.374732 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3836.748090 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.993317 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 502.876093 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 689.542033 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 6.851035 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.itb.walker 0.974650 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1682.063126 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 1580.426346 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.562457 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu1.inst 504.839969 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 688.402361 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 10.761256 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1676.159647 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 1594.119177 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.562104 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.079761 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.058595 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.079855 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.058544 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.007673 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.010522 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000105 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.itb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.025666 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.024115 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.768925 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 2 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65394 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id +system.l2c.tags.occ_percent::cpu1.inst 0.007703 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.010504 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000164 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.025576 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.024324 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.768790 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65391 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 340 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2645 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6480 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55890 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000031 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.997833 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 17683343 # Number of tag accesses -system.l2c.tags.data_accesses 17683343 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 8706 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3165 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 467858 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 176725 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 2609 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1184 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 130025 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 64311 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 18749 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 4292 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 281381 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 132168 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1291173 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 597611 # number of Writeback hits -system.l2c.Writeback_hits::total 597611 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 14 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 4 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 13 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 31 # number of UpgradeReq hits +system.l2c.tags.age_task_id_blocks_1024::1 342 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2635 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6483 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 55892 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.997787 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 17682479 # Number of tag accesses +system.l2c.tags.data_accesses 17682479 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 8678 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 3134 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 467928 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 176815 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 2613 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 1177 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 128266 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 64331 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 18618 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 4179 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 283323 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 132022 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1291084 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 597612 # number of Writeback hits +system.l2c.Writeback_hits::total 597612 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 13 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 5 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2.data 12 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 30 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu2.data 2 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 61949 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 18453 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 33219 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 113621 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 8706 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3165 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 467858 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 238674 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 2609 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 1184 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 130025 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 82764 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 18749 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 4292 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 281381 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 165387 # number of demand (read+write) hits -system.l2c.demand_hits::total 1404794 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 8706 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 3165 # number of overall hits -system.l2c.overall_hits::cpu0.inst 467858 # number of overall hits -system.l2c.overall_hits::cpu0.data 238674 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 2609 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 1184 # number of overall hits -system.l2c.overall_hits::cpu1.inst 130025 # number of overall hits -system.l2c.overall_hits::cpu1.data 82764 # number of overall hits -system.l2c.overall_hits::cpu2.dtb.walker 18749 # number of overall hits -system.l2c.overall_hits::cpu2.itb.walker 4292 # number of overall hits -system.l2c.overall_hits::cpu2.inst 281381 # number of overall hits -system.l2c.overall_hits::cpu2.data 165387 # number of overall hits -system.l2c.overall_hits::total 1404794 # number of overall hits +system.l2c.ReadExReq_hits::cpu0.data 61918 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 18367 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2.data 33347 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 113632 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 8678 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 3134 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 467928 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 238733 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 2613 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 1177 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 128266 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 82698 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.dtb.walker 18618 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.itb.walker 4179 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 283323 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 165369 # number of demand (read+write) hits +system.l2c.demand_hits::total 1404716 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 8678 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 3134 # number of overall hits +system.l2c.overall_hits::cpu0.inst 467928 # number of overall hits +system.l2c.overall_hits::cpu0.data 238733 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 2613 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 1177 # number of overall hits +system.l2c.overall_hits::cpu1.inst 128266 # number of overall hits +system.l2c.overall_hits::cpu1.data 82698 # number of overall hits +system.l2c.overall_hits::cpu2.dtb.walker 18618 # number of overall hits +system.l2c.overall_hits::cpu2.itb.walker 4179 # number of overall hits +system.l2c.overall_hits::cpu2.inst 283323 # number of overall hits +system.l2c.overall_hits::cpu2.data 165369 # number of overall hits +system.l2c.overall_hits::total 1404716 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 7594 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6477 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 7595 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 6472 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 1002 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1121 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.dtb.walker 7 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 2915 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 2544 # number of ReadReq misses -system.l2c.ReadReq_misses::total 21665 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1413 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 467 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 1028 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2908 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 104452 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 9697 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 19224 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 133373 # number of ReadExReq misses +system.l2c.ReadReq_misses::cpu1.inst 1007 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 1114 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.dtb.walker 11 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.inst 2890 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.data 2549 # number of ReadReq misses +system.l2c.ReadReq_misses::total 21642 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1432 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 464 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 1010 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2906 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 104665 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 9733 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 18973 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 133371 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 7594 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 110929 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 7595 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 111137 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1002 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 10818 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.dtb.walker 7 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 2915 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 21768 # number of demand (read+write) misses -system.l2c.demand_misses::total 155038 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 1007 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 10847 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.dtb.walker 11 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 2890 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 21522 # number of demand (read+write) misses +system.l2c.demand_misses::total 155013 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 7594 # number of overall misses -system.l2c.overall_misses::cpu0.data 110929 # number of overall misses +system.l2c.overall_misses::cpu0.inst 7595 # number of overall misses +system.l2c.overall_misses::cpu0.data 111137 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1002 # number of overall misses -system.l2c.overall_misses::cpu1.data 10818 # number of overall misses -system.l2c.overall_misses::cpu2.dtb.walker 7 # number of overall misses -system.l2c.overall_misses::cpu2.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu2.inst 2915 # number of overall misses -system.l2c.overall_misses::cpu2.data 21768 # number of overall misses -system.l2c.overall_misses::total 155038 # number of overall misses +system.l2c.overall_misses::cpu1.inst 1007 # number of overall misses +system.l2c.overall_misses::cpu1.data 10847 # number of overall misses +system.l2c.overall_misses::cpu2.dtb.walker 11 # number of overall misses +system.l2c.overall_misses::cpu2.inst 2890 # number of overall misses +system.l2c.overall_misses::cpu2.data 21522 # number of overall misses +system.l2c.overall_misses::total 155013 # number of overall misses system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 74500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 72874750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 86399250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 538750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.itb.walker 75000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 221844500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 200958749 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 582765499 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 93996 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2.data 162493 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 256489 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 729445478 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 1446208147 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 2175653625 # number of ReadExReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 72811500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 86760500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 823500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.inst 218694500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.data 200617750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 579782250 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 116995 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2.data 138994 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 255989 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 735376977 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 1427662394 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 2163039371 # number of ReadExReq miss cycles system.l2c.demand_miss_latency::cpu1.dtb.walker 74500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 72874750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 815844728 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.dtb.walker 538750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.itb.walker 75000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 221844500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 1647166896 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 2758419124 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 72811500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 822137477 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.dtb.walker 823500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 218694500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 1628280144 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 2742821621 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu1.dtb.walker 74500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 72874750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 815844728 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.dtb.walker 538750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.itb.walker 75000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 221844500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 1647166896 # number of overall miss cycles -system.l2c.overall_miss_latency::total 2758419124 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 8707 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 3167 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 475452 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 183202 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 2610 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 1184 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 131027 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 65432 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.dtb.walker 18756 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.itb.walker 4293 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 284296 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.data 134712 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1312838 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 597611 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 597611 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 1427 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 471 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 1041 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2939 # number of UpgradeReq accesses(hits+misses) +system.l2c.overall_miss_latency::cpu1.inst 72811500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 822137477 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.dtb.walker 823500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 218694500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 1628280144 # number of overall miss cycles +system.l2c.overall_miss_latency::total 2742821621 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 8679 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 3136 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 475523 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 183287 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 2614 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 1177 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 129273 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 65445 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.dtb.walker 18629 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.itb.walker 4179 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.inst 286213 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.data 134571 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1312726 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 597612 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 597612 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 1445 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 469 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 1022 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2936 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu2.data 2 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 166401 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 28150 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 52443 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 246994 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 8707 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 3167 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 475452 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 349603 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 2610 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 1184 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 131027 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 93582 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.dtb.walker 18756 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.itb.walker 4293 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 284296 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 187155 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1559832 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 8707 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 3167 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 475452 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 349603 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 2610 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 1184 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 131027 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 93582 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.dtb.walker 18756 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.itb.walker 4293 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 284296 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 187155 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1559832 # number of overall (read+write) accesses +system.l2c.ReadExReq_accesses::cpu0.data 166583 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 28100 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 52320 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 247003 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 8679 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 3136 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 475523 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 349870 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 2614 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 1177 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 129273 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 93545 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.dtb.walker 18629 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.itb.walker 4179 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 286213 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 186891 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1559729 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 8679 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 3136 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 475523 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 349870 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 2614 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 1177 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 129273 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 93545 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.dtb.walker 18629 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.itb.walker 4179 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 286213 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 186891 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1559729 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000115 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000632 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000638 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.inst 0.015972 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.035354 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.035311 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000383 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.007647 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.017132 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000373 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.itb.walker 0.000233 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.010253 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.018885 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.016502 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.990189 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.991507 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2.data 0.987512 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.989452 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.627713 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.344476 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2.data 0.366569 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.539985 # miss rate for ReadExReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.007790 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.017022 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000590 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.inst 0.010097 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.data 0.018942 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.016486 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.991003 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.989339 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2.data 0.988258 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.989782 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.628305 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.346370 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2.data 0.362634 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.539957 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000115 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000632 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000638 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.inst 0.015972 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.317300 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.317652 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000383 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.007647 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.115599 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000373 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.itb.walker 0.000233 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.010253 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.116310 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.099394 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.007790 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.115955 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000590 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.010097 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.115158 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.099385 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000115 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000632 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000638 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.inst 0.015972 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.317300 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.317652 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000383 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.007647 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.115599 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000373 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.itb.walker 0.000233 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.010253 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.116310 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.099394 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.007790 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.115955 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000590 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.010097 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.115158 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.099385 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 74500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72729.291417 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 77073.371989 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 76964.285714 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker 75000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 76104.459691 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.data 78993.218947 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 26898.938334 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 201.276231 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 158.067121 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 88.201169 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 75223.829844 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 75229.304359 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 16312.549204 # average ReadExReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72305.362463 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 77881.956912 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 74863.636364 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.inst 75672.837370 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.data 78704.491958 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 26789.679789 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 252.144397 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 137.617822 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 88.089814 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 75555.016644 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 75247.056027 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 16218.213637 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 74500 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 72729.291417 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 75415.486042 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 76964.285714 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.itb.walker 75000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 76104.459691 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 75669.188534 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 17791.890530 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 72305.362463 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 75793.996220 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 74863.636364 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 75672.837370 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 75656.544187 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 17694.139337 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 74500 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 72729.291417 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 75415.486042 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 76964.285714 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.itb.walker 75000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 76104.459691 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 75669.188534 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 17791.890530 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 72305.362463 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 75793.996220 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 74863.636364 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 75672.837370 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 75656.544187 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 17694.139337 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -870,146 +857,134 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 58498 # number of writebacks -system.l2c.writebacks::total 58498 # number of writebacks +system.l2c.writebacks::writebacks 58480 # number of writebacks +system.l2c.writebacks::total 58480 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu2.inst 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu2.data 11 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 12 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu2.data 10 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu2.inst 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2.data 11 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 12 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2.data 10 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu2.inst 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2.data 11 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 12 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2.data 10 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 1002 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 1121 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 7 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.inst 2914 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.data 2533 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 7579 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 467 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 1028 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 1495 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 9697 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2.data 19224 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 28921 # number of ReadExReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 1007 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 1114 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 11 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.inst 2889 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.data 2539 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 7561 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 464 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 1010 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 1474 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 9733 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2.data 18973 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 28706 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu1.dtb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 1002 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 10818 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.dtb.walker 7 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.inst 2914 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.data 21757 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 36500 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 1007 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 10847 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.dtb.walker 11 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 2889 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.data 21512 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 36267 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu1.dtb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 1002 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 10818 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.dtb.walker 7 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.inst 2914 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.data 21757 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 36500 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 1007 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 10847 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.dtb.walker 11 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.inst 2889 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.data 21512 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 36267 # number of overall MSHR misses system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 62500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 60159250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 72443750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 451250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker 62500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 185254250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.data 168538249 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 486971749 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4670967 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 10281028 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 14951995 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 606663522 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1206372353 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 1813035875 # number of ReadExReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 60036000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 72891500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 687500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 182410250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.data 168409750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 484497500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4640464 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 10101010 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 14741474 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 612184523 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1191173106 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1803357629 # number of ReadExReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 62500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 60159250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 679107272 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 451250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.itb.walker 62500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 185254250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 1374910602 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 2300007624 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 60036000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 685076023 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 687500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 182410250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 1359582856 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 2287855129 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 62500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 60159250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 679107272 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 451250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.itb.walker 62500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 185254250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 1374910602 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 2300007624 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 25039931500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 26362168250 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 51402099750 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 935202510 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 8516244000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 9451446510 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 25975134010 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2.data 34878412250 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 60853546260 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 60036000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 685076023 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 687500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 182410250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 1359582856 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 2287855129 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 25078473000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 26153900000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 51232373000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 935173509 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 8511559500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 9446733009 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 26013646509 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 34665459500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 60679106009 # number of overall MSHR uncacheable cycles system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000383 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.007647 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.017132 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000373 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker 0.000233 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.010250 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.018803 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.005773 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.991507 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.987512 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.508676 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.344476 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.366569 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.117092 # mshr miss rate for ReadExReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.007790 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.017022 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000590 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.010094 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.018867 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.005760 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.989339 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.988258 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.502044 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.346370 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.362634 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.116217 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000383 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007647 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.115599 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000373 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.000233 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.010250 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.116251 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.023400 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007790 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.115955 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000590 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.010094 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.115105 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.023252 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000383 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007647 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.115599 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000373 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.000233 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.010250 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.116251 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.023400 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007790 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.115955 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000590 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.010094 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.115105 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.023252 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60039.171657 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 64624.219447 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 64464.285714 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 63573.867536 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 66537.011054 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 64252.770682 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10002.070664 # average UpgradeReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 59618.669315 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65432.226212 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 62500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 63139.581170 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 66329.165026 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 64078.494908 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.334448 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62561.980200 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 62753.451571 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 62689.252619 # average ReadExReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62897.824206 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 62782.538660 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 62821.627151 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60039.171657 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62775.676835 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 64464.285714 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63573.867536 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 63193.942271 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 63013.907507 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59618.669315 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 63158.110353 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 62500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63139.581170 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 63201.136854 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 63083.660876 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60039.171657 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62775.676835 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 64464.285714 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63573.867536 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 63193.942271 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 63013.907507 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59618.669315 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63158.110353 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 62500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63139.581170 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 63201.136854 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 63083.660876 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1026,52 +1001,52 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 58816500 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 1021450 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 1021449 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 432230 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 432230 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 265546 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 1512 # Transaction distribution +system.toL2Bus.throughput 58820773 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 1019834 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 1019833 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 432143 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 432143 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 265318 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 1491 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1514 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 80593 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 80593 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 831311 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2423002 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 15637 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 52276 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 3322226 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 26580608 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 37417965 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 21908 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 85464 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 64105945 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 141275262 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 99532 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 2179112263 # Layer occupancy (ticks) +system.toL2Bus.trans_dist::UpgradeResp 1493 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 80420 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 80420 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 831638 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2419538 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 15322 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 51904 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 3318402 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 26591040 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 37381340 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 21424 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 84972 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 64078776 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 141286926 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 98800 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 2177097249 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1872836168 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1873558443 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1848885181 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1846163669 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 10174967 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 9980966 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 31036489 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 30796222 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48762826 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 13805907 # Transaction distribution -system.iobus.trans_dist::ReadResp 13805907 # Transaction distribution +system.iobus.throughput 48762593 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 13806282 # Transaction distribution +system.iobus.trans_dist::ReadResp 13806282 # Transaction distribution system.iobus.trans_dist::WriteReq 2774 # Transaction distribution system.iobus.trans_dist::WriteResp 2774 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 11404 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 3028 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 3024 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 20 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 256 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 718942 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 716528 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -1087,18 +1062,18 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 733938 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 26883424 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::total 26883424 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 27617362 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 731520 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 26886592 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 26886592 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 27618112 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 15368 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 6056 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 6048 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 40 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 512 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 715269 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 712856 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1114,14 +1089,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 737821 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 107533696 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::total 107533696 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 108271517 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 117209194 # Total data (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 735400 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 107546368 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::total 107546368 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 108281768 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 117209182 # Total data (bytes) system.iobus.reqLayer0.occupancy 7964000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 1514000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 1512000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 20000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1133,7 +1108,7 @@ system.iobus.reqLayer5.occupancy 8000 # La system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 359973000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 358766000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) @@ -1165,459 +1140,501 @@ system.iobus.reqLayer22.occupancy 8000 # La system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 13441712000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 13443296000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 731164000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 728746000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 36852557250 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 36856311500 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) +system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7990938 # DTB read hits -system.cpu0.dtb.read_misses 6181 # DTB read misses -system.cpu0.dtb.write_hits 6591681 # DTB write hits -system.cpu0.dtb.write_misses 1989 # DTB write misses -system.cpu0.dtb.flush_tlb 279 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 7990923 # DTB read hits +system.cpu0.dtb.read_misses 6211 # DTB read misses +system.cpu0.dtb.write_hits 6594140 # DTB write hits +system.cpu0.dtb.write_misses 1982 # DTB write misses +system.cpu0.dtb.flush_tlb 556 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 674 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5665 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 681 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 29 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 5674 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 119 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 122 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 208 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7997119 # DTB read accesses -system.cpu0.dtb.write_accesses 6593670 # DTB write accesses +system.cpu0.dtb.perms_faults 210 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 7997134 # DTB read accesses +system.cpu0.dtb.write_accesses 6596122 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14582619 # DTB hits -system.cpu0.dtb.misses 8170 # DTB misses -system.cpu0.dtb.accesses 14590789 # DTB accesses -system.cpu0.itb.inst_hits 32323173 # ITB inst hits -system.cpu0.itb.inst_misses 3455 # ITB inst misses +system.cpu0.dtb.hits 14585063 # DTB hits +system.cpu0.dtb.misses 8193 # DTB misses +system.cpu0.dtb.accesses 14593256 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.itb.inst_hits 32307309 # ITB inst hits +system.cpu0.itb.inst_misses 3464 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 279 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 556 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 674 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2571 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 681 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 29 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 2638 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 32326628 # ITB inst accesses -system.cpu0.itb.hits 32323173 # DTB hits -system.cpu0.itb.misses 3455 # DTB misses -system.cpu0.itb.accesses 32326628 # DTB accesses -system.cpu0.numCycles 113706934 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 32310773 # ITB inst accesses +system.cpu0.itb.hits 32307309 # DTB hits +system.cpu0.itb.misses 3464 # DTB misses +system.cpu0.itb.accesses 32310773 # DTB accesses +system.cpu0.numCycles 113705948 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 31845607 # Number of instructions committed -system.cpu0.committedOps 42007795 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 37151613 # Number of integer alu accesses +system.cpu0.committedInsts 31835702 # Number of instructions committed +system.cpu0.committedOps 42002663 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 37391372 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 4937 # Number of float alu accesses -system.cpu0.num_func_calls 1198507 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4245528 # number of instructions that are conditional controls -system.cpu0.num_int_insts 37151613 # number of integer instructions +system.cpu0.num_func_calls 1198329 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4242666 # number of instructions that are conditional controls +system.cpu0.num_int_insts 37391372 # number of integer instructions system.cpu0.num_fp_insts 4937 # number of float instructions -system.cpu0.num_int_register_reads 189362798 # number of times the integer registers were read -system.cpu0.num_int_register_writes 39261274 # number of times the integer registers were written +system.cpu0.num_int_register_reads 193815032 # number of times the integer registers were read +system.cpu0.num_int_register_writes 39491762 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3572 # number of times the floating registers were read system.cpu0.num_fp_register_writes 1366 # number of times the floating registers were written -system.cpu0.num_mem_refs 15249830 # number of memory refs -system.cpu0.num_load_insts 8359344 # Number of load instructions -system.cpu0.num_store_insts 6890486 # Number of store instructions -system.cpu0.num_idle_cycles 110900908.371908 # Number of idle cycles -system.cpu0.num_busy_cycles 2806025.628092 # Number of busy cycles -system.cpu0.not_idle_fraction 0.024678 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.975322 # Percentage of idle cycles +system.cpu0.num_mem_refs 15252645 # number of memory refs +system.cpu0.num_load_insts 8359351 # Number of load instructions +system.cpu0.num_store_insts 6893294 # Number of store instructions +system.cpu0.num_idle_cycles 111019314.623883 # Number of idle cycles +system.cpu0.num_busy_cycles 2686633.376117 # Number of busy cycles +system.cpu0.not_idle_fraction 0.023628 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.976372 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 82892 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 891661 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.603832 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 43642559 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 892173 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 48.917148 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 8180434250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 493.710568 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 7.685506 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 10.207759 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.964278 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.015011 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.019937 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 891892 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.603893 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 43639057 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 892404 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 48.900562 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 8180676250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 495.451765 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 7.618297 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 8.533831 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.967679 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.014879 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.016668 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999226 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 138 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 158 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 129 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 220 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 160 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 45450915 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 45450915 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 31849634 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 8050768 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 3742157 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 43642559 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 31849634 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 8050768 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 3742157 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 43642559 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 31849634 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 8050768 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 3742157 # number of overall hits -system.cpu0.icache.overall_hits::total 43642559 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 476194 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 131290 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 308690 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 916174 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 476194 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 131290 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 308690 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 916174 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 476194 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 131290 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 308690 # number of overall misses -system.cpu0.icache.overall_misses::total 916174 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1773545250 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4166299335 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5939844585 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 1773545250 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 4166299335 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5939844585 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 1773545250 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 4166299335 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5939844585 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 32325828 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 8182058 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 4050847 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 44558733 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 32325828 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 8182058 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 4050847 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 44558733 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 32325828 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 8182058 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 4050847 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 44558733 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014731 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016046 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.076204 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.020561 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014731 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016046 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.076204 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.020561 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014731 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016046 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.076204 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.020561 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13508.608805 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13496.709757 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 6483.314943 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13508.608805 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13496.709757 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 6483.314943 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13508.608805 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13496.709757 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 6483.314943 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 4376 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 45447878 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 45447878 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 31833706 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 8062582 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 3742769 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 43639057 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 31833706 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 8062582 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 3742769 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 43639057 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 31833706 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 8062582 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 3742769 # number of overall hits +system.cpu0.icache.overall_hits::total 43639057 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 476257 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 129542 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu2.inst 310613 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 916412 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 476257 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 129542 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu2.inst 310613 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 916412 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 476257 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 129542 # number of overall misses +system.cpu0.icache.overall_misses::cpu2.inst 310613 # number of overall misses +system.cpu0.icache.overall_misses::total 916412 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1750680500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4190164618 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5940845118 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 1750680500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu2.inst 4190164618 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5940845118 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 1750680500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu2.inst 4190164618 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5940845118 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 32309963 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 8192124 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu2.inst 4053382 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 44555469 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 32309963 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 8192124 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 4053382 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 44555469 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 32309963 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 8192124 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 4053382 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 44555469 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014740 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015813 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.076631 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.020568 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014740 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015813 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.076631 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.020568 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014740 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015813 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.076631 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.020568 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13514.385296 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13489.984701 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 6482.722965 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13514.385296 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13489.984701 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 6482.722965 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13514.385296 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13489.984701 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 6482.722965 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 4056 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 225 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 197 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 19.448889 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 20.588832 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 23991 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 23991 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu2.inst 23991 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 23991 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu2.inst 23991 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 23991 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 131290 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 284699 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 415989 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 131290 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 284699 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 415989 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 131290 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 284699 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 415989 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1510573750 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3389684570 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4900258320 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1510573750 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3389684570 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4900258320 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1510573750 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3389684570 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4900258320 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016046 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.070281 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009336 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016046 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.070281 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.009336 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016046 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.070281 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.009336 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11505.626857 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11906.204693 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11779.778600 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11505.626857 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11906.204693 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11779.778600 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11505.626857 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11906.204693 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11779.778600 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 24002 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 24002 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 24002 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 24002 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 24002 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 24002 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 129542 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 286611 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 416153 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 129542 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 286611 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 416153 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 129542 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 286611 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 416153 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1491204500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3408089041 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4899293541 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1491204500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3408089041 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4899293541 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1491204500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3408089041 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4899293541 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015813 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.070709 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009340 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015813 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.070709 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.009340 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015813 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.070709 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.009340 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11511.359250 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11890.991766 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11772.818028 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11511.359250 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11890.991766 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11772.818028 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11511.359250 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11890.991766 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11772.818028 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 629828 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.997119 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 23220836 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 630340 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 36.838589 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 21763000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 497.025505 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 8.136631 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 6.834983 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.970753 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.015892 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.013350 # Average percentage of cache occupancy +system.cpu0.dcache.tags.replacements 629794 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.997118 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 23221016 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 630306 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 36.840861 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 21768000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 497.062624 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 8.150626 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 6.783867 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.970825 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.015919 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.013250 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 197 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 297 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 301 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 98826136 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 98826136 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6861592 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 1819766 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 4641843 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13323201 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5960512 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 1314083 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 2134390 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 9408985 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 131699 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 33044 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 73537 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 238280 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 138171 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 34778 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 74440 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 247389 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 12822104 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 3133849 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 6776233 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 22732186 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 12822104 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 3133849 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 6776233 # number of overall hits -system.cpu0.dcache.overall_hits::total 22732186 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 176730 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 63698 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 271377 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 511805 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 167828 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 28621 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 610894 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 807343 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6472 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 1734 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 3738 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 11944 # number of LoadLockedReq misses +system.cpu0.dcache.tags.tag_accesses 98822314 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 98822314 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6860309 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 1818197 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 4643556 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 13322062 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5962720 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 1310571 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 2137098 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 9410389 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 131686 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 33079 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 73392 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 238157 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 138128 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 34832 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu2.data 74432 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 247392 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 12823029 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 3128768 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 6780654 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 22732451 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 12823029 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 3128768 # number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 6780654 # number of overall hits +system.cpu0.dcache.overall_hits::total 22732451 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 176845 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 63692 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu2.data 271624 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 512161 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 168028 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 28569 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu2.data 609317 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 805914 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6442 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 1753 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 3730 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 11925 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu2.data 2 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 344558 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 92319 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 882271 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1319148 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 344558 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 92319 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 882271 # number of overall misses -system.cpu0.dcache.overall_misses::total 1319148 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 907621250 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 3911808086 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 4819429336 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1013384989 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 23348414230 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 24361799219 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 22749500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 49835999 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 72585499 # number of LoadLockedReq miss cycles +system.cpu0.dcache.demand_misses::cpu0.data 344873 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 92261 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu2.data 880941 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1318075 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 344873 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 92261 # number of overall misses +system.cpu0.dcache.overall_misses::cpu2.data 880941 # number of overall misses +system.cpu0.dcache.overall_misses::total 1318075 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 907950750 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 3924341569 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 4832292319 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1018206487 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 23272443628 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 24290650115 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 23011750 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 49882999 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 72894749 # number of LoadLockedReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 26000 # number of StoreCondReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::total 26000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 1921006239 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 27260222316 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 29181228555 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 1921006239 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 27260222316 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 29181228555 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7038322 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 1883464 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 4913220 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 13835006 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 6128340 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 1342704 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 2745284 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 10216328 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 138171 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 34778 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 77275 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 250224 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 138171 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 34778 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 74442 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 247391 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13166662 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 3226168 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 7658504 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 24051334 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13166662 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 3226168 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 7658504 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 24051334 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.025110 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033820 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.055234 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.036993 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027386 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.021316 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.222525 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.079025 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.046841 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.049859 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.048373 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.047733 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_miss_latency::cpu1.data 1926157237 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu2.data 27196785197 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 29122942434 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 1926157237 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu2.data 27196785197 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 29122942434 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7037154 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 1881889 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu2.data 4915180 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 13834223 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 6130748 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 1339140 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu2.data 2746415 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 10216303 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 138128 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 34832 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 77122 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 250082 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 138128 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 34832 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 74434 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 247394 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 13167902 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 3221029 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu2.data 7661595 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 24050526 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13167902 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 3221029 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 7661595 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 24050526 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.025130 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033845 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.055262 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.037021 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027407 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.021334 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.221859 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.078885 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.046638 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.050327 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.048365 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.047684 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000027 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000008 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026169 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.028616 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.115201 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.054847 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026169 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.028616 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.115201 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.054847 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14248.818644 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14414.663313 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 9416.534297 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 35407.043395 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 38220.074563 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 30175.277694 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13119.665513 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13332.262975 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 6077.151624 # average LoadLockedReq miss latency +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026190 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.028643 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.114981 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.054804 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026190 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.028643 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.114981 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.054804 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14255.334265 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14447.698175 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 9435.104038 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 35640.256467 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 38194.312038 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 30140.499005 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13127.067884 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13373.458177 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 6112.767212 # average LoadLockedReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13000 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 20808.351899 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 30897.787999 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 22121.269604 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 20808.351899 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 30897.787999 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 22121.269604 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 7683 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 3605 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 878 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 49 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8.750569 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 73.571429 # average number of cycles each access was blocked +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 20877.263817 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 30872.425278 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 22095.057136 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 20877.263817 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 30872.425278 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 22095.057136 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 8107 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 3163 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 889 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 50 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9.119235 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 63.260000 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 597611 # number of writebacks -system.cpu0.dcache.writebacks::total 597611 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 139954 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 139954 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 557446 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 557446 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 413 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 413 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 697400 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 697400 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 697400 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 697400 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 63698 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 131423 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 195121 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 28621 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 53448 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 82069 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1734 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 3325 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 5059 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.writebacks::writebacks 597612 # number of writebacks +system.cpu0.dcache.writebacks::total 597612 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 140350 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 140350 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 556007 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 556007 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 401 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 401 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 696357 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 696357 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 696357 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 696357 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 63692 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 131274 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 194966 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 28569 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 53310 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 81879 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1753 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 3329 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 5082 # number of LoadLockedReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 2 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 92319 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 184871 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 277190 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 92319 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 184871 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 277190 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 780025750 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1703190327 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2483216077 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 953521011 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 1887250485 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2840771496 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 19281500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 38325501 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 57607001 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_misses::cpu1.data 92261 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 184584 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 276845 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 92261 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 184584 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 276845 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 780369250 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1701870584 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2482239834 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 958496513 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 1869248236 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2827744749 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 19505250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 38414501 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 57919751 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 22000 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1733546761 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3590440812 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 5323987573 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1733546761 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3590440812 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 5323987573 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27356277500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 28781091750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 56137369250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1442174490 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 13339751582 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 14781926072 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28798451990 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 42120843332 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 70919295322 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033820 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.026749 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014103 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021316 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019469 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008033 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.049859 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.043028 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020218 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1738865763 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3571118820 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 5309984583 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1738865763 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3571118820 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 5309984583 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27398396000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 28553530500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 55951926500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1442155991 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 13334829583 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 14776985574 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28840551991 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 41888360083 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 70728912074 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033845 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.026708 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014093 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021334 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019411 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008015 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050327 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.043165 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020321 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000027 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000008 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028616 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.024139 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.011525 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028616 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.024139 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.011525 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12245.686678 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12959.606210 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12726.544437 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33315.433109 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 35310.030029 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34614.428054 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11119.665513 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11526.466466 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11387.033208 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028643 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.024092 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.011511 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028643 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.024092 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.011511 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12252.233405 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12964.262413 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12731.654924 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33550.229725 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 35063.744813 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34535.653208 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11126.782658 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11539.351457 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11397.038764 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18777.789632 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19421.330614 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19206.997269 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18777.789632 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19421.330614 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19206.997269 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18847.245998 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19346.849239 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19180.352121 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18847.245998 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19346.849239 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19180.352121 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1628,390 +1645,474 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 2096419 # DTB read hits -system.cpu1.dtb.read_misses 2083 # DTB read misses -system.cpu1.dtb.write_hits 1418166 # DTB write hits -system.cpu1.dtb.write_misses 373 # DTB write misses -system.cpu1.dtb.flush_tlb 277 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 2095173 # DTB read hits +system.cpu1.dtb.read_misses 2089 # DTB read misses +system.cpu1.dtb.write_hits 1414657 # DTB write hits +system.cpu1.dtb.write_misses 374 # DTB write misses +system.cpu1.dtb.flush_tlb 554 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 234 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1734 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 220 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 13 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 1771 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 39 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 38 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 78 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 2098502 # DTB read accesses -system.cpu1.dtb.write_accesses 1418539 # DTB write accesses +system.cpu1.dtb.read_accesses 2097262 # DTB read accesses +system.cpu1.dtb.write_accesses 1415031 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 3514585 # DTB hits -system.cpu1.dtb.misses 2456 # DTB misses -system.cpu1.dtb.accesses 3517041 # DTB accesses -system.cpu1.itb.inst_hits 8182058 # ITB inst hits -system.cpu1.itb.inst_misses 1201 # ITB inst misses +system.cpu1.dtb.hits 3509830 # DTB hits +system.cpu1.dtb.misses 2463 # DTB misses +system.cpu1.dtb.accesses 3512293 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.itb.inst_hits 8192124 # ITB inst hits +system.cpu1.itb.inst_misses 1194 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 277 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 554 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 234 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 889 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 220 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 13 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 949 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8183259 # ITB inst accesses -system.cpu1.itb.hits 8182058 # DTB hits -system.cpu1.itb.misses 1201 # DTB misses -system.cpu1.itb.accesses 8183259 # DTB accesses -system.cpu1.numCycles 581387993 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 8193318 # ITB inst accesses +system.cpu1.itb.hits 8192124 # DTB hits +system.cpu1.itb.misses 1194 # DTB misses +system.cpu1.itb.accesses 8193318 # DTB accesses +system.cpu1.numCycles 581420474 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7973391 # Number of instructions committed -system.cpu1.committedOps 10123180 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 9055145 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 2019 # Number of float alu accesses -system.cpu1.num_func_calls 304839 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1113920 # number of instructions that are conditional controls -system.cpu1.num_int_insts 9055145 # number of integer instructions -system.cpu1.num_fp_insts 2019 # number of float instructions -system.cpu1.num_int_register_reads 52196104 # number of times the integer registers were read -system.cpu1.num_int_register_writes 9841677 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 1441 # number of times the floating registers were read +system.cpu1.committedInsts 7979382 # Number of instructions committed +system.cpu1.committedOps 10120569 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 9091581 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 1987 # Number of float alu accesses +system.cpu1.num_func_calls 304296 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1113753 # number of instructions that are conditional controls +system.cpu1.num_int_insts 9091581 # number of integer instructions +system.cpu1.num_fp_insts 1987 # number of float instructions +system.cpu1.num_int_register_reads 53006739 # number of times the integer registers were read +system.cpu1.num_int_register_writes 9888017 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 1409 # number of times the floating registers were read system.cpu1.num_fp_register_writes 580 # number of times the floating registers were written -system.cpu1.num_mem_refs 3682729 # number of memory refs -system.cpu1.num_load_insts 2189938 # Number of load instructions -system.cpu1.num_store_insts 1492791 # Number of store instructions -system.cpu1.num_idle_cycles 546287151.729317 # Number of idle cycles -system.cpu1.num_busy_cycles 35100841.270683 # Number of busy cycles -system.cpu1.not_idle_fraction 0.060374 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.939626 # Percentage of idle cycles +system.cpu1.num_mem_refs 3676771 # number of memory refs +system.cpu1.num_load_insts 2188618 # Number of load instructions +system.cpu1.num_store_insts 1488153 # Number of store instructions +system.cpu1.num_idle_cycles 545340562.414449 # Number of idle cycles +system.cpu1.num_busy_cycles 36079911.585551 # Number of busy cycles +system.cpu1.not_idle_fraction 0.062055 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.937945 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 4728615 # Number of BP lookups -system.cpu2.branchPred.condPredicted 3846891 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 223365 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 3153803 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 2531568 # Number of BTB hits +system.cpu2.branchPred.lookups 4789734 # Number of BP lookups +system.cpu2.branchPred.condPredicted 3907352 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 223904 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 3178605 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 2529099 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 80.270328 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 413323 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 21760 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 79.566319 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 413607 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 21727 # Number of incorrect RAS predictions. +system.cpu2.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu2.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu2.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu2.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu2.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu2.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu2.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu2.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu2.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu2.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu2.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu2.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu2.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 10972958 # DTB read hits -system.cpu2.dtb.read_misses 22884 # DTB read misses -system.cpu2.dtb.write_hits 3353841 # DTB write hits -system.cpu2.dtb.write_misses 6440 # DTB write misses -system.cpu2.dtb.flush_tlb 276 # Number of times complete TLB was flushed +system.cpu2.dtb.read_hits 10928591 # DTB read hits +system.cpu2.dtb.read_misses 22863 # DTB read misses +system.cpu2.dtb.write_hits 3355192 # DTB write hits +system.cpu2.dtb.write_misses 6501 # DTB write misses +system.cpu2.dtb.flush_tlb 552 # Number of times complete TLB was flushed system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.dtb.flush_tlb_mva_asid 531 # Number of times TLB was flushed by MVA & ASID +system.cpu2.dtb.flush_tlb_mva_asid 538 # Number of times TLB was flushed by MVA & ASID system.cpu2.dtb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 2329 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 684 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 147 # Number of TLB faults due to prefetch +system.cpu2.dtb.flush_entries 2326 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 747 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 160 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 471 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 10995842 # DTB read accesses -system.cpu2.dtb.write_accesses 3360281 # DTB write accesses +system.cpu2.dtb.perms_faults 464 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 10951454 # DTB read accesses +system.cpu2.dtb.write_accesses 3361693 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 14326799 # DTB hits -system.cpu2.dtb.misses 29324 # DTB misses -system.cpu2.dtb.accesses 14356123 # DTB accesses -system.cpu2.itb.inst_hits 4052293 # ITB inst hits -system.cpu2.itb.inst_misses 4591 # ITB inst misses +system.cpu2.dtb.hits 14283783 # DTB hits +system.cpu2.dtb.misses 29364 # DTB misses +system.cpu2.dtb.accesses 14313147 # DTB accesses +system.cpu2.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu2.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu2.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu2.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu2.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu2.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu2.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu2.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu2.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu2.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu2.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu2.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu2.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu2.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu2.itb.inst_hits 4054873 # ITB inst hits +system.cpu2.itb.inst_misses 4512 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses -system.cpu2.itb.flush_tlb 276 # Number of times complete TLB was flushed +system.cpu2.itb.flush_tlb 552 # Number of times complete TLB was flushed system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.itb.flush_tlb_mva_asid 531 # Number of times TLB was flushed by MVA & ASID +system.cpu2.itb.flush_tlb_mva_asid 538 # Number of times TLB was flushed by MVA & ASID system.cpu2.itb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 1671 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_entries 1691 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 1020 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 1038 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 4056884 # ITB inst accesses -system.cpu2.itb.hits 4052293 # DTB hits -system.cpu2.itb.misses 4591 # DTB misses -system.cpu2.itb.accesses 4056884 # DTB accesses -system.cpu2.numCycles 88364936 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 4059385 # ITB inst accesses +system.cpu2.itb.hits 4054873 # DTB hits +system.cpu2.itb.misses 4512 # DTB misses +system.cpu2.itb.accesses 4059385 # DTB accesses +system.cpu2.numCycles 88337048 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9352566 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 32517206 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 4728615 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 2944891 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 6861610 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 1759869 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 50868 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.BlockedCycles 18844594 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 335 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 866 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 32744 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 721068 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 448 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 4050852 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 289827 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 1989 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 37074469 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.054164 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.440934 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9388767 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 32522302 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 4789734 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 2942706 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 6862489 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 1760464 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 49990 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.BlockedCycles 19168441 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 508 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 916 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 33389 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 724944 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 411 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 4053387 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 290500 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 1970 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 37439208 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.044253 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.431681 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 30218075 81.51% 81.51% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 386681 1.04% 82.55% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 516163 1.39% 83.94% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 819367 2.21% 86.15% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 628808 1.70% 87.85% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 344228 0.93% 88.78% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1045241 2.82% 91.60% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 229591 0.62% 92.21% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 2886315 7.79% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 30581596 81.68% 81.68% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 385766 1.03% 82.71% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 516570 1.38% 84.09% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 819401 2.19% 86.28% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 630355 1.68% 87.97% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 341667 0.91% 88.88% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1045652 2.79% 91.67% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 230362 0.62% 92.29% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 2887839 7.71% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 37074469 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.053512 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.367988 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 9932859 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 19459354 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 6244628 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 279238 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1157490 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 609849 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 53110 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 36985250 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 179754 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 1157490 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 10483306 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 6921288 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 11074515 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 5953553 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 1483425 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 34895792 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 2444 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 326661 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 892066 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.FullRegisterEvents 111 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 37386016 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 159700078 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 148525933 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 3408 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 26513636 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 10872379 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 232480 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 208815 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3253838 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6628841 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3905916 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 536820 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 771052 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 32212739 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 505163 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 34823222 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 55040 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 7182108 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 19097970 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 148083 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 37074469 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 0.939278 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.598547 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 37439208 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.054221 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.368162 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 10012366 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 19744012 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 6199418 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 325352 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1157163 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 610165 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 53442 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 36995280 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 180745 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 1157163 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 10561732 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 6812365 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 11427981 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 5960297 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 1518769 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 34903210 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 107 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 326244 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 883069 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.FullRegisterEvents 119 # Number of times there has been no free registers +system.cpu2.rename.RenamedOperands 37436972 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 161085942 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 148506742 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 3418 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 26572380 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 10864591 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 285670 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 261929 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3326002 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6631520 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3908381 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 522508 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 782143 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 32221978 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 504989 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 34786596 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 55958 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 7182504 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 19112764 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 148353 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 37439208 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 0.929149 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.590514 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 24463826 65.99% 65.99% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 3833492 10.34% 76.33% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 2324654 6.27% 82.60% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 2008652 5.42% 88.01% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 2796278 7.54% 95.56% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 971248 2.62% 98.18% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 496274 1.34% 99.51% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 144890 0.39% 99.91% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 35155 0.09% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 24741126 66.08% 66.08% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 3984374 10.64% 76.73% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 2311240 6.17% 82.90% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 1973818 5.27% 88.17% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 2779235 7.42% 95.59% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 969976 2.59% 98.19% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 499460 1.33% 99.52% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 145124 0.39% 99.91% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 34855 0.09% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 37074469 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 37439208 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 19545 1.28% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 1 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 1401661 91.55% 92.82% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 109897 7.18% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 19410 1.27% 1.27% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 1 0.00% 1.27% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.27% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.27% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.27% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.27% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.27% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.27% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.27% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.27% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.27% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.27% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.27% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.27% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.27% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.27% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.27% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.27% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.27% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.27% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.27% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.27% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.27% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.27% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.27% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.27% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.27% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.27% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.27% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 1392857 91.45% 92.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 110885 7.28% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 61115 0.18% 0.18% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 19755783 56.73% 56.91% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 28013 0.08% 56.99% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 56.99% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 56.99% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 56.99% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 56.99% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 56.99% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 56.99% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 56.99% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 56.99% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 56.99% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 56.99% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 56.99% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 56.99% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 6 0.00% 56.99% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 56.99% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 56.99% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 56.99% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 6 0.00% 56.99% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 56.99% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.99% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.99% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.99% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.99% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.99% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 388 0.00% 56.99% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 56.99% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 56.99% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.99% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 11456328 32.90% 89.89% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3521577 10.11% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 8329 0.02% 0.02% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 19813633 56.96% 56.98% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 28024 0.08% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 5 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 5 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 386 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 11412307 32.81% 89.87% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3523902 10.13% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 34823222 # Type of FU issued -system.cpu2.iq.rate 0.394084 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 1531104 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.043968 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 108328678 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 39905127 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 28084625 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 7572 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 4019 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 3368 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 36289170 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 4041 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 206363 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 34786596 # Type of FU issued +system.cpu2.iq.rate 0.393794 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 1523153 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.043786 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 108613127 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 39914727 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 28091280 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 7607 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 3993 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 3398 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 36297355 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 4065 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 206023 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1533130 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 2013 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 9465 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 562980 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1534437 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 2089 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 9566 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 563640 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 5327720 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 344503 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 5283023 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 345372 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1157490 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 5247900 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 88519 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 32800222 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 60619 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6628841 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3905916 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 362644 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 29757 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 2395 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 9465 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 107959 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 89408 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 197367 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 33908136 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 11185478 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 915086 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 1157163 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 5185391 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 88081 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 32809694 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 61016 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6631520 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3908381 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 362677 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 29698 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 2464 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 9566 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 107529 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 89869 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 197398 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 33871170 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 11141481 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 915426 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 82320 # number of nop insts executed -system.cpu2.iew.exec_refs 14673656 # number of memory reference insts executed -system.cpu2.iew.exec_branches 3709694 # Number of branches executed -system.cpu2.iew.exec_stores 3488178 # Number of stores executed -system.cpu2.iew.exec_rate 0.383728 # Inst execution rate -system.cpu2.iew.wb_sent 33508440 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 28087993 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 16121354 # num instructions producing a value -system.cpu2.iew.wb_consumers 29172590 # num instructions consuming a value +system.cpu2.iew.exec_nop 82727 # number of nop insts executed +system.cpu2.iew.exec_refs 14631897 # number of memory reference insts executed +system.cpu2.iew.exec_branches 3767155 # Number of branches executed +system.cpu2.iew.exec_stores 3490416 # Number of stores executed +system.cpu2.iew.exec_rate 0.383431 # Inst execution rate +system.cpu2.iew.wb_sent 33470061 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 28094678 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 16123172 # num instructions producing a value +system.cpu2.iew.wb_consumers 29138246 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.317864 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.552620 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.318040 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.553334 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 7137877 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 357080 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 171034 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 35916785 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 0.707415 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.751354 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 7139947 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 356636 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 171258 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 36281839 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 0.700541 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.737980 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 27161260 75.62% 75.62% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4227698 11.77% 87.39% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1252285 3.49% 90.88% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 635084 1.77% 92.65% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 561790 1.56% 94.21% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 319405 0.89% 95.10% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 418201 1.16% 96.27% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 311340 0.87% 97.13% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1029722 2.87% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 27358624 75.41% 75.41% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4439139 12.24% 87.64% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1255970 3.46% 91.10% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 641270 1.77% 92.87% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 512644 1.41% 94.28% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 317320 0.87% 95.16% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 419851 1.16% 96.31% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 310411 0.86% 97.17% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1026610 2.83% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 35916785 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 20564616 # Number of instructions committed -system.cpu2.commit.committedOps 25408067 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 36281839 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 20568992 # Number of instructions committed +system.cpu2.commit.committedOps 25416928 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8438647 # Number of memory references committed -system.cpu2.commit.loads 5095711 # Number of loads committed -system.cpu2.commit.membars 94423 # Number of memory barriers committed -system.cpu2.commit.branches 3185422 # Number of branches committed -system.cpu2.commit.fp_insts 3299 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 22610745 # Number of committed integer instructions. -system.cpu2.commit.function_calls 295586 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 1029722 # number cycles where commit BW limit reached +system.cpu2.commit.refs 8441824 # Number of memory references committed +system.cpu2.commit.loads 5097083 # Number of loads committed +system.cpu2.commit.membars 94345 # Number of memory barriers committed +system.cpu2.commit.branches 3244670 # Number of branches committed +system.cpu2.commit.fp_insts 3331 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 22669662 # Number of committed integer instructions. +system.cpu2.commit.function_calls 295973 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 1026610 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 66910934 # The number of ROB reads -system.cpu2.rob.rob_writes 66293514 # The number of ROB writes -system.cpu2.timesIdled 359960 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 51290467 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 3553935024 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 20509130 # Number of Instructions Simulated -system.cpu2.committedOps 25352581 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 20509130 # Number of Instructions Simulated -system.cpu2.cpi 4.308566 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 4.308566 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.232096 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.232096 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 157121826 # number of integer regfile reads -system.cpu2.int_regfile_writes 29906145 # number of integer regfile writes -system.cpu2.fp_regfile_reads 22616 # number of floating regfile reads -system.cpu2.fp_regfile_writes 20826 # number of floating regfile writes -system.cpu2.misc_regfile_reads 9261107 # number of misc regfile reads -system.cpu2.misc_regfile_writes 242774 # number of misc regfile writes +system.cpu2.rob.rob_reads 67290844 # The number of ROB reads +system.cpu2.rob.rob_writes 66314967 # The number of ROB writes +system.cpu2.timesIdled 359753 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 50897840 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 3553970695 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 20513640 # Number of Instructions Simulated +system.cpu2.committedOps 25361576 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 20513640 # Number of Instructions Simulated +system.cpu2.cpi 4.306259 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 4.306259 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.232220 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.232220 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 157179181 # number of integer regfile reads +system.cpu2.int_regfile_writes 29907517 # number of integer regfile writes +system.cpu2.fp_regfile_reads 46919 # number of floating regfile reads +system.cpu2.fp_regfile_writes 45194 # number of floating regfile writes +system.cpu2.misc_regfile_reads 66774204 # number of misc regfile reads +system.cpu2.misc_regfile_writes 297147 # number of misc regfile writes system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. @@ -2028,10 +2129,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1347589582250 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1347589582250 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1347589582250 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1347589582250 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1347815916500 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1347815916500 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1347815916500 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1347815916500 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini index 3aa171235..789fa7ff8 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini @@ -14,6 +14,7 @@ children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l atags_addr=256 boot_loader=/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain dtb_filename= @@ -22,9 +23,16 @@ enable_context_switch_stats_dump=false eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 +have_generic_timer=false +have_large_asid_64=false +have_lpae=false +have_security=false +have_virtualization=false +highest_el_is_64=false init_param=0 kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 +load_offset=0 machine_type=RealView_PBX mem_mode=timing mem_ranges=0:134217727 @@ -33,7 +41,9 @@ multi_proc=true num_work_ids=16 panic_on_oops=true panic_on_panic=true +phys_addr_range_64=40 readfile=tests/halt.sh +reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -86,7 +96,7 @@ voltage_domain=system.voltage_domain [system.cpu0] type=DerivO3CPU -children=branchPred dcache dtb fuPool icache interrupts isa itb tracer +children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb tracer LFSTSize=1024 LQEntries=32 LSQCheckLoads=true @@ -112,6 +122,7 @@ dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu0.dstage2_mmu dtb=system.cpu0.dtb eventq_index=0 fetchBufferSize=64 @@ -130,6 +141,7 @@ interrupts=system.cpu0.interrupts isa=system.cpu0.isa issueToExecuteDelay=1 issueWidth=8 +istage2_mmu=system.cpu0.istage2_mmu itb=system.cpu0.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -224,10 +236,35 @@ hit_latency=2 sequential_access=false size=32768 +[system.cpu0.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb +tlb=system.cpu0.dtb + +[system.cpu0.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu0.dstage2_mmu.stage2_tlb.walker + +[system.cpu0.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[5] + [system.cpu0.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu0.dtb.walker @@ -235,6 +272,7 @@ walker=system.cpu0.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[3] @@ -589,24 +627,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu0.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb +tlb=system.cpu0.itb + +[system.cpu0.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu0.istage2_mmu.stage2_tlb.walker + +[system.cpu0.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[4] [system.cpu0.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu0.itb.walker @@ -614,6 +688,7 @@ walker=system.cpu0.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[2] @@ -624,7 +699,7 @@ eventq_index=0 [system.cpu1] type=DerivO3CPU -children=branchPred dtb fuPool isa itb tracer +children=branchPred dstage2_mmu dtb fuPool isa istage2_mmu itb tracer LFSTSize=1024 LQEntries=32 LSQCheckLoads=true @@ -650,6 +725,7 @@ dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu1.dstage2_mmu dtb=system.cpu1.dtb eventq_index=0 fetchBufferSize=64 @@ -668,6 +744,7 @@ interrupts=Null isa=system.cpu1.isa issueToExecuteDelay=1 issueWidth=8 +istage2_mmu=system.cpu1.istage2_mmu itb=system.cpu1.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -725,10 +802,34 @@ localPredictorSize=2048 numThreads=1 predType=tournament +[system.cpu1.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb +tlb=system.cpu1.dtb + +[system.cpu1.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu1.dstage2_mmu.stage2_tlb.walker + +[system.cpu1.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system + [system.cpu1.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu1.dtb.walker @@ -736,6 +837,7 @@ walker=system.cpu1.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system @@ -1050,24 +1152,59 @@ opLat=3 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu1.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb +tlb=system.cpu1.itb + +[system.cpu1.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu1.istage2_mmu.stage2_tlb.walker + +[system.cpu1.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system [system.cpu1.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu1.itb.walker @@ -1075,6 +1212,7 @@ walker=system.cpu1.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system @@ -1713,7 +1851,7 @@ system=system use_default_range=false width=8 master=system.l2c.cpu_side -slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port +slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port [system.vncserver] type=VncServer diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr index 1059ef88b..5150881aa 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr @@ -11,7 +11,23 @@ warn: instruction 'mcr dccimvac' unimplemented warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented warn: LCD dual screen mode not supported -warn: instruction 'mcr icialluis' unimplemented -warn: instruction 'mcr bpiallis' unimplemented +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout index 74e20af0b..f047a9e04 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout @@ -1,8 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 23 2014 00:28:14 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 19:10:32 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 Global frequency set at 1000000000000 ticks per second + 0: system.cpu0.isa: ISA system set to: 0x6aaf400 0x6aaf400 + 0: system.cpu1.isa: ISA system set to: 0x6aaf400 0x6aaf400 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index 5e74bf3fb..7a8eccd80 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -1,154 +1,158 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.549345 # Number of seconds simulated -sim_ticks 2549345168000 # Number of ticks simulated -final_tick 2549345168000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.550461 # Number of seconds simulated +sim_ticks 2550460850000 # Number of ticks simulated +final_tick 2550460850000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 76720 # Simulator instruction rate (inst/s) -host_op_rate 98719 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3242754050 # Simulator tick rate (ticks/s) -host_mem_usage 404480 # Number of bytes of host memory used -host_seconds 786.17 # Real time elapsed on the host -sim_insts 60314699 # Number of instructions simulated -sim_ops 77609228 # Number of ops (including micro ops) simulated +host_inst_rate 71467 # Simulator instruction rate (inst/s) +host_op_rate 91959 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3022122690 # Simulator tick rate (ticks/s) +host_mem_usage 427404 # Number of bytes of host memory used +host_seconds 843.93 # Real time elapsed on the host +sim_insts 60313440 # Number of instructions simulated +sim_ops 77607116 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 1856 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 498624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4680272 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 1024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 301248 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4410392 # Number of bytes read from this memory -system.physmem.bytes_read::total 131004072 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 498624 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 301248 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 799872 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3784640 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1521380 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1494720 # Number of bytes written to this memory -system.physmem.bytes_written::total 6800740 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 504512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5067800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 293824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4027288 # Number of bytes read from this memory +system.physmem.bytes_read::total 131006896 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 504512 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 293824 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 798336 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3786560 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1521444 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1494656 # Number of bytes written to this memory +system.physmem.bytes_written::total 6802660 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 29 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 7791 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 73163 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 16 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 4707 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 68918 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15293442 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59135 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 380345 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 373680 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813160 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47506524 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu0.inst 7883 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 79220 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 14 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 4591 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 62932 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15293488 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59165 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 380361 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 373664 # Number of write requests responded to by this memory +system.physmem.num_writes::total 813190 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47485743 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 728 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 195589 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1835872 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 402 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 118167 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1730010 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51387342 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 195589 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 118167 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 313756 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1484554 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 596773 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 586315 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2667642 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1484554 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47506524 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 197812 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1987013 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 351 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 25 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 115204 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1579043 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51365970 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 197812 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 115204 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 313016 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1484657 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 596537 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 586034 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2667228 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1484657 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47485743 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 728 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 195589 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2432645 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 402 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 118167 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2316325 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54054984 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15293442 # Number of read requests accepted -system.physmem.writeReqs 813160 # Number of write requests accepted -system.physmem.readBursts 15293442 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 813160 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 978220224 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 560064 # Total number of bytes read from write queue -system.physmem.bytesWritten 6909248 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 131004072 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6800740 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 8751 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 705188 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4685 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 955866 # Per bank write bursts -system.physmem.perBankRdBursts::1 955512 # Per bank write bursts -system.physmem.perBankRdBursts::2 954595 # Per bank write bursts -system.physmem.perBankRdBursts::3 954812 # Per bank write bursts -system.physmem.perBankRdBursts::4 955762 # Per bank write bursts -system.physmem.perBankRdBursts::5 955910 # Per bank write bursts -system.physmem.perBankRdBursts::6 954892 # Per bank write bursts -system.physmem.perBankRdBursts::7 954654 # Per bank write bursts -system.physmem.perBankRdBursts::8 956247 # Per bank write bursts -system.physmem.perBankRdBursts::9 955899 # Per bank write bursts -system.physmem.perBankRdBursts::10 954311 # Per bank write bursts -system.physmem.perBankRdBursts::11 954068 # Per bank write bursts -system.physmem.perBankRdBursts::12 956211 # Per bank write bursts -system.physmem.perBankRdBursts::13 955980 # Per bank write bursts -system.physmem.perBankRdBursts::14 955097 # Per bank write bursts -system.physmem.perBankRdBursts::15 954875 # Per bank write bursts -system.physmem.perBankWrBursts::0 6687 # Per bank write bursts -system.physmem.perBankWrBursts::1 6461 # Per bank write bursts -system.physmem.perBankWrBursts::2 6610 # Per bank write bursts -system.physmem.perBankWrBursts::3 6631 # Per bank write bursts -system.physmem.perBankWrBursts::4 6571 # Per bank write bursts -system.physmem.perBankWrBursts::5 6830 # Per bank write bursts -system.physmem.perBankWrBursts::6 6820 # Per bank write bursts -system.physmem.perBankWrBursts::7 6764 # Per bank write bursts -system.physmem.perBankWrBursts::8 7113 # Per bank write bursts -system.physmem.perBankWrBursts::9 6879 # Per bank write bursts -system.physmem.perBankWrBursts::10 6545 # Per bank write bursts -system.physmem.perBankWrBursts::11 6197 # Per bank write bursts -system.physmem.perBankWrBursts::12 7141 # Per bank write bursts -system.physmem.perBankWrBursts::13 6760 # Per bank write bursts -system.physmem.perBankWrBursts::14 7037 # Per bank write bursts -system.physmem.perBankWrBursts::15 6911 # Per bank write bursts +system.physmem.bw_total::cpu0.inst 197812 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2583550 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 351 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 115204 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2165077 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54033198 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15293488 # Number of read requests accepted +system.physmem.writeReqs 813190 # Number of write requests accepted +system.physmem.readBursts 15293488 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 813190 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 978237376 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 545856 # Total number of bytes read from write queue +system.physmem.bytesWritten 6910336 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 131006896 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6802660 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 8529 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 705216 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4690 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 955874 # Per bank write bursts +system.physmem.perBankRdBursts::1 955460 # Per bank write bursts +system.physmem.perBankRdBursts::2 954683 # Per bank write bursts +system.physmem.perBankRdBursts::3 954757 # Per bank write bursts +system.physmem.perBankRdBursts::4 955767 # Per bank write bursts +system.physmem.perBankRdBursts::5 955952 # Per bank write bursts +system.physmem.perBankRdBursts::6 954810 # Per bank write bursts +system.physmem.perBankRdBursts::7 954709 # Per bank write bursts +system.physmem.perBankRdBursts::8 956270 # Per bank write bursts +system.physmem.perBankRdBursts::9 955934 # Per bank write bursts +system.physmem.perBankRdBursts::10 954560 # Per bank write bursts +system.physmem.perBankRdBursts::11 953973 # Per bank write bursts +system.physmem.perBankRdBursts::12 956221 # Per bank write bursts +system.physmem.perBankRdBursts::13 955978 # Per bank write bursts +system.physmem.perBankRdBursts::14 955151 # Per bank write bursts +system.physmem.perBankRdBursts::15 954860 # Per bank write bursts +system.physmem.perBankWrBursts::0 6693 # Per bank write bursts +system.physmem.perBankWrBursts::1 6460 # Per bank write bursts +system.physmem.perBankWrBursts::2 6602 # Per bank write bursts +system.physmem.perBankWrBursts::3 6635 # Per bank write bursts +system.physmem.perBankWrBursts::4 6566 # Per bank write bursts +system.physmem.perBankWrBursts::5 6824 # Per bank write bursts +system.physmem.perBankWrBursts::6 6825 # Per bank write bursts +system.physmem.perBankWrBursts::7 6757 # Per bank write bursts +system.physmem.perBankWrBursts::8 7131 # Per bank write bursts +system.physmem.perBankWrBursts::9 6880 # Per bank write bursts +system.physmem.perBankWrBursts::10 6546 # Per bank write bursts +system.physmem.perBankWrBursts::11 6195 # Per bank write bursts +system.physmem.perBankWrBursts::12 7145 # Per bank write bursts +system.physmem.perBankWrBursts::13 6763 # Per bank write bursts +system.physmem.perBankWrBursts::14 7046 # Per bank write bursts +system.physmem.perBankWrBursts::15 6906 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2549344036000 # Total gap between requests +system.physmem.totGap 2550459728500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 42 # Read request sizes (log2) +system.physmem.readPktSize::2 44 # Read request sizes (log2) system.physmem.readPktSize::3 15138816 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 154584 # Read request sizes (log2) +system.physmem.readPktSize::6 154628 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 754025 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 59135 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1194358 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1134175 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1088302 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3688965 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2641659 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2636525 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2648641 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 52098 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 58013 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 20372 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 20352 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 20320 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 20270 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 20227 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 20195 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 20165 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 41 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59165 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1189211 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1129031 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1083368 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3689725 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2647408 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2642045 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2653706 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 51340 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 57140 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 20388 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 20349 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 20322 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 20287 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 20234 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 20199 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 20166 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 23 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -161,31 +165,31 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4920 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5608 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 5013 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5417 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4913 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4910 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4927 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4839 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4807 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4790 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4777 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4754 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4743 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4728 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4706 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4719 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4733 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4669 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5063 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4924 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5663 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4987 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5378 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4936 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4909 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4915 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4840 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4820 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4777 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4773 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4768 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4749 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4738 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4711 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4718 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4690 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4693 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 129 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see @@ -193,381 +197,396 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 86636 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 11370.889515 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 1019.409545 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 16839.040635 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-71 23447 27.06% 27.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-135 14187 16.38% 43.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-199 2756 3.18% 46.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-263 2051 2.37% 48.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-327 1336 1.54% 50.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-391 1207 1.39% 51.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-455 834 0.96% 52.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-519 1069 1.23% 54.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-583 542 0.63% 54.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-647 595 0.69% 55.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-711 544 0.63% 56.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-775 497 0.57% 56.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-839 259 0.30% 56.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-903 256 0.30% 57.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-967 151 0.17% 57.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1031 457 0.53% 57.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1095 109 0.13% 58.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1159 146 0.17% 58.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1223 72 0.08% 58.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1287 245 0.28% 58.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1351 63 0.07% 58.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1415 509 0.59% 59.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1479 29 0.03% 59.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1543 238 0.27% 59.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1607 21 0.02% 59.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1671 111 0.13% 59.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1735 24 0.03% 59.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1799 197 0.23% 59.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1863 24 0.03% 59.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1927 41 0.05% 60.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1991 13 0.02% 60.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2055 375 0.43% 60.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2119 14 0.02% 60.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2183 36 0.04% 60.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2247 11 0.01% 60.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2311 279 0.32% 60.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2375 8 0.01% 60.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2439 26 0.03% 60.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2503 6 0.01% 60.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2567 24 0.03% 60.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2631 10 0.01% 60.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2695 21 0.02% 60.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2759 7 0.01% 61.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2823 158 0.18% 61.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2887 8 0.01% 61.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2951 20 0.02% 61.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3015 12 0.01% 61.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3079 221 0.26% 61.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3143 10 0.01% 61.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3207 16 0.02% 61.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3271 7 0.01% 61.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3335 86 0.10% 61.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3399 7 0.01% 61.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3463 12 0.01% 61.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3527 13 0.02% 61.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3591 93 0.11% 61.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3655 7 0.01% 61.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3719 17 0.02% 61.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3783 7 0.01% 61.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3847 145 0.17% 61.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3911 10 0.01% 61.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3975 20 0.02% 62.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4039 16 0.02% 62.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4103 418 0.48% 62.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4167 6 0.01% 62.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4231 13 0.02% 62.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4295 5 0.01% 62.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4359 16 0.02% 62.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4423 22 0.03% 62.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4487 16 0.02% 62.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4551 10 0.01% 62.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4615 214 0.25% 62.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4679 6 0.01% 62.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4743 10 0.01% 62.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4807 2 0.00% 62.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4871 11 0.01% 62.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4935 11 0.01% 62.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4999 9 0.01% 62.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5063 5 0.01% 62.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5127 326 0.38% 63.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5191 6 0.01% 63.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5255 11 0.01% 63.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5319 8 0.01% 63.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5383 81 0.09% 63.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5447 11 0.01% 63.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5511 14 0.02% 63.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5575 6 0.01% 63.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5639 112 0.13% 63.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5703 3 0.00% 63.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5767 16 0.02% 63.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5831 7 0.01% 63.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5895 131 0.15% 63.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5959 3 0.00% 63.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6023 12 0.01% 63.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6087 12 0.01% 63.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6151 585 0.68% 64.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6215 5 0.01% 64.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6279 9 0.01% 64.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6343 3 0.00% 64.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6407 63 0.07% 64.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6471 2 0.00% 64.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6535 10 0.01% 64.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6599 4 0.00% 64.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6663 9 0.01% 64.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6727 6 0.01% 64.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6791 18 0.02% 64.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6855 6 0.01% 64.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6919 188 0.22% 64.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6983 4 0.00% 64.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7047 8 0.01% 64.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7111 12 0.01% 64.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7175 264 0.30% 65.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7239 3 0.00% 65.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7303 8 0.01% 65.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7367 14 0.02% 65.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7431 15 0.02% 65.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7495 4 0.00% 65.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7559 8 0.01% 65.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7623 3 0.00% 65.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7687 139 0.16% 65.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7751 1 0.00% 65.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7815 8 0.01% 65.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7879 5 0.01% 65.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7943 78 0.09% 65.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8071 7 0.01% 65.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8199 491 0.57% 66.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8256-8263 1 0.00% 66.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8320-8327 1 0.00% 66.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8455 73 0.08% 66.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8711 137 0.16% 66.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8832-8839 1 0.00% 66.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8967 1 0.00% 66.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9223 257 0.30% 66.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9479 183 0.21% 66.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9735 1 0.00% 66.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9991 57 0.07% 66.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10247 569 0.66% 67.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10432-10439 1 0.00% 67.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10503 64 0.07% 67.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10759 98 0.11% 67.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11015 68 0.08% 67.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11271 311 0.36% 68.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11527 1 0.00% 68.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11648-11655 1 0.00% 68.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11783 192 0.22% 68.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11904-11911 1 0.00% 68.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12224-12231 1 0.00% 68.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12295 384 0.44% 68.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12352-12359 1 0.00% 68.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12551 130 0.15% 69.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12807 71 0.08% 69.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12928-12935 1 0.00% 69.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13063 66 0.08% 69.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13319 202 0.23% 69.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13575 137 0.16% 69.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13831 4 0.00% 69.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14087 238 0.27% 69.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14272-14279 1 0.00% 69.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14343 326 0.38% 70.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14528-14535 1 0.00% 70.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14599 131 0.15% 70.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14855 64 0.07% 70.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 86806 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 11348.833952 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 1015.155739 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 16835.722240 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 23589 27.17% 27.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 14167 16.32% 43.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 2667 3.07% 46.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 2091 2.41% 48.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 1355 1.56% 50.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 1138 1.31% 51.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 864 1.00% 52.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 1120 1.29% 54.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 549 0.63% 54.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 610 0.70% 55.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 512 0.59% 56.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-775 456 0.53% 56.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-839 243 0.28% 56.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-903 296 0.34% 57.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 156 0.18% 57.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 592 0.68% 58.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 118 0.14% 58.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1159 142 0.16% 58.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1223 67 0.08% 58.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1287 249 0.29% 58.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1351 52 0.06% 58.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1415 529 0.61% 59.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1479 29 0.03% 59.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1543 292 0.34% 59.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1607 23 0.03% 59.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1671 99 0.11% 59.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1735 19 0.02% 59.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1799 187 0.22% 60.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1863 23 0.03% 60.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1927 47 0.05% 60.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1991 18 0.02% 60.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2055 308 0.35% 60.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2119 8 0.01% 60.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2183 37 0.04% 60.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2247 15 0.02% 60.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2311 167 0.19% 60.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2375 7 0.01% 60.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2439 23 0.03% 60.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2503 12 0.01% 60.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2567 29 0.03% 60.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2631 15 0.02% 60.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2695 19 0.02% 60.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2759 10 0.01% 61.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2823 208 0.24% 61.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2887 13 0.01% 61.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2951 29 0.03% 61.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3015 6 0.01% 61.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3079 407 0.47% 61.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3143 12 0.01% 61.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3207 20 0.02% 61.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3271 9 0.01% 61.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3335 80 0.09% 61.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3399 11 0.01% 61.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3463 13 0.01% 61.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3527 7 0.01% 61.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3591 84 0.10% 62.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3655 10 0.01% 62.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3719 19 0.02% 62.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3783 9 0.01% 62.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3847 152 0.18% 62.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3911 7 0.01% 62.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3975 15 0.02% 62.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4039 9 0.01% 62.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4103 349 0.40% 62.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4167 12 0.01% 62.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4231 10 0.01% 62.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4295 13 0.01% 62.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4359 21 0.02% 62.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4423 11 0.01% 62.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4487 12 0.01% 62.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4551 11 0.01% 62.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4615 184 0.21% 63.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4679 10 0.01% 63.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4743 8 0.01% 63.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4807 12 0.01% 63.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4871 8 0.01% 63.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4935 5 0.01% 63.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4999 12 0.01% 63.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5063 6 0.01% 63.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5127 273 0.31% 63.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5191 7 0.01% 63.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5255 11 0.01% 63.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5319 14 0.02% 63.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5383 208 0.24% 63.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5447 11 0.01% 63.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5511 14 0.02% 63.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5575 7 0.01% 63.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5639 73 0.08% 63.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5703 5 0.01% 63.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5767 17 0.02% 63.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5831 9 0.01% 63.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5895 138 0.16% 63.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5959 3 0.00% 63.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6023 13 0.01% 64.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6087 5 0.01% 64.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6151 459 0.53% 64.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6215 4 0.00% 64.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6279 8 0.01% 64.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6343 6 0.01% 64.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6407 9 0.01% 64.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6471 3 0.00% 64.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6535 10 0.01% 64.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6599 6 0.01% 64.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6663 12 0.01% 64.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6727 10 0.01% 64.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6791 19 0.02% 64.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6855 4 0.00% 64.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6919 133 0.15% 64.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6983 6 0.01% 64.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7047 4 0.00% 64.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7111 4 0.00% 64.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7175 263 0.30% 65.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7239 1 0.00% 65.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7303 10 0.01% 65.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7367 11 0.01% 65.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7431 14 0.02% 65.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7495 5 0.01% 65.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7559 26 0.03% 65.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7623 7 0.01% 65.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7687 188 0.22% 65.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7751 2 0.00% 65.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7815 3 0.00% 65.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7943 68 0.08% 65.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8007 5 0.01% 65.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8071 6 0.01% 65.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8135 2 0.00% 65.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8199 602 0.69% 66.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8455 64 0.07% 66.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8711 184 0.21% 66.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8896-8903 1 0.00% 66.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8967 4 0.00% 66.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9024-9031 1 0.00% 66.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9152-9159 1 0.00% 66.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9223 261 0.30% 66.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9344-9351 1 0.00% 66.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9479 128 0.15% 66.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9536-9543 1 0.00% 66.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9600-9607 2 0.00% 66.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9735 3 0.00% 66.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9991 4 0.00% 66.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10247 451 0.52% 67.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10503 68 0.08% 67.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10759 63 0.07% 67.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11015 194 0.22% 67.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11072-11079 1 0.00% 67.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11271 259 0.30% 68.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11783 167 0.19% 68.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11968-11975 1 0.00% 68.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12039 5 0.01% 68.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12295 322 0.37% 68.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12352-12359 1 0.00% 68.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12480-12487 1 0.00% 68.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12551 135 0.16% 68.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12807 67 0.08% 68.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12864-12871 1 0.00% 68.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13063 55 0.06% 69.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13319 384 0.44% 69.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13575 185 0.21% 69.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13760-13767 1 0.00% 69.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13831 6 0.01% 69.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13952-13959 1 0.00% 69.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14087 126 0.15% 69.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14144-14151 1 0.00% 69.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14215 1 0.00% 69.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14343 259 0.30% 70.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14599 129 0.15% 70.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14855 129 0.15% 70.43% # Bytes accessed per row activation system.physmem.bytesPerActivate::15040-15047 1 0.00% 70.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15111 130 0.15% 70.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15367 263 0.30% 70.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15424-15431 1 0.00% 70.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15879 128 0.15% 71.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16000-16007 1 0.00% 71.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16135 62 0.07% 71.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16320-16327 1 0.00% 71.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16391 773 0.89% 72.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16647 60 0.07% 72.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16704-16711 1 0.00% 72.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16903 129 0.15% 72.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17024-17031 1 0.00% 72.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17415 261 0.30% 72.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17671 130 0.15% 72.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17927 64 0.07% 72.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18183 130 0.15% 72.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18439 328 0.38% 73.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18496-18503 1 0.00% 73.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18695 242 0.28% 73.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18816-18823 1 0.00% 73.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18944-18951 2 0.00% 73.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19207 137 0.16% 73.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19264-19271 1 0.00% 73.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19463 198 0.23% 73.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19520-19527 2 0.00% 73.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19584-19591 2 0.00% 73.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19648-19655 1 0.00% 73.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19719 63 0.07% 74.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19968-19975 69 0.08% 74.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20231 129 0.15% 74.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20487 386 0.45% 74.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20608-20615 1 0.00% 74.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20864-20871 1 0.00% 74.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20928-20935 1 0.00% 74.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-20999 194 0.22% 74.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21376-21383 1 0.00% 74.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21511 312 0.36% 75.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21767 67 0.08% 75.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22023 97 0.11% 75.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22279 65 0.08% 75.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22535 568 0.66% 76.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22791 55 0.06% 76.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22848-22855 1 0.00% 76.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22912-22919 2 0.00% 76.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23040-23047 2 0.00% 76.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23296-23303 183 0.21% 76.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23559 257 0.30% 76.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23808-23815 1 0.00% 76.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24071 135 0.16% 76.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24327 73 0.08% 77.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24448-24455 1 0.00% 77.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24583 388 0.45% 77.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24640-24647 1 0.00% 77.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24839 72 0.08% 77.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24896-24903 2 0.00% 77.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25088-25095 137 0.16% 77.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25152-25159 1 0.00% 77.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25216-25223 1 0.00% 77.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25344-25351 1 0.00% 77.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25607 257 0.30% 78.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25856-25863 182 0.21% 78.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25984-25991 1 0.00% 78.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26048-26055 2 0.00% 78.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26112-26119 1 0.00% 78.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26375 55 0.06% 78.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26631 568 0.66% 78.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26880-26887 64 0.07% 79.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27143 98 0.11% 79.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27399 69 0.08% 79.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27655 312 0.36% 79.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27968-27975 1 0.00% 79.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28160-28167 192 0.22% 79.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28224-28231 1 0.00% 79.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28423 2 0.00% 79.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28544-28551 2 0.00% 79.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28679 387 0.45% 80.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28800-28807 1 0.00% 80.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28935 130 0.15% 80.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29056-29063 1 0.00% 80.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29191 70 0.08% 80.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29376-29383 1 0.00% 80.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29447 64 0.07% 80.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29703 199 0.23% 80.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29824-29831 1 0.00% 80.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29888-29895 1 0.00% 80.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-29959 138 0.16% 80.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30208-30215 2 0.00% 80.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30471 236 0.27% 81.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30727 324 0.37% 81.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30912-30919 1 0.00% 81.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-30983 131 0.15% 81.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31040-31047 1 0.00% 81.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31239 65 0.08% 81.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31488-31495 131 0.15% 81.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31552-31559 1 0.00% 81.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31751 262 0.30% 82.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32192-32199 1 0.00% 82.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32256-32263 128 0.15% 82.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32512-32519 61 0.07% 82.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32775 772 0.89% 83.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32832-32839 1 0.00% 83.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32896-32903 1 0.00% 83.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33031 61 0.07% 83.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33287 129 0.15% 83.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33543 2 0.00% 83.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33600-33607 1 0.00% 83.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33664-33671 2 0.00% 83.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33799 262 0.30% 83.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34048-34055 131 0.15% 84.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34304-34311 64 0.07% 84.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34368-34375 1 0.00% 84.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34560-34567 131 0.15% 84.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34823 325 0.38% 84.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34944-34951 1 0.00% 84.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35072-35079 236 0.27% 84.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35328-35335 2 0.00% 84.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35584-35591 137 0.16% 85.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35847 198 0.23% 85.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36096-36103 64 0.07% 85.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36160-36167 1 0.00% 85.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36352-36359 70 0.08% 85.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36608-36615 129 0.15% 85.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36864-36871 384 0.44% 86.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37120-37127 1 0.00% 86.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37376-37383 192 0.22% 86.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37895 312 0.36% 86.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38144-38151 70 0.08% 86.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38400-38407 98 0.11% 86.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38656-38663 64 0.07% 86.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38912-38919 568 0.66% 87.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38976-38983 1 0.00% 87.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39168-39175 55 0.06% 87.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39232-39239 1 0.00% 87.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39424-39431 1 0.00% 87.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39488-39495 1 0.00% 87.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39552-39559 1 0.00% 87.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39680-39687 182 0.21% 87.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39808-39815 1 0.00% 87.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39936-39943 257 0.30% 88.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40192-40199 1 0.00% 88.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40448-40455 136 0.16% 88.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40640-40647 1 0.00% 88.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40704-40711 72 0.08% 88.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40960-40967 387 0.45% 88.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41024-41031 1 0.00% 88.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41152-41159 1 0.00% 88.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41216-41223 73 0.08% 88.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41472-41479 135 0.16% 89.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41728-41735 1 0.00% 89.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-41991 257 0.30% 89.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42240-42247 183 0.21% 89.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42688-42695 1 0.00% 89.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42752-42759 55 0.06% 89.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43008-43015 569 0.66% 90.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43136-43143 1 0.00% 90.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43264-43271 66 0.08% 90.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43520-43527 97 0.11% 90.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43776-43783 68 0.08% 90.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44032-44039 314 0.36% 90.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44160-44167 2 0.00% 90.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44288-44295 1 0.00% 90.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44544-44551 196 0.23% 91.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44800-44807 1 0.00% 91.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44992-44999 1 0.00% 91.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45056-45063 386 0.45% 91.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45312-45319 132 0.15% 91.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45440-45447 1 0.00% 91.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45568-45575 70 0.08% 91.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45824-45831 65 0.08% 91.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45888-45895 1 0.00% 91.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46016-46023 3 0.00% 91.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46087 199 0.23% 92.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46336-46343 135 0.16% 92.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46528-46535 1 0.00% 92.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46592-46599 1 0.00% 92.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46848-46855 239 0.28% 92.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47040-47047 1 0.00% 92.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47104-47111 324 0.37% 93.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47360-47367 131 0.15% 93.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47616-47623 64 0.07% 93.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47872-47879 131 0.15% 93.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48135 260 0.30% 93.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48640-48647 128 0.15% 93.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48832-48839 1 0.00% 93.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48903 61 0.07% 93.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48960-48967 3 0.00% 93.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49088-49095 1 0.00% 93.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49159 5274 6.09% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49344-49351 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49536-49543 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50176-50183 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50304-50311 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15111 124 0.14% 70.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15367 385 0.44% 71.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15623 3 0.00% 71.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15879 129 0.15% 71.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16135 67 0.08% 71.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16192-16199 1 0.00% 71.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16391 642 0.74% 71.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16448-16455 1 0.00% 71.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16647 65 0.07% 72.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16896-16903 128 0.15% 72.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17159 2 0.00% 72.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17280-17287 1 0.00% 72.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17344-17351 1 0.00% 72.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17415 384 0.44% 72.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17600-17607 1 0.00% 72.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17671 123 0.14% 72.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17927 129 0.15% 72.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18183 129 0.15% 73.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18368-18375 1 0.00% 73.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18439 261 0.30% 73.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18624-18631 1 0.00% 73.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18688-18695 126 0.15% 73.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18944-18951 6 0.01% 73.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19072-19079 1 0.00% 73.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19207 183 0.21% 73.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19264-19271 2 0.00% 73.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19392-19399 1 0.00% 73.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19463 384 0.44% 74.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19584-19591 1 0.00% 74.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19712-19719 55 0.06% 74.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19968-19975 67 0.08% 74.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20224-20231 132 0.15% 74.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20487 322 0.37% 74.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20736-20743 6 0.01% 74.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20992-20999 169 0.19% 75.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21248-21255 3 0.00% 75.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21511 256 0.29% 75.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21760-21767 195 0.22% 75.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21952-21959 1 0.00% 75.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22016-22023 63 0.07% 75.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22272-22279 64 0.07% 75.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22535 449 0.52% 76.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22592-22599 1 0.00% 76.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22784-22791 5 0.01% 76.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22848-22855 1 0.00% 76.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22912-22919 1 0.00% 76.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23040-23047 3 0.00% 76.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23296-23303 129 0.15% 76.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23559 259 0.30% 76.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23616-23623 1 0.00% 76.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23808-23815 4 0.00% 76.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23936-23943 1 0.00% 76.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24000-24007 1 0.00% 76.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24064-24071 184 0.21% 76.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24327 65 0.07% 77.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24448-24455 1 0.00% 77.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24583 497 0.57% 77.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24832-24839 65 0.07% 77.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25088-25095 186 0.21% 77.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25344-25351 4 0.00% 77.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25607 259 0.30% 78.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25792-25799 1 0.00% 78.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25856-25863 130 0.15% 78.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26112-26119 2 0.00% 78.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26375 6 0.01% 78.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26631 449 0.52% 78.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26880-26887 64 0.07% 78.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27136-27143 61 0.07% 79.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27399 194 0.22% 79.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27655 258 0.30% 79.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27712-27719 1 0.00% 79.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28032-28039 1 0.00% 79.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28160-28167 167 0.19% 79.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28352-28359 2 0.00% 79.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28423 5 0.01% 79.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28679 321 0.37% 80.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28935 130 0.15% 80.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29120-29127 1 0.00% 80.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29191 66 0.08% 80.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29376-29383 1 0.00% 80.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29447 54 0.06% 80.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29504-29511 1 0.00% 80.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29632-29639 1 0.00% 80.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29703 384 0.44% 80.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29888-29895 1 0.00% 80.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-29959 186 0.21% 81.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30144-30151 1 0.00% 81.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30215 7 0.01% 81.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30336-30343 1 0.00% 81.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30471 127 0.15% 81.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30656-30663 1 0.00% 81.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30727 260 0.30% 81.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30912-30919 1 0.00% 81.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-30983 130 0.15% 81.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31239 128 0.15% 81.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31360-31367 1 0.00% 81.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31424-31431 1 0.00% 81.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31495 123 0.14% 81.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31751 385 0.44% 82.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31872-31879 1 0.00% 82.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32007 3 0.00% 82.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32064-32071 1 0.00% 82.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32263 128 0.15% 82.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32519 65 0.07% 82.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32775 640 0.74% 83.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33031 65 0.07% 83.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33287 128 0.15% 83.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33543 3 0.00% 83.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33799 386 0.44% 84.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34048-34055 123 0.14% 84.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34304-34311 128 0.15% 84.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34368-34375 1 0.00% 84.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34560-34567 130 0.15% 84.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34823 260 0.30% 84.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35008-35015 1 0.00% 84.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35072-35079 126 0.15% 84.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35328-35335 8 0.01% 84.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35520-35527 1 0.00% 84.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35584-35591 185 0.21% 85.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35847 384 0.44% 85.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35968-35975 1 0.00% 85.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36032-36039 1 0.00% 85.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36096-36103 55 0.06% 85.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36352-36359 67 0.08% 85.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36608-36615 130 0.15% 85.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36871 321 0.37% 86.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37120-37127 5 0.01% 86.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37376-37383 165 0.19% 86.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37504-37511 1 0.00% 86.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37895 258 0.30% 86.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38151 194 0.22% 86.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38400-38407 60 0.07% 87.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38656-38663 64 0.07% 87.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38784-38791 1 0.00% 87.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38919 449 0.52% 87.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39168-39175 5 0.01% 87.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39424-39431 3 0.00% 87.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39680-39687 128 0.15% 87.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39744-39751 1 0.00% 87.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39808-39815 1 0.00% 87.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39936-39943 257 0.30% 88.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40192-40199 4 0.00% 88.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40448-40455 186 0.21% 88.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40704-40711 65 0.07% 88.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40967 498 0.57% 88.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41223 65 0.07% 89.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41472-41479 183 0.21% 89.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41600-41607 1 0.00% 89.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41664-41671 1 0.00% 89.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41728-41735 4 0.00% 89.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41856-41863 1 0.00% 89.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-41991 258 0.30% 89.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42240-42247 128 0.15% 89.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42503 2 0.00% 89.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42688-42695 1 0.00% 89.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42759 4 0.00% 89.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42944-42951 1 0.00% 89.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43015 450 0.52% 90.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43136-43143 1 0.00% 90.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43200-43207 1 0.00% 90.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43271 65 0.07% 90.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43456-43463 1 0.00% 90.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43527 59 0.07% 90.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43712-43719 1 0.00% 90.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43776-43783 195 0.22% 90.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 257 0.30% 90.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44224-44231 2 0.00% 90.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44295 1 0.00% 90.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44352-44359 2 0.00% 90.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44551 168 0.19% 91.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44672-44679 1 0.00% 91.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44807 6 0.01% 91.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44928-44935 2 0.00% 91.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44992-44999 1 0.00% 91.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 327 0.38% 91.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45319 131 0.15% 91.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 67 0.08% 91.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 55 0.06% 91.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 386 0.44% 92.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46144-46151 1 0.00% 92.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46343 185 0.21% 92.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46599 6 0.01% 92.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 126 0.15% 92.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46912-46919 1 0.00% 92.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 260 0.30% 92.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 129 0.15% 93.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 130 0.15% 93.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47808-47815 1 0.00% 93.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 122 0.14% 93.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48000-48007 1 0.00% 93.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 386 0.44% 93.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 1 0.00% 93.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 129 0.15% 93.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 65 0.07% 93.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48960-48967 2 0.00% 93.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 1 0.00% 93.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 5210 6.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49600-49607 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49664-49671 2 0.00% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::50688-50695 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51072-51079 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51200-51207 3 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51968-51975 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 86636 # Bytes accessed per row activation -system.physmem.totQLat 369559391250 # Total ticks spent queuing -system.physmem.totMemAccLat 463610140000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 76423455000 # Total ticks spent in databus transfers -system.physmem.totBankLat 17627293750 # Total ticks spent accessing banks -system.physmem.avgQLat 24178.40 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1153.26 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::50816-50823 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51008-51015 2 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51136-51143 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51200-51207 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51456-51463 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::52416-52423 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 86806 # Bytes accessed per row activation +system.physmem.totQLat 369546937250 # Total ticks spent queuing +system.physmem.totMemAccLat 463545387250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 76424795000 # Total ticks spent in databus transfers +system.physmem.totBankLat 17573655000 # Total ticks spent accessing banks +system.physmem.avgQLat 24177.16 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1149.74 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30331.67 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 383.71 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 30326.90 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 383.55 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.71 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 51.39 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 51.37 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.67 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 3.02 # Data bus utilization in percentage @@ -575,13 +594,13 @@ system.physmem.busUtilRead 3.00 # Da system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing system.physmem.avgWrQLen 1.05 # Average write queue length when enqueuing -system.physmem.readRowHits 15212838 # Number of row buffer hits during reads -system.physmem.writeRowHits 93174 # Number of row buffer hits during writes +system.physmem.readRowHits 15213019 # Number of row buffer hits during reads +system.physmem.writeRowHits 93108 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.53 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 86.29 # Row buffer hit rate for writes -system.physmem.avgGap 158279.45 # Average gap between requests +system.physmem.writeRowHitRate 86.23 # Row buffer hit rate for writes +system.physmem.avgGap 158347.97 # Average gap between requests system.physmem.pageHitRate 99.44 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 1.88 # Percentage of time for which DRAM has all the banks in precharge state +system.physmem.prechargeAllPercent 2.65 # Percentage of time for which DRAM has all the banks in precharge state system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory @@ -594,285 +613,305 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54995612 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16346068 # Transaction distribution -system.membus.trans_dist::ReadResp 16346071 # Transaction distribution +system.membus.throughput 54973413 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16346095 # Transaction distribution +system.membus.trans_dist::ReadResp 16346098 # Transaction distribution system.membus.trans_dist::WriteReq 763348 # Transaction distribution system.membus.trans_dist::WriteResp 763348 # Transaction distribution -system.membus.trans_dist::Writeback 59135 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4685 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4685 # Transaction distribution -system.membus.trans_dist::ReadExReq 131422 # Transaction distribution -system.membus.trans_dist::ReadExResp 131422 # Transaction distribution +system.membus.trans_dist::Writeback 59165 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4689 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4690 # Transaction distribution +system.membus.trans_dist::ReadExReq 131440 # Transaction distribution +system.membus.trans_dist::ReadExResp 131440 # Transaction distribution system.membus.trans_dist::LoadLockedReq 3 # Transaction distribution system.membus.trans_dist::StoreCondReq 3 # Transaction distribution system.membus.trans_dist::StoreCondResp 3 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382960 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382958 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3790 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1885807 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4272561 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1885939 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4272691 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34550193 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390337 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 34550323 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390333 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7580 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16694284 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 19092269 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16699028 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 19097009 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 140202797 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 140202797 # Total data (bytes) +system.membus.tot_pkt_size::total 140207537 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 140207537 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1487346000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1487746500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3636500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3620500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17566569000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17566438500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4736419263 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4736460824 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 34186627978 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 34185683234 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 64357 # number of replacements -system.l2c.tags.tagsinuse 51453.251473 # Cycle average of tags in use -system.l2c.tags.total_refs 1905423 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 129744 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 14.686020 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2512210729500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 36987.198092 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 19.713113 # Average occupied blocks per requestor +system.l2c.tags.replacements 64398 # number of replacements +system.l2c.tags.tagsinuse 51440.737713 # Cycle average of tags in use +system.l2c.tags.total_refs 1904463 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 129791 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 14.673306 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2513095359500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 36974.659237 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 18.382027 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000371 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4872.243485 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3313.752357 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 13.584037 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3345.363294 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2901.396724 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.564380 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000301 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.inst 4864.361052 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3325.264959 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 12.733963 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 0.979227 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3333.561172 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2910.795705 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.564189 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000280 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.074345 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.050564 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000207 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.051046 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.044272 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.785114 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 24 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65363 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 24 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 345 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3051 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6862 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55068 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000366 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.997360 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 18937227 # Number of tag accesses -system.l2c.tags.data_accesses 18937227 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 32950 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 7107 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 506567 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 181823 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 30566 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 6814 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 464544 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 205967 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1436338 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 608494 # number of Writeback hits -system.l2c.Writeback_hits::total 608494 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 18 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 16 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 34 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 2 # number of SCUpgradeReq hits +system.l2c.tags.occ_percent::cpu0.inst 0.074224 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.050740 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000194 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.050866 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.044415 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.784923 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 23 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65370 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 22 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 341 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3070 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6833 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 55085 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000351 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.997467 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 18926387 # Number of tag accesses +system.l2c.tags.data_accesses 18926387 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 32717 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 6688 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 507057 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 188596 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 30977 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 7027 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 463887 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 198617 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1435566 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 607936 # number of Writeback hits +system.l2c.Writeback_hits::total 607936 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 19 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 17 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 36 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 3 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu1.data 4 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 6 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 58298 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 54682 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 112980 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 32950 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 7107 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 506567 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 240121 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 30566 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 6814 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 464544 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 260649 # number of demand (read+write) hits -system.l2c.demand_hits::total 1549318 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 32950 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 7107 # number of overall hits -system.l2c.overall_hits::cpu0.inst 506567 # number of overall hits -system.l2c.overall_hits::cpu0.data 240121 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 30566 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 6814 # number of overall hits -system.l2c.overall_hits::cpu1.inst 464544 # number of overall hits -system.l2c.overall_hits::cpu1.data 260649 # number of overall hits -system.l2c.overall_hits::total 1549318 # number of overall hits +system.l2c.SCUpgradeReq_hits::total 7 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 60659 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 52244 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 112903 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 32717 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 6688 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 507057 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 249255 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 30977 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 7027 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 463887 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 250861 # number of demand (read+write) hits +system.l2c.demand_hits::total 1548469 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 32717 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 6688 # number of overall hits +system.l2c.overall_hits::cpu0.inst 507057 # number of overall hits +system.l2c.overall_hits::cpu0.data 249255 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 30977 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 7027 # number of overall hits +system.l2c.overall_hits::cpu1.inst 463887 # number of overall hits +system.l2c.overall_hits::cpu1.data 250861 # number of overall hits +system.l2c.overall_hits::total 1548469 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 29 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 7681 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6151 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 16 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 4714 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 4533 # number of ReadReq misses -system.l2c.ReadReq_misses::total 23126 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1282 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1636 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2918 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 67869 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 65320 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 133189 # number of ReadExReq misses +system.l2c.ReadReq_misses::cpu0.inst 7772 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 6310 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 14 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 4598 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 4426 # number of ReadReq misses +system.l2c.ReadReq_misses::total 23152 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1623 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1291 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2914 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 1 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 73806 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 59409 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 133215 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 29 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 7681 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 74020 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 16 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 4714 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 69853 # number of demand (read+write) misses -system.l2c.demand_misses::total 156315 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 7772 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 80116 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 14 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 4598 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 63835 # number of demand (read+write) misses +system.l2c.demand_misses::total 156367 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 29 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 7681 # number of overall misses -system.l2c.overall_misses::cpu0.data 74020 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 16 # number of overall misses -system.l2c.overall_misses::cpu1.inst 4714 # number of overall misses -system.l2c.overall_misses::cpu1.data 69853 # number of overall misses -system.l2c.overall_misses::total 156315 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 2207500 # number of ReadReq miss cycles +system.l2c.overall_misses::cpu0.inst 7772 # number of overall misses +system.l2c.overall_misses::cpu0.data 80116 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 14 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses +system.l2c.overall_misses::cpu1.inst 4598 # number of overall misses +system.l2c.overall_misses::cpu1.data 63835 # number of overall misses +system.l2c.overall_misses::total 156367 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 2411500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.itb.walker 158000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 559087000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 461077500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1541500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 349988250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 349614499 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1723674249 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 255989 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 162493 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 418482 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 5047283901 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 4980536832 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 10027820733 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 2207500 # number of demand (read+write) miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 562480250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 472355249 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1382500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.itb.walker 75000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 339266250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 344164000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1722292749 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 162493 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 280988 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 443481 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 5508293110 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 4400568365 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 9908861475 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 2411500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.itb.walker 158000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 559087000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 5508361401 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 1541500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 349988250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 5330151331 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 11751494982 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 2207500 # number of overall miss cycles +system.l2c.demand_miss_latency::cpu0.inst 562480250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 5980648359 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 1382500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.itb.walker 75000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 339266250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 4744732365 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 11631154224 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 2411500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.itb.walker 158000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 559087000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 5508361401 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 1541500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 349988250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 5330151331 # number of overall miss cycles -system.l2c.overall_miss_latency::total 11751494982 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 32979 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 7109 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 514248 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 187974 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 30582 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 6814 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 469258 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 210500 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1459464 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 608494 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 608494 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 1300 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1652 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2952 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 2 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.overall_miss_latency::cpu0.inst 562480250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 5980648359 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 1382500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.itb.walker 75000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 339266250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 4744732365 # number of overall miss cycles +system.l2c.overall_miss_latency::total 11631154224 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 32746 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 6690 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 514829 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 194906 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 30991 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 7028 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 468485 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 203043 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1458718 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 607936 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 607936 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 1642 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 1308 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2950 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 4 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu1.data 4 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 6 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 126167 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 120002 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 246169 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 32979 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 7109 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 514248 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 314141 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 30582 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 6814 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 469258 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 330502 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1705633 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 32979 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 7109 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 514248 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 314141 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 30582 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 6814 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 469258 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 330502 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1705633 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000879 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000281 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.014936 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.032723 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000523 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.010046 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.021534 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.015846 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.986154 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.990315 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.988482 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.537930 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.544324 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.541047 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000879 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000281 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.014936 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.235627 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000523 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.010046 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.211354 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.091646 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000879 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000281 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.014936 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.235627 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000523 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.010046 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.211354 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.091646 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 76120.689655 # average ReadReq miss latency +system.l2c.SCUpgradeReq_accesses::total 8 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 134465 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 111653 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 246118 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 32746 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 6690 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 514829 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 329371 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 30991 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 7028 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 468485 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 314696 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1704836 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 32746 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 6690 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 514829 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 329371 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 30991 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 7028 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 468485 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 314696 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1704836 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000886 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000299 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.015096 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.032375 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000452 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000142 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.009815 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.021798 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.015871 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.988429 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.987003 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.987797 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.250000 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.125000 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.548886 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.532086 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.541265 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000886 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000299 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.015096 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.243239 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000452 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.000142 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.009815 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.202847 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.091720 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000886 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000299 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.015096 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.243239 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000452 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.000142 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.009815 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.202847 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.091720 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 83155.172414 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 79000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 72788.308814 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 74959.762640 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 96343.750000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 74244.431481 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 77126.516435 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 74534.041728 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 199.679407 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 99.323350 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 143.413982 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 74368.031075 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 76248.267483 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 75290.157093 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 76120.689655 # average overall miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 72372.651827 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 74858.201109 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 98750 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 75000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 73785.613310 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 77759.602350 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 74390.668150 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 100.118916 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 217.651433 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 152.189774 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 74632.050375 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 74072.419415 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 74382.475510 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 83155.172414 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.itb.walker 79000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 72788.308814 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 74417.203472 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 96343.750000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 74244.431481 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 76305.260060 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 75178.293715 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 76120.689655 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 72372.651827 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 74649.862187 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 98750 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.itb.walker 75000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 73785.613310 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 74328.070259 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 74383.688528 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 83155.172414 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.itb.walker 79000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 72788.308814 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 74417.203472 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 96343.750000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 74244.431481 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 76305.260060 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 75178.293715 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 72372.651827 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 74649.862187 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 98750 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.itb.walker 75000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 73785.613310 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 74328.070259 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 74383.688528 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -881,158 +920,178 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 59135 # number of writebacks -system.l2c.writebacks::total 59135 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0.inst 5 # number of ReadReq MSHR hits +system.l2c.writebacks::writebacks 59165 # number of writebacks +system.l2c.writebacks::total 59165 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0.inst 7 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu0.data 44 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu1.inst 7 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.data 23 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 79 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 5 # number of demand (read+write) MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.data 24 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 82 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 7 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu0.data 44 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.data 23 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 79 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 5 # number of overall MSHR hits +system.l2c.demand_mshr_hits::cpu1.data 24 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 82 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 7 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu0.data 44 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.data 23 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 79 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.data 24 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 82 # number of overall MSHR hits system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 29 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 7676 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 6107 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 16 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 4707 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 4510 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 23047 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 1282 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 1636 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 2918 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 67869 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 65320 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 133189 # number of ReadExReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 7765 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 6266 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 14 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 4591 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 4402 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 23070 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 1623 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 1291 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 2914 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 1 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 73806 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 59409 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 133215 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu0.dtb.walker 29 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 7676 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 73976 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 16 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 4707 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 69830 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 156236 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 7765 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 80072 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 14 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 4591 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 63811 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 156285 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu0.dtb.walker 29 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 7676 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 73976 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 16 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 4707 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 69830 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 156236 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 1848500 # number of ReadReq MSHR miss cycles +system.l2c.overall_mshr_misses::cpu0.inst 7765 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 80072 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 14 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 4591 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 63811 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 156285 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 2051500 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 133500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 462156500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 381785750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 1343500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 290452750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 292088999 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1429809499 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 12821282 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 16367635 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 29188917 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4199900099 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4165909168 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 8365809267 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 1848500 # number of demand (read+write) MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 464320500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 391082249 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 1210500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 62500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 281154500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 287909500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1427924749 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 16231623 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 12916289 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 29147912 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 10001 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 10001 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4587475890 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3659831635 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 8247307525 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 2051500 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 133500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 462156500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 4581685849 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1343500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 290452750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 4457998167 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 9795618766 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 1848500 # number of overall MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 464320500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 4978558139 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1210500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 62500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 281154500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 3947741135 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 9675232274 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 2051500 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 133500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 462156500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 4581685849 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1343500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 290452750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 4457998167 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 9795618766 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 6012999 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 84589545750 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 82347341250 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 166942899999 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 8959860803 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8414119000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 17373979803 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 464320500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 4978558139 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1210500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 62500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 281154500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 3947741135 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 9675232274 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 6162749 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 83808284500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 83128929250 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 166943376499 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 8942076738 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8427643000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 17369719738 # number of WriteReq MSHR uncacheable cycles system.l2c.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 116250 # number of LoadLockedReq MSHR uncacheable cycles system.l2c.LoadLockedReq_mshr_uncacheable_latency::total 116250 # number of LoadLockedReq MSHR uncacheable cycles system.l2c.StoreCondReq_mshr_uncacheable_latency::cpu1.data 60000 # number of StoreCondReq MSHR uncacheable cycles system.l2c.StoreCondReq_mshr_uncacheable_latency::total 60000 # number of StoreCondReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 6012999 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 93549406553 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 90761460250 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 184316879802 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000879 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000281 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014927 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.032489 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000523 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010031 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.021425 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.015791 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.986154 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.990315 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.988482 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.537930 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.544324 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.541047 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000879 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000281 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014927 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.235487 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000523 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010031 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.211285 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.091600 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000879 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000281 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014927 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.235487 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000523 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010031 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.211285 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.091600 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 63741.379310 # average ReadReq mshr miss latency +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 6162749 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 92750361238 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 91556572250 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 184313096237 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000886 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000299 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015083 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.032149 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000452 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000142 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009800 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.021680 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.015815 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.988429 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.987003 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.987797 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.250000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.125000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.548886 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.532086 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.541265 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000886 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000299 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015083 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.243106 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000452 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000142 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009800 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.202770 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.091672 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000886 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000299 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015083 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.243106 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000452 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000142 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009800 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.202770 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.091672 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 70741.379310 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 66750 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60207.985930 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 62516.088096 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 83968.750000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61706.554068 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 64764.744789 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 62038.855339 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59796.587250 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 62413.381583 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 86464.285714 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61240.361577 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65404.248069 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 61895.307716 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10004.666870 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10003.055860 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 61882.451473 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 63776.931537 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 62811.563019 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 63741.379310 # average overall mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10004.871418 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10002.715168 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 62155.866596 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61603.993250 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 61909.751342 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 70741.379310 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 66750 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60207.985930 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61934.760585 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 83968.750000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61706.554068 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 63840.729873 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 62697.577805 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 63741.379310 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59796.587250 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 62176.018321 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 86464.285714 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61240.361577 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61866.153720 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 61907.619247 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 70741.379310 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 66750 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60207.985930 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61934.760585 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 83968.750000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61706.554068 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63840.729873 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 62697.577805 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59796.587250 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 62176.018321 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 86464.285714 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61240.361577 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61866.153720 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 61907.619247 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -1055,49 +1114,49 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 58478558 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2677542 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2677544 # Transaction distribution +system.toL2Bus.throughput 58420424 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2676760 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2676762 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 763348 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 763348 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 608494 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2952 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 6 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 607936 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2950 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 8 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 2958 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 246169 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 246169 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 246118 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 246118 # Transaction distribution system.toL2Bus.trans_dist::LoadLockedReq 3 # Transaction distribution system.toL2Bus.trans_dist::StoreCondReq 3 # Transaction distribution system.toL2Bus.trans_dist::StoreCondResp 3 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1968408 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5798582 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 38031 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 149645 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7954666 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 62951744 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 85614957 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 55692 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 254244 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 148876637 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 148876637 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 205392 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4965399712 # Layer occupancy (ticks) +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1968062 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5796874 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 37580 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 149966 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7952482 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 62939648 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 85542385 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 54872 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 254948 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 148791853 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 148791853 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 207152 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4962468234 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4434611165 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4433875230 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4486677044 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4484319469 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 24152407 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 23911393 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 86557036 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 86679578 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48444152 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16322136 # Transaction distribution -system.iobus.trans_dist::ReadResp 16322136 # Transaction distribution +system.iobus.throughput 48422959 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16322135 # Transaction distribution +system.iobus.trans_dist::ReadResp 16322135 # Transaction distribution system.iobus.trans_dist::WriteReq 8160 # Transaction distribution system.iobus.trans_dist::WriteResp 8160 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7942 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7940 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 522 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1030 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -1119,12 +1178,12 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382960 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382958 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 32660592 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 32660590 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15884 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15880 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1044 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2060 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -1146,14 +1205,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390337 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390333 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 123500865 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 123500865 # Total data (bytes) +system.iobus.tot_pkt_size::total 123500861 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 123500861 # Total data (bytes) system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3976000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 3975000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 522000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1199,698 +1258,740 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374800000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374798000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 41494630022 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 41495326766 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) -system.cpu0.branchPred.lookups 7183590 # Number of BP lookups -system.cpu0.branchPred.condPredicted 5694303 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 377290 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 4721847 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 3824688 # Number of BTB hits +system.cpu0.branchPred.lookups 7528776 # Number of BP lookups +system.cpu0.branchPred.condPredicted 6012881 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 377531 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 4829761 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 3930404 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 80.999829 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 708757 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 39349 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 81.378851 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 724348 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 39225 # Number of incorrect RAS predictions. +system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 25676392 # DTB read hits -system.cpu0.dtb.read_misses 38073 # DTB read misses -system.cpu0.dtb.write_hits 5871403 # DTB write hits -system.cpu0.dtb.write_misses 9193 # DTB write misses -system.cpu0.dtb.flush_tlb 257 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 25731693 # DTB read hits +system.cpu0.dtb.read_misses 40178 # DTB read misses +system.cpu0.dtb.write_hits 6168711 # DTB write hits +system.cpu0.dtb.write_misses 10337 # DTB write misses +system.cpu0.dtb.flush_tlb 514 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 629 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 776 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5420 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1344 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 238 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 5677 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1369 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 257 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 585 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 25714465 # DTB read accesses -system.cpu0.dtb.write_accesses 5880596 # DTB write accesses +system.cpu0.dtb.perms_faults 641 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 25771871 # DTB read accesses +system.cpu0.dtb.write_accesses 6179048 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 31547795 # DTB hits -system.cpu0.dtb.misses 47266 # DTB misses -system.cpu0.dtb.accesses 31595061 # DTB accesses -system.cpu0.itb.inst_hits 5793609 # ITB inst hits -system.cpu0.itb.inst_misses 6965 # ITB inst misses +system.cpu0.dtb.hits 31900404 # DTB hits +system.cpu0.dtb.misses 50515 # DTB misses +system.cpu0.dtb.accesses 31950919 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.itb.inst_hits 5899860 # ITB inst hits +system.cpu0.itb.inst_misses 7207 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 257 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 514 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 629 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 776 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2542 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2688 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1475 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1562 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 5800574 # ITB inst accesses -system.cpu0.itb.hits 5793609 # DTB hits -system.cpu0.itb.misses 6965 # DTB misses -system.cpu0.itb.accesses 5800574 # DTB accesses -system.cpu0.numCycles 241355643 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 5907067 # ITB inst accesses +system.cpu0.itb.hits 5899860 # DTB hits +system.cpu0.itb.misses 7207 # DTB misses +system.cpu0.itb.accesses 5907067 # DTB accesses +system.cpu0.numCycles 242297109 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 15408312 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 44581736 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 7183590 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 4533445 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 10042154 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2412494 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 81949 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 48815807 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 1726 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 1993 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 42608 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 1411972 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 385 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 5791670 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 368874 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 3149 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 77468964 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.722040 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.069743 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 15555542 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 45617593 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 7528776 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 4654752 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 10311247 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2439507 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 83051 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 50330649 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 1691 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 2002 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 48587 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 1491133 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 722 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 5897866 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 368478 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 3041 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 79507031 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.722707 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.070799 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 67434698 87.05% 87.05% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 662922 0.86% 87.90% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 849826 1.10% 89.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1158615 1.50% 90.50% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1071303 1.38% 91.88% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 540404 0.70% 92.58% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 1264103 1.63% 94.21% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 371341 0.48% 94.69% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4115752 5.31% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 69202528 87.04% 87.04% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 678265 0.85% 87.89% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 875305 1.10% 88.99% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1177307 1.48% 90.47% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1118218 1.41% 91.88% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 557082 0.70% 92.58% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 1282023 1.61% 94.19% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 381348 0.48% 94.67% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4234955 5.33% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 77468964 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.029764 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.184714 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 16332862 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 49931887 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 9147459 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 483482 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1571127 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 985970 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 93586 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 53203424 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 313882 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1571127 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 17204608 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 20551297 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 26349401 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 8685161 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 3105311 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 50667470 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 7242 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 502803 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 2087731 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 194 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 52194379 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 231353972 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 213903823 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 5361 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 38031727 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 14162651 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 415813 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 366209 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 6409920 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9794680 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6688167 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1031152 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1299354 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 47050561 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 979447 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 60972564 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 88288 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 9787230 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 24359943 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 256705 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 77468964 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.787058 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.508592 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 79507031 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.031072 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.188271 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 16656471 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 51363244 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 9231902 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 659908 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1593273 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 1005882 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 91811 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 54700033 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 305616 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1593273 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 17552192 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 20324540 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 27741870 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 8932000 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3360998 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 52127379 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 375 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 510306 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 2174045 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 221 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 53799249 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 241745694 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 220537236 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 5112 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 39397526 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 14401722 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 594296 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 542687 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 6992906 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 10039494 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6994522 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1049493 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1384753 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 48432856 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1029992 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 62172633 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 89012 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 9963233 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 24631985 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 276940 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 79507031 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.781977 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.500620 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 55694568 71.89% 71.89% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 6744950 8.71% 80.60% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3431902 4.43% 85.03% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2928703 3.78% 88.81% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 6175861 7.97% 96.78% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1433177 1.85% 98.63% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 773017 1.00% 99.63% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 224018 0.29% 99.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 62768 0.08% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 56951176 71.63% 71.63% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 7375765 9.28% 80.91% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3517120 4.42% 85.33% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2922983 3.68% 89.01% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 6158188 7.75% 96.75% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1492282 1.88% 98.63% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 793715 1.00% 99.63% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 229189 0.29% 99.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 66613 0.08% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 77468964 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 79507031 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 30016 0.67% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 1 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 4221900 94.67% 95.34% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 207684 4.66% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 30271 0.68% 0.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 2 0.00% 0.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 4195541 94.33% 95.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 221720 4.99% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 165809 0.27% 0.27% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 28246973 46.33% 46.60% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 46806 0.08% 46.68% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 46.68% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 46.68% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 46.68% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 46.68% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 46.68% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 46.68% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 46.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 46.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 46.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 46.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 46.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 46.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 14 0.00% 46.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 46.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 46.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 46.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 9 0.00% 46.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 46.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 46.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 46.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 46.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 1267 0.00% 46.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 46.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 46.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 46.68% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 26338371 43.20% 89.88% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6173305 10.12% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 15963 0.03% 0.03% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 29223949 47.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 47621 0.08% 47.11% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.11% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.11% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.11% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.11% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.11% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.11% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 9 0.00% 47.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 47.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 6 0.00% 47.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 1246 0.00% 47.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 47.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.11% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 26409062 42.48% 89.59% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 6474770 10.41% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 60972564 # Type of FU issued -system.cpu0.iq.rate 0.252625 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 4459601 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.073141 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 203996977 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 57825737 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 42036875 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 12074 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 6420 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 5360 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 65259915 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 6441 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 303470 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 62172633 # Type of FU issued +system.cpu0.iq.rate 0.256597 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 4447534 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.071535 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 208427694 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 59435167 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 43384407 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 11467 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 6219 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 5237 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 66598153 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 6051 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 313701 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2107176 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3913 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 15490 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 838182 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2134408 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3835 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 15882 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 849708 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 17232343 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 348683 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 17067409 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 348218 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1571127 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 15861030 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 237452 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 48130825 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 105592 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9794680 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6688167 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 690516 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 54721 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 4205 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 15490 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 181987 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 144371 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 326358 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 59914186 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 26012956 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1058378 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1593273 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 15683016 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 239861 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 49569735 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 107283 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 10039494 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6994522 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 730989 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 55378 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 4828 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 15882 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 184147 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 145491 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 329638 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 61106002 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 26080146 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1066631 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 100817 # number of nop insts executed -system.cpu0.iew.exec_refs 32128938 # number of memory reference insts executed -system.cpu0.iew.exec_branches 5674429 # Number of branches executed -system.cpu0.iew.exec_stores 6115982 # Number of stores executed -system.cpu0.iew.exec_rate 0.248240 # Inst execution rate -system.cpu0.iew.wb_sent 59424173 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 42042235 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 22754717 # num instructions producing a value -system.cpu0.iew.wb_consumers 41618983 # num instructions consuming a value +system.cpu0.iew.exec_nop 106887 # number of nop insts executed +system.cpu0.iew.exec_refs 32497006 # number of memory reference insts executed +system.cpu0.iew.exec_branches 5987699 # Number of branches executed +system.cpu0.iew.exec_stores 6416860 # Number of stores executed +system.cpu0.iew.exec_rate 0.252195 # Inst execution rate +system.cpu0.iew.wb_sent 60612995 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 43389644 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 23417175 # num instructions producing a value +system.cpu0.iew.wb_consumers 43060015 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.174192 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.546739 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.179076 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.543826 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 9657152 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 722742 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 285161 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 75897837 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.500741 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.473402 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 9791777 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 753052 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 287149 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 77913758 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.504003 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.469415 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 62326931 82.12% 82.12% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 6623929 8.73% 90.85% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1927651 2.54% 93.39% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1062809 1.40% 94.79% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 977806 1.29% 96.08% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 537572 0.71% 96.78% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 721191 0.95% 97.73% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 348340 0.46% 98.19% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1371608 1.81% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 63454715 81.44% 81.44% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7423327 9.53% 90.97% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1988141 2.55% 93.52% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1098394 1.41% 94.93% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 861624 1.11% 96.04% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 581195 0.75% 96.78% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 738806 0.95% 97.73% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 351756 0.45% 98.18% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1415800 1.82% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 75897837 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 29270698 # Number of instructions committed -system.cpu0.commit.committedOps 38005132 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 77913758 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 30063645 # Number of instructions committed +system.cpu0.commit.committedOps 39268790 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13537489 # Number of memory references committed -system.cpu0.commit.loads 7687504 # Number of loads committed -system.cpu0.commit.membars 203418 # Number of memory barriers committed -system.cpu0.commit.branches 4891612 # Number of branches committed -system.cpu0.commit.fp_insts 5306 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 33685063 # Number of committed integer instructions. -system.cpu0.commit.function_calls 497791 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1371608 # number cycles where commit BW limit reached +system.cpu0.commit.refs 14049900 # Number of memory references committed +system.cpu0.commit.loads 7905086 # Number of loads committed +system.cpu0.commit.membars 209983 # Number of memory barriers committed +system.cpu0.commit.branches 5182251 # Number of branches committed +system.cpu0.commit.fp_insts 5199 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 34974968 # Number of committed integer instructions. +system.cpu0.commit.function_calls 508855 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1415800 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 121269057 # The number of ROB reads -system.cpu0.rob.rob_writes 96938789 # The number of ROB writes -system.cpu0.timesIdled 907351 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 163886679 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2251360755 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 29203197 # Number of Instructions Simulated -system.cpu0.committedOps 37937631 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 29203197 # Number of Instructions Simulated -system.cpu0.cpi 8.264699 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 8.264699 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.120997 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.120997 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 271224247 # number of integer regfile reads -system.cpu0.int_regfile_writes 42758050 # number of integer regfile writes -system.cpu0.fp_regfile_reads 22657 # number of floating regfile reads -system.cpu0.fp_regfile_writes 19930 # number of floating regfile writes -system.cpu0.misc_regfile_reads 15040337 # number of misc regfile reads -system.cpu0.misc_regfile_writes 403311 # number of misc regfile writes -system.cpu0.icache.tags.replacements 984140 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.573239 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 10515740 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 984652 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 10.679651 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 7012159250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 319.827324 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 191.745915 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.624663 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.374504 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999166 # Average percentage of cache occupancy +system.cpu0.rob.rob_reads 124579792 # The number of ROB reads +system.cpu0.rob.rob_writes 99757537 # The number of ROB writes +system.cpu0.timesIdled 906870 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 162790078 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2250741366 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 29991762 # Number of Instructions Simulated +system.cpu0.committedOps 39196907 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 29991762 # Number of Instructions Simulated +system.cpu0.cpi 8.078789 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 8.078789 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.123781 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.123781 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 277582728 # number of integer regfile reads +system.cpu0.int_regfile_writes 44079568 # number of integer regfile writes +system.cpu0.fp_regfile_reads 44948 # number of floating regfile reads +system.cpu0.fp_regfile_writes 42562 # number of floating regfile writes +system.cpu0.misc_regfile_reads 138472263 # number of misc regfile reads +system.cpu0.misc_regfile_writes 583698 # number of misc regfile writes +system.cpu0.icache.tags.replacements 983976 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.534971 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 10503842 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 984488 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 10.669345 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 7011386250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 317.535325 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 193.999646 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.620186 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.378906 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999092 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 210 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 167 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 164 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 12566622 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 12566622 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 5233615 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 5282125 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 10515740 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5233615 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 5282125 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 10515740 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5233615 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 5282125 # number of overall hits -system.cpu0.icache.overall_hits::total 10515740 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 557933 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 508279 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1066212 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 557933 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 508279 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1066212 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 557933 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 508279 # number of overall misses -system.cpu0.icache.overall_misses::total 1066212 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7711361387 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6850959748 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 14562321135 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 7711361387 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 6850959748 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 14562321135 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 7711361387 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 6850959748 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 14562321135 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 5791548 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 5790404 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 11581952 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 5791548 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 5790404 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 11581952 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 5791548 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 5790404 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 11581952 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.096336 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.087780 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.092058 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.096336 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.087780 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.092058 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.096336 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.087780 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.092058 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13821.303610 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13478.738543 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13657.997786 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13821.303610 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13478.738543 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13657.997786 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13821.303610 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13478.738543 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13657.997786 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 6730 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 450 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 431 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 12554064 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 12554064 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 5339906 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 5163936 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 10503842 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 5339906 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 5163936 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 10503842 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 5339906 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 5163936 # number of overall hits +system.cpu0.icache.overall_hits::total 10503842 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 557837 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 507875 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1065712 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 557837 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 507875 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1065712 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 557837 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 507875 # number of overall misses +system.cpu0.icache.overall_misses::total 1065712 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7709624467 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6833167274 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 14542791741 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 7709624467 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 6833167274 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 14542791741 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 7709624467 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 6833167274 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 14542791741 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 5897743 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 5671811 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 11569554 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 5897743 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 5671811 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 11569554 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 5897743 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 5671811 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 11569554 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.094585 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.089544 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.092113 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.094585 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.089544 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.092113 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.094585 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.089544 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.092113 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13820.568494 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13454.427318 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13646.080499 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13820.568494 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13454.427318 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13646.080499 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13820.568494 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13454.427318 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13646.080499 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 7635 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 400 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 377 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.614849 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 450 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 20.251989 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 400 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 43117 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 38424 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 81541 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 43117 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu1.inst 38424 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 81541 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 43117 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu1.inst 38424 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 81541 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 514816 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 469855 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 984671 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 514816 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 469855 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 984671 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 514816 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 469855 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 984671 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 6258274414 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5575421883 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 11833696297 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 6258274414 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5575421883 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 11833696297 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 6258274414 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5575421883 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 11833696297 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8426500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8426500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8426500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 8426500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.088891 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.081144 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.085018 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.088891 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.081144 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.085018 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.088891 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.081144 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.085018 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12156.332387 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11866.260619 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12017.918977 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12156.332387 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11866.260619 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12017.918977 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12156.332387 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11866.260619 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12017.918977 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 42413 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 38788 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 81201 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 42413 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu1.inst 38788 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 81201 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 42413 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu1.inst 38788 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 81201 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 515424 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 469087 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 984511 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 515424 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 469087 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 984511 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 515424 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 469087 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 984511 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 6265245391 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5558732594 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 11823977985 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 6265245391 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5558732594 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 11823977985 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 6265245391 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5558732594 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 11823977985 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8638250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8638250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8638250 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 8638250 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.087393 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.082705 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.085095 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.087393 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.082705 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.085095 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.087393 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.082705 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.085095 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12155.517382 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11850.110095 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12010.000889 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12155.517382 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11850.110095 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12010.000889 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12155.517382 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11850.110095 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12010.000889 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 644131 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.993324 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 21534637 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 644643 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 33.405524 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 43026250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 254.706394 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 257.286930 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.497473 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.502514 # Average percentage of cache occupancy +system.cpu0.dcache.tags.replacements 643555 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.993287 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 21527522 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 644067 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 33.424352 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 43200250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 256.501132 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 255.492155 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.500979 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.499008 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 300 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 192 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 303 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 101674783 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 101674783 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6830201 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 6949651 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13779852 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3598843 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 3661860 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 7260703 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 114028 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 129247 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 243275 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 116593 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 131076 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 247669 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10429044 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 10611511 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 21040555 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10429044 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 10611511 # number of overall hits -system.cpu0.dcache.overall_hits::total 21040555 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 324834 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 424795 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 749629 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1512773 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 1450071 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2962844 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 7425 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 6132 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13557 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2 # number of StoreCondReq misses +system.cpu0.dcache.tags.tag_accesses 101636995 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 101636995 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 7028225 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 6743962 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 13772187 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3755786 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 3505627 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 7261413 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 117401 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 125757 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 243158 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 120052 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 127593 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 247645 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10784011 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 10249589 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 21033600 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10784011 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 10249589 # number of overall hits +system.cpu0.dcache.overall_hits::total 21033600 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 339066 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 409132 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 748198 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1643950 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 1318126 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 2962076 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 7538 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 6009 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 13547 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 4 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::cpu1.data 4 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 6 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1837607 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 1874866 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3712473 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1837607 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 1874866 # number of overall misses -system.cpu0.dcache.overall_misses::total 3712473 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5222562191 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 6193158591 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 11415720782 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 75296679857 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 74371858974 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 149668538831 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 106104748 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 82161747 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 188266495 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 26000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_misses::total 8 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1983016 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 1727258 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3710274 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1983016 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 1727258 # number of overall misses +system.cpu0.dcache.overall_misses::total 3710274 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5448026578 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 5983783737 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 11431810315 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 84542718469 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 64782602600 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 149325321069 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 108200746 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 80635496 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 188836242 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 64501 # number of StoreCondReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 52000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 78000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 80519242048 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 80565017565 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 161084259613 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 80519242048 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 80565017565 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 161084259613 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7155035 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 7374446 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 14529481 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5111616 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 5111931 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 10223547 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 121453 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 135379 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 256832 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 116595 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 131080 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 247675 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12266651 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 12486377 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 24753028 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12266651 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 12486377 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 24753028 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.045399 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.057604 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.051594 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.295948 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.283664 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.289806 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.061135 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.045295 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052785 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000017 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_latency::total 116501 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 89990745047 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 70766386337 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 160757131384 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 89990745047 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 70766386337 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 160757131384 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7367291 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 7153094 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 14520385 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5399736 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 4823753 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 10223489 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 124939 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 131766 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 256705 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 120056 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 127597 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 247653 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12767027 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 11976847 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 24743874 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12767027 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 11976847 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 24743874 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.046023 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.057197 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.051527 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.304450 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.273257 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.289732 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.060333 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.045604 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052773 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000033 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000031 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000024 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.149805 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.150153 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.149981 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.149805 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.150153 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.149981 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16077.634087 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14579.170167 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15228.494071 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 49773.944840 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 51288.425859 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 50515.160039 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14290.201751 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13398.849804 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13887.032161 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 13000 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000032 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.155323 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.144216 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.149947 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.155323 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.144216 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.149947 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16067.746628 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14625.557857 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15279.124396 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 51426.575303 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 49147.503805 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 50412.386809 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14354.039002 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13419.120652 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13939.340223 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 16125.250000 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 43817.444126 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 42971.080368 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 43390.015123 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 43817.444126 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 42971.080368 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 43390.015123 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 36582 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 25832 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 3477 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 293 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10.521139 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 88.163823 # average number of cycles each access was blocked +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 14562.625000 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 45380.745817 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 40970.362469 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 43327.563243 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 45380.745817 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 40970.362469 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 43327.563243 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 36899 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 27773 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 3449 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 287 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10.698463 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 96.770035 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 608494 # number of writebacks -system.cpu0.dcache.writebacks::total 608494 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 143520 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 219714 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 363234 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1385356 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1328479 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 2713835 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 715 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 651 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1366 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1528876 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 1548193 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 3077069 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1528876 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 1548193 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 3077069 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 181314 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 205081 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 386395 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 127417 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 121592 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 249009 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6710 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5481 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12191 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2 # number of StoreCondReq MSHR misses +system.cpu0.dcache.writebacks::writebacks 607936 # number of writebacks +system.cpu0.dcache.writebacks::total 607936 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 150881 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 211427 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 362308 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1507904 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1205220 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 2713124 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 756 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 616 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1372 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1658785 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 1416647 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 3075432 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1658785 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 1416647 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 3075432 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188185 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 197705 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 385890 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 136046 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 112906 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 248952 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6782 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5393 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12175 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 4 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 4 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 6 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 308731 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 326673 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 635404 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 308731 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 326673 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 635404 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2537114094 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2716244009 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5253358103 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5888392200 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 5776496365 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11664888565 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 84437751 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 63633003 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 148070754 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 22000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_misses::total 8 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 324231 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 310611 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 634842 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 324231 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 310611 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 634842 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2625949736 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2626651360 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5252601096 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6397854586 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 5145719244 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11543573830 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 85584754 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 62638004 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 148222758 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 56499 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 44000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 66000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8425506294 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 8492740374 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 16918246668 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8425506294 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 8492740374 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 16918246668 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 92381073251 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 89949254752 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182330328003 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13713085264 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 13059234413 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26772319677 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 100499 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9023804322 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7772370604 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 16796174926 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 9023804322 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7772370604 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 16796174926 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91527403500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90803265751 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182330669251 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13693631022 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 13075286221 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26768917243 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 155750 # number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 155750 # number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 96000 # number of StoreCondReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 96000 # number of StoreCondReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 106094158515 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103008489165 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 209102647680 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.025341 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027810 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026594 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.024927 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023786 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024356 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.055248 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.040486 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047467 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000017 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 105221034522 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103878551972 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 209099586494 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.025543 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027639 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026576 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025195 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023406 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024351 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.054282 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.040929 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047428 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000033 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000031 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000024 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.025168 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.026162 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.025670 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.025168 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.026162 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.025670 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13992.929912 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13244.737489 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13595.823194 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 46213.552352 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 47507.207423 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46845.248826 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12583.867511 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11609.743295 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12145.907145 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000032 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.025396 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025934 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.025657 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.025396 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025934 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.025657 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13954.086330 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13285.710326 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13611.653829 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47027.142187 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 45575.250598 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46368.672796 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12619.397523 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11614.686445 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12174.353840 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 14124.750000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27290.768643 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25997.680782 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26625.968153 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 27290.768643 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25997.680782 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26625.968153 # average overall mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 12562.375000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27831.405146 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25022.844020 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26457.252239 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 27831.405146 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25022.844020 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26457.252239 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1905,324 +2006,366 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 7296861 # Number of BP lookups -system.cpu1.branchPred.condPredicted 5846678 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 347662 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 4742078 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 3857406 # Number of BTB hits +system.cpu1.branchPred.lookups 7298811 # Number of BP lookups +system.cpu1.branchPred.condPredicted 5882879 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 344498 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 4442454 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 3749763 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 81.344212 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 691724 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 35172 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 84.407469 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 676814 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 34330 # Number of incorrect RAS predictions. +system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 25545961 # DTB read hits -system.cpu1.dtb.read_misses 37652 # DTB read misses -system.cpu1.dtb.write_hits 5843070 # DTB write hits -system.cpu1.dtb.write_misses 9833 # DTB write misses -system.cpu1.dtb.flush_tlb 255 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 25485052 # DTB read hits +system.cpu1.dtb.read_misses 36401 # DTB read misses +system.cpu1.dtb.write_hits 5542090 # DTB write hits +system.cpu1.dtb.write_misses 8345 # DTB write misses +system.cpu1.dtb.flush_tlb 512 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 810 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 663 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 5607 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 2149 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 268 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 5452 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 1278 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 241 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 680 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 25583613 # DTB read accesses -system.cpu1.dtb.write_accesses 5852903 # DTB write accesses +system.cpu1.dtb.perms_faults 674 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 25521453 # DTB read accesses +system.cpu1.dtb.write_accesses 5550435 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 31389031 # DTB hits -system.cpu1.dtb.misses 47485 # DTB misses -system.cpu1.dtb.accesses 31436516 # DTB accesses -system.cpu1.itb.inst_hits 5792513 # ITB inst hits -system.cpu1.itb.inst_misses 7242 # ITB inst misses +system.cpu1.dtb.hits 31027142 # DTB hits +system.cpu1.dtb.misses 44746 # DTB misses +system.cpu1.dtb.accesses 31071888 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.itb.inst_hits 5673835 # ITB inst hits +system.cpu1.itb.inst_misses 6882 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 255 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 512 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 810 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 663 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2667 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2658 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1547 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1447 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 5799755 # ITB inst accesses -system.cpu1.itb.hits 5792513 # DTB hits -system.cpu1.itb.misses 7242 # DTB misses -system.cpu1.itb.accesses 5799755 # DTB accesses -system.cpu1.numCycles 235437063 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 5680717 # ITB inst accesses +system.cpu1.itb.hits 5673835 # DTB hits +system.cpu1.itb.misses 6882 # DTB misses +system.cpu1.itb.accesses 5680717 # DTB accesses +system.cpu1.numCycles 236975623 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 14594322 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 46143705 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 7296861 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 4549130 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 10187153 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 2325105 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 84075 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 48390355 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 1006 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 1773 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 50802 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 1299927 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 134 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 5790405 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 352119 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3045 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 76215873 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.749895 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.108619 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 14429172 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 45037398 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 7298811 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 4426577 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 9907364 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 2282600 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 82705 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 49394158 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 1073 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 1935 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 44118 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 1230431 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 170 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 5671812 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 352198 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3013 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 76664255 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.724522 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.076690 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 66035998 86.64% 86.64% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 646269 0.85% 87.49% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 866115 1.14% 88.63% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1144603 1.50% 90.13% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1038380 1.36% 91.49% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 570616 0.75% 92.24% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1298592 1.70% 93.94% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 378941 0.50% 94.44% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 4236359 5.56% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 66765211 87.09% 87.09% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 630389 0.82% 87.91% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 841220 1.10% 89.01% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1125492 1.47% 90.48% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 998152 1.30% 91.78% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 547084 0.71% 92.49% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1279264 1.67% 94.16% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 367549 0.48% 94.64% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 4109894 5.36% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 76215873 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.030993 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.195992 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 15595502 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 49311936 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 9258524 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 522439 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1525385 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 986467 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 83299 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 54522655 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 277301 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1525385 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 16476975 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 19655955 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 26515105 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 8823591 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 3216801 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 52024243 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 13429 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 607553 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 2083322 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 488 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 54254654 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 237368382 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 219812592 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 5012 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 40368418 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 13886236 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 416636 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 371803 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 6618695 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 10010762 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 6654363 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 928897 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1221940 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 48420965 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1005597 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 62096685 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 94311 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 9477685 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 23931706 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 245448 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 76215873 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.814747 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.522121 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 76664255 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.030800 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.190051 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 15533095 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 50132740 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 8857878 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 647971 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1490380 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 961231 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 85259 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 52933701 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 285543 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1490380 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 16375879 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 19322833 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 27622785 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 8617835 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 3232383 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 50467558 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 173 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 596710 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 2000524 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 626 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 52901652 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 233465152 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 213426027 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 5240 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 39335356 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 13566296 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 577962 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 535418 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 6495060 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 9746539 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 6334911 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 894923 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1137674 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 46958643 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 959615 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 60863950 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 85447 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 9232783 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 23424311 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 229955 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 76664255 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.793903 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.504568 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 53862159 70.67% 70.67% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 6987914 9.17% 79.84% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 3609115 4.74% 84.57% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3073312 4.03% 88.61% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 6185840 8.12% 96.72% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1415029 1.86% 98.58% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 789705 1.04% 99.62% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 228522 0.30% 99.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 64277 0.08% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 54480181 71.06% 71.06% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 7304682 9.53% 80.59% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 3460273 4.51% 85.11% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 2866704 3.74% 88.84% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 6125054 7.99% 96.83% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1372858 1.79% 98.62% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 769548 1.00% 99.63% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 222824 0.29% 99.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 62131 0.08% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 76215873 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 76664255 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 30122 0.69% 0.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 4 0.00% 0.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4155854 94.74% 95.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 200598 4.57% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 29010 0.66% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 4 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 4179738 94.96% 95.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 192807 4.38% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 197857 0.32% 0.32% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 29468242 47.46% 47.77% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 46687 0.08% 47.85% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.85% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.85% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.85% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.85% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.85% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.85% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 11 0.00% 47.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 9 0.00% 47.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 846 0.00% 47.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 47.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.85% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 26218549 42.22% 90.07% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 6164475 9.93% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 12555 0.02% 0.02% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 28808011 47.33% 47.35% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 45980 0.08% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 12 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 867 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 26140692 42.95% 90.38% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 5855817 9.62% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 62096685 # Type of FU issued -system.cpu1.iq.rate 0.263751 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 4386578 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.070641 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 204926211 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 58913069 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 43552448 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 11222 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 6050 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 4957 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 66279422 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 5984 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 320383 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 60863950 # Type of FU issued +system.cpu1.iq.rate 0.256836 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 4401559 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.072318 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 202912608 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 57159577 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 42178137 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 11121 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 6181 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 5062 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 65247126 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 5828 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 310626 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2041284 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 2958 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 15466 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 770955 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 1995012 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 2960 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 15279 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 746422 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 16877302 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 331906 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 17045290 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 332871 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1525385 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 14957873 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 224833 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 49549209 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 95185 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 10010762 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 6654363 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 720304 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 50705 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 4281 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 15466 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 171203 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 135670 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 306873 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 61058870 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 25897367 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1037815 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 1490380 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 14881654 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 224199 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 48035025 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 95776 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 9746539 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 6334911 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 685011 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 49572 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 5137 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 15279 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 166909 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 134382 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 301291 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 59839107 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 25823960 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1024843 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 122647 # number of nop insts executed -system.cpu1.iew.exec_refs 32008147 # number of memory reference insts executed -system.cpu1.iew.exec_branches 5821795 # Number of branches executed -system.cpu1.iew.exec_stores 6110780 # Number of stores executed -system.cpu1.iew.exec_rate 0.259343 # Inst execution rate -system.cpu1.iew.wb_sent 60589807 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 43557405 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 24211075 # num instructions producing a value -system.cpu1.iew.wb_consumers 44594441 # num instructions consuming a value +system.cpu1.iew.exec_nop 116767 # number of nop insts executed +system.cpu1.iew.exec_refs 31629946 # number of memory reference insts executed +system.cpu1.iew.exec_branches 5849908 # Number of branches executed +system.cpu1.iew.exec_stores 5805986 # Number of stores executed +system.cpu1.iew.exec_rate 0.252512 # Inst execution rate +system.cpu1.iew.wb_sent 59372558 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 42183199 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 23508004 # num instructions producing a value +system.cpu1.iew.wb_consumers 42759548 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.185007 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.542917 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.178006 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.549772 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 9363446 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 760149 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 265641 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 74690488 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.532256 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.520816 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 9155270 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 729660 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 260542 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 75173875 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.511996 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.483358 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 60561931 81.08% 81.08% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 6932594 9.28% 90.37% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1961063 2.63% 92.99% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1092193 1.46% 94.45% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1024970 1.37% 95.83% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 536622 0.72% 96.54% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 713910 0.96% 97.50% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 380912 0.51% 98.01% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1486293 1.99% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 60919870 81.04% 81.04% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 7446257 9.91% 90.94% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1922213 2.56% 93.50% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1068282 1.42% 94.92% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 820469 1.09% 96.01% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 498258 0.66% 96.68% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 699309 0.93% 97.61% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 369578 0.49% 98.10% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1429639 1.90% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 74690488 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 31194382 # Number of instructions committed -system.cpu1.commit.committedOps 39754477 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 75173875 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 30400176 # Number of instructions committed +system.cpu1.commit.committedOps 38488707 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 13852886 # Number of memory references committed -system.cpu1.commit.loads 7969478 # Number of loads committed -system.cpu1.commit.membars 200339 # Number of memory barriers committed -system.cpu1.commit.branches 5070949 # Number of branches committed -system.cpu1.commit.fp_insts 4906 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 35178713 # Number of committed integer instructions. -system.cpu1.commit.function_calls 493679 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1486293 # number cycles where commit BW limit reached +system.cpu1.commit.refs 13340016 # Number of memory references committed +system.cpu1.commit.loads 7751527 # Number of loads committed +system.cpu1.commit.membars 193715 # Number of memory barriers committed +system.cpu1.commit.branches 5124652 # Number of branches committed +system.cpu1.commit.fp_insts 5013 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 34222153 # Number of committed integer instructions. +system.cpu1.commit.function_calls 482564 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1429639 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 121392021 # The number of ROB reads -system.cpu1.rob.rob_writes 99804752 # The number of ROB writes -system.cpu1.timesIdled 864703 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 159221190 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 2318646914 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 31111502 # Number of Instructions Simulated -system.cpu1.committedOps 39671597 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 31111502 # Number of Instructions Simulated -system.cpu1.cpi 7.567525 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 7.567525 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.132144 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.132144 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 276724007 # number of integer regfile reads -system.cpu1.int_regfile_writes 44911737 # number of integer regfile writes -system.cpu1.fp_regfile_reads 22398 # number of floating regfile reads -system.cpu1.fp_regfile_writes 19708 # number of floating regfile writes -system.cpu1.misc_regfile_reads 15283998 # number of misc regfile reads -system.cpu1.misc_regfile_writes 429459 # number of misc regfile writes +system.cpu1.rob.rob_reads 120517356 # The number of ROB reads +system.cpu1.rob.rob_writes 96821590 # The number of ROB writes +system.cpu1.timesIdled 866519 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 160311368 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 2319089759 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 30321678 # Number of Instructions Simulated +system.cpu1.committedOps 38410209 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 30321678 # Number of Instructions Simulated +system.cpu1.cpi 7.815386 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 7.815386 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.127953 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.127953 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 271574951 # number of integer regfile reads +system.cpu1.int_regfile_writes 43566618 # number of integer regfile writes +system.cpu1.fp_regfile_reads 45165 # number of floating regfile reads +system.cpu1.fp_regfile_writes 42266 # number of floating regfile writes +system.cpu1.misc_regfile_reads 132802747 # number of misc regfile reads +system.cpu1.misc_regfile_writes 590318 # number of misc regfile writes system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. @@ -2239,17 +2382,17 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1518454987022 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1518454987022 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1518454987022 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1518454987022 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1518508564766 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1518508564766 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1518508564766 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1518508564766 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 83063 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 83065 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini index 6f15742b0..1d8001986 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini @@ -14,6 +14,7 @@ children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l atags_addr=256 boot_loader=/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain dtb_filename= @@ -22,9 +23,16 @@ enable_context_switch_stats_dump=false eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 +have_generic_timer=false +have_large_asid_64=false +have_lpae=false +have_security=false +have_virtualization=false +highest_el_is_64=false init_param=0 kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 +load_offset=0 machine_type=RealView_PBX mem_mode=timing mem_ranges=0:134217727 @@ -33,7 +41,9 @@ multi_proc=true num_work_ids=16 panic_on_oops=true panic_on_panic=true +phys_addr_range_64=40 readfile=tests/halt.sh +reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -86,19 +96,21 @@ voltage_domain=system.voltage_domain [system.cpu0] type=TimingSimpleCPU -children=dcache dtb icache interrupts isa itb tracer +children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu0.dstage2_mmu dtb=system.cpu0.dtb eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu0.interrupts isa=system.cpu0.isa +istage2_mmu=system.cpu0.istage2_mmu itb=system.cpu0.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -150,10 +162,35 @@ hit_latency=2 sequential_access=false size=32768 +[system.cpu0.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb +tlb=system.cpu0.dtb + +[system.cpu0.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu0.dstage2_mmu.stage2_tlb.walker + +[system.cpu0.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[5] + [system.cpu0.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu0.dtb.walker @@ -161,6 +198,7 @@ walker=system.cpu0.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[3] @@ -208,24 +246,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu0.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb +tlb=system.cpu0.itb + +[system.cpu0.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu0.istage2_mmu.stage2_tlb.walker + +[system.cpu0.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[4] [system.cpu0.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu0.itb.walker @@ -233,6 +307,7 @@ walker=system.cpu0.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[2] @@ -243,19 +318,21 @@ eventq_index=0 [system.cpu1] type=TimingSimpleCPU -children=dtb isa itb tracer +children=dstage2_mmu dtb isa istage2_mmu itb tracer checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu1.dstage2_mmu dtb=system.cpu1.dtb eventq_index=0 function_trace=false function_trace_start=0 interrupts=Null isa=system.cpu1.isa +istage2_mmu=system.cpu1.istage2_mmu itb=system.cpu1.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -270,10 +347,34 @@ system=system tracer=system.cpu1.tracer workload= +[system.cpu1.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb +tlb=system.cpu1.dtb + +[system.cpu1.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu1.dstage2_mmu.stage2_tlb.walker + +[system.cpu1.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system + [system.cpu1.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu1.dtb.walker @@ -281,6 +382,7 @@ walker=system.cpu1.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system @@ -288,24 +390,59 @@ sys=system type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu1.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb +tlb=system.cpu1.itb + +[system.cpu1.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu1.istage2_mmu.stage2_tlb.walker + +[system.cpu1.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system [system.cpu1.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu1.itb.walker @@ -313,6 +450,7 @@ walker=system.cpu1.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system @@ -951,7 +1089,7 @@ system=system use_default_range=false width=8 master=system.l2c.cpu_side -slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port +slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port [system.vncserver] type=VncServer diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr index 4dfb66c84..fdcb49ed7 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr @@ -11,8 +11,42 @@ warn: instruction 'mcr dccimvac' unimplemented warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented warn: LCD dual screen mode not supported -warn: instruction 'mcr icialluis' unimplemented -warn: instruction 'mcr bpiallis' unimplemented +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout index 25848b995..16dc9f3ee 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout @@ -1,8 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 23 2014 00:31:08 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 19:11:44 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-timing -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-timing Global frequency set at 1000000000000 ticks per second + 0: system.cpu0.isa: ISA system set to: 0x6f57400 0x6f57400 + 0: system.cpu1.isa: ISA system set to: 0x6f57400 0x6f57400 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt index e79723ba6..b41d3a6bf 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt @@ -1,81 +1,81 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.629717 # Number of seconds simulated -sim_ticks 2629717216500 # Number of ticks simulated -final_tick 2629717216500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.629734 # Number of seconds simulated +sim_ticks 2629733911500 # Number of ticks simulated +final_tick 2629733911500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 592417 # Simulator instruction rate (inst/s) -host_op_rate 753843 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 25873243563 # Simulator tick rate (ticks/s) -host_mem_usage 401372 # Number of bytes of host memory used -host_seconds 101.64 # Real time elapsed on the host -sim_insts 60212334 # Number of instructions simulated -sim_ops 76619433 # Number of ops (including micro ops) simulated +host_inst_rate 461706 # Simulator instruction rate (inst/s) +host_op_rate 587514 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 20164609948 # Simulator tick rate (ticks/s) +host_mem_usage 422284 # Number of bytes of host memory used +host_seconds 130.41 # Real time elapsed on the host +sim_insts 60212552 # Number of instructions simulated +sim_ops 76619667 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 298016 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4661584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 300040 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4644312 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 406404 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4399060 # Number of bytes read from this memory -system.physmem.bytes_read::total 134021512 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 298016 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 406404 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 704420 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3689984 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1527272 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1489008 # Number of bytes written to this memory -system.physmem.bytes_written::total 6706264 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 404420 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4416276 # Number of bytes read from this memory +system.physmem.bytes_read::total 134021496 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 300040 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 404420 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 704460 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3689920 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1526984 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1489296 # Number of bytes written to this memory +system.physmem.bytes_written::total 6706200 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15532032 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 10859 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 72871 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 10900 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 72603 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6366 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 68770 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15690901 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57656 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 381818 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 372252 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811726 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47250805 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu1.inst 6335 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 69039 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15690912 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57655 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 381746 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 372324 # Number of write requests responded to by this memory +system.physmem.num_writes::total 811725 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47250505 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 113326 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1772656 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 114095 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1766077 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 24 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 154543 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1672826 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50964230 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 113326 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 154543 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 267869 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1403187 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 580774 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 566224 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2550184 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1403187 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47250805 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 153787 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1679362 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50963900 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 114095 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 153787 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 267883 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1403153 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 580661 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 566330 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2550144 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1403153 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47250505 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 113326 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2353430 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 114095 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2346738 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 24 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 154543 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2239050 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53514414 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15690901 # Number of read requests accepted -system.physmem.writeReqs 811726 # Number of write requests accepted -system.physmem.readBursts 15690901 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 811726 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1004215808 # Total number of bytes read from DRAM +system.physmem.bw_total::cpu1.inst 153787 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2245692 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53514044 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15690912 # Number of read requests accepted +system.physmem.writeReqs 811725 # Number of write requests accepted +system.physmem.readBursts 15690912 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 811725 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1004216512 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 1856 # Total number of bytes read from write queue -system.physmem.bytesWritten 6837952 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 134021512 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6706264 # Total written bytes from the system interface side +system.physmem.bytesWritten 6837440 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 134021496 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6706200 # Total written bytes from the system interface side system.physmem.servicedByWrQ 29 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 704883 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4518 # Number of requests that are neither read nor write +system.physmem.mergedWrBursts 704890 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4516 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 980392 # Per bank write bursts system.physmem.perBankRdBursts::1 980205 # Per bank write bursts system.physmem.perBankRdBursts::2 980222 # Per bank write bursts @@ -88,60 +88,60 @@ system.physmem.perBankRdBursts::8 980615 # Pe system.physmem.perBankRdBursts::9 980431 # Per bank write bursts system.physmem.perBankRdBursts::10 979815 # Per bank write bursts system.physmem.perBankRdBursts::11 979558 # Per bank write bursts -system.physmem.perBankRdBursts::12 980154 # Per bank write bursts +system.physmem.perBankRdBursts::12 980153 # Per bank write bursts system.physmem.perBankRdBursts::13 980093 # Per bank write bursts -system.physmem.perBankRdBursts::14 980155 # Per bank write bursts +system.physmem.perBankRdBursts::14 980167 # Per bank write bursts system.physmem.perBankRdBursts::15 980109 # Per bank write bursts -system.physmem.perBankWrBursts::0 6731 # Per bank write bursts -system.physmem.perBankWrBursts::1 6599 # Per bank write bursts -system.physmem.perBankWrBursts::2 6610 # Per bank write bursts -system.physmem.perBankWrBursts::3 6672 # Per bank write bursts -system.physmem.perBankWrBursts::4 6746 # Per bank write bursts +system.physmem.perBankWrBursts::0 6735 # Per bank write bursts +system.physmem.perBankWrBursts::1 6596 # Per bank write bursts +system.physmem.perBankWrBursts::2 6612 # Per bank write bursts +system.physmem.perBankWrBursts::3 6671 # Per bank write bursts +system.physmem.perBankWrBursts::4 6747 # Per bank write bursts system.physmem.perBankWrBursts::5 7052 # Per bank write bursts -system.physmem.perBankWrBursts::6 7033 # Per bank write bursts -system.physmem.perBankWrBursts::7 6881 # Per bank write bursts -system.physmem.perBankWrBursts::8 7002 # Per bank write bursts -system.physmem.perBankWrBursts::9 6827 # Per bank write bursts -system.physmem.perBankWrBursts::10 6323 # Per bank write bursts -system.physmem.perBankWrBursts::11 6122 # Per bank write bursts -system.physmem.perBankWrBursts::12 6612 # Per bank write bursts -system.physmem.perBankWrBursts::13 6399 # Per bank write bursts +system.physmem.perBankWrBursts::6 7031 # Per bank write bursts +system.physmem.perBankWrBursts::7 6880 # Per bank write bursts +system.physmem.perBankWrBursts::8 6999 # Per bank write bursts +system.physmem.perBankWrBursts::9 6828 # Per bank write bursts +system.physmem.perBankWrBursts::10 6320 # Per bank write bursts +system.physmem.perBankWrBursts::11 6125 # Per bank write bursts +system.physmem.perBankWrBursts::12 6609 # Per bank write bursts +system.physmem.perBankWrBursts::13 6397 # Per bank write bursts system.physmem.perBankWrBursts::14 6618 # Per bank write bursts -system.physmem.perBankWrBursts::15 6616 # Per bank write bursts +system.physmem.perBankWrBursts::15 6615 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2629712785000 # Total gap between requests +system.physmem.totGap 2629729480000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 6706 # Read request sizes (log2) +system.physmem.readPktSize::2 6718 # Read request sizes (log2) system.physmem.readPktSize::3 15532032 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 152163 # Read request sizes (log2) +system.physmem.readPktSize::6 152162 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 754070 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 57656 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1290849 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1134741 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1135188 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3791353 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2690884 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2690157 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2706986 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 51561 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 56279 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 20477 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 20472 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 20444 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 20380 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 20364 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 20351 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 20341 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 45 # What read queue length does an incoming req see +system.physmem.writePktSize::6 57655 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1274921 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1118631 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1118848 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3789956 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2706257 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2705513 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2723130 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 52826 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 57874 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 20508 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 20484 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 20456 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 20388 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 20359 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 20349 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 20334 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 49 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -157,28 +157,28 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 5039 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5010 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4995 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4971 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 5032 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4992 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4975 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 4959 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4947 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4931 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4918 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4896 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4879 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4863 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4844 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4825 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4815 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4801 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4786 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4750 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4736 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4719 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4708 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4689 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4942 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4932 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4917 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4895 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4877 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4860 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4846 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4821 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4790 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4747 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4732 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4718 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4704 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4687 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see @@ -189,299 +189,317 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 90454 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 11177.544033 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 1030.436917 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 16744.733089 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-71 23393 25.86% 25.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-135 14737 16.29% 42.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-199 2929 3.24% 45.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-263 2185 2.42% 47.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-327 1403 1.55% 49.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-391 1153 1.27% 50.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-455 940 1.04% 51.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-519 1175 1.30% 52.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-583 610 0.67% 53.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-647 557 0.62% 54.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-711 555 0.61% 54.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-775 601 0.66% 55.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-839 293 0.32% 55.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-903 323 0.36% 56.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-967 207 0.23% 56.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1031 643 0.71% 57.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1095 173 0.19% 57.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1159 141 0.16% 57.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1223 139 0.15% 57.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1287 211 0.23% 57.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1351 108 0.12% 58.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1415 2249 2.49% 60.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1479 108 0.12% 60.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1543 135 0.15% 60.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1607 71 0.08% 60.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1671 48 0.05% 60.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1735 33 0.04% 60.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1799 98 0.11% 61.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1863 34 0.04% 61.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1927 27 0.03% 61.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1991 23 0.03% 61.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2055 231 0.26% 61.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2119 24 0.03% 61.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2183 27 0.03% 61.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2247 30 0.03% 61.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2311 143 0.16% 61.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2375 12 0.01% 61.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2439 18 0.02% 61.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2503 17 0.02% 61.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2567 86 0.10% 61.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2631 22 0.02% 61.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2695 12 0.01% 61.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2759 15 0.02% 61.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2823 205 0.23% 62.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2887 13 0.01% 62.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2951 20 0.02% 62.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3015 10 0.01% 62.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3079 404 0.45% 62.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3143 18 0.02% 62.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3207 8 0.01% 62.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3271 8 0.01% 62.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3335 21 0.02% 62.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3399 11 0.01% 62.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3463 14 0.02% 62.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3527 16 0.02% 62.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3591 82 0.09% 62.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3655 9 0.01% 62.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3719 15 0.02% 62.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3783 35 0.04% 62.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3847 129 0.14% 62.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3911 12 0.01% 62.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3975 9 0.01% 62.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4039 7 0.01% 63.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4103 283 0.31% 63.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4167 7 0.01% 63.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4231 5 0.01% 63.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4295 10 0.01% 63.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4359 6 0.01% 63.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4423 5 0.01% 63.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4487 11 0.01% 63.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4551 8 0.01% 63.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4615 271 0.30% 63.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4679 14 0.02% 63.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4743 4 0.00% 63.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4807 9 0.01% 63.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4871 136 0.15% 63.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4935 4 0.00% 63.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4999 11 0.01% 63.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5063 11 0.01% 63.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5127 341 0.38% 64.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5191 2 0.00% 64.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5255 14 0.02% 64.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5319 4 0.00% 64.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5383 205 0.23% 64.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5447 168 0.19% 64.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5511 59 0.07% 64.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5639 3 0.00% 64.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5703 1 0.00% 64.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5895 126 0.14% 64.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6151 267 0.30% 65.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6407 256 0.28% 65.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6535 2 0.00% 65.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6599 1 0.00% 65.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6663 5 0.01% 65.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6919 65 0.07% 65.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7175 454 0.50% 66.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7303 1 0.00% 66.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7431 9 0.01% 66.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7559 2 0.00% 66.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7687 192 0.21% 66.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7943 2 0.00% 66.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8199 261 0.29% 66.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8711 193 0.21% 66.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8967 9 0.01% 66.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9223 455 0.50% 67.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9344-9351 1 0.00% 67.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9479 64 0.07% 67.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9735 5 0.01% 67.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9991 257 0.28% 67.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10176-10183 1 0.00% 67.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10247 265 0.29% 67.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10503 124 0.14% 68.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10759 4 0.00% 68.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11015 195 0.22% 68.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11072-11079 1 0.00% 68.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11200-11207 1 0.00% 68.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11271 336 0.37% 68.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11527 123 0.14% 68.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11783 266 0.29% 69.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12295 267 0.30% 69.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12551 121 0.13% 69.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12807 75 0.08% 69.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13063 4 0.00% 69.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13319 387 0.43% 70.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13575 197 0.22% 70.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13831 78 0.09% 70.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13888-13895 1 0.00% 70.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14087 129 0.14% 70.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14343 206 0.23% 70.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14599 65 0.07% 70.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14855 65 0.07% 70.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15111 71 0.08% 70.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15232-15239 1 0.00% 70.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15367 455 0.50% 71.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15424-15431 1 0.00% 71.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15623 66 0.07% 71.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15879 131 0.14% 71.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16135 128 0.14% 71.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16391 401 0.44% 72.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16647 130 0.14% 72.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16903 129 0.14% 72.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17088-17095 1 0.00% 72.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17159 68 0.08% 72.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17415 460 0.51% 73.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17600-17607 1 0.00% 73.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17671 71 0.08% 73.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17927 66 0.07% 73.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18183 64 0.07% 73.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18439 208 0.23% 73.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18695 128 0.14% 73.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18944-18951 77 0.09% 73.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19207 196 0.22% 74.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19328-19335 1 0.00% 74.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19463 386 0.43% 74.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19719 3 0.00% 74.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19968-19975 72 0.08% 74.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20231 120 0.13% 74.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20487 270 0.30% 74.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-20999 265 0.29% 75.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21248-21255 123 0.14% 75.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21511 334 0.37% 75.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21767 195 0.22% 75.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21824-21831 1 0.00% 75.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22023 3 0.00% 76.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22279 127 0.14% 76.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22535 264 0.29% 76.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22720-22727 1 0.00% 76.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22791 255 0.28% 76.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23040-23047 5 0.01% 76.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23296-23303 65 0.07% 76.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23559 452 0.50% 77.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23808-23815 9 0.01% 77.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24071 192 0.21% 77.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24327 3 0.00% 77.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24583 259 0.29% 77.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24839 1 0.00% 77.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25088-25095 193 0.21% 78.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25344-25351 7 0.01% 78.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25607 454 0.50% 78.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25856-25863 66 0.07% 78.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26112-26119 5 0.01% 78.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26375 256 0.28% 78.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26631 266 0.29% 79.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26880-26887 124 0.14% 79.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27143 2 0.00% 79.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27399 195 0.22% 79.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27655 332 0.37% 79.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27911 123 0.14% 80.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28160-28167 266 0.29% 80.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28679 267 0.30% 80.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28935 122 0.13% 80.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29120-29127 1 0.00% 80.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29191 74 0.08% 80.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29447 4 0.00% 80.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29703 387 0.43% 81.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-29959 194 0.21% 81.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30208-30215 77 0.09% 81.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30272-30279 1 0.00% 81.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30471 128 0.14% 81.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30592-30599 1 0.00% 81.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30727 205 0.23% 81.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-30983 64 0.07% 82.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31239 66 0.07% 82.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31488-31495 71 0.08% 82.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31751 457 0.51% 82.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32000-32007 65 0.07% 82.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32256-32263 130 0.14% 82.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32512-32519 128 0.14% 83.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32775 400 0.44% 83.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33031 128 0.14% 83.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33287 135 0.15% 83.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33543 65 0.07% 83.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33799 456 0.50% 84.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34048-34055 71 0.08% 84.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34304-34311 66 0.07% 84.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34560-34567 64 0.07% 84.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34823 205 0.23% 84.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34944-34951 1 0.00% 84.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35072-35079 128 0.14% 84.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35328-35335 76 0.08% 85.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35584-35591 194 0.21% 85.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35847 386 0.43% 85.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36096-36103 3 0.00% 85.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36352-36359 73 0.08% 85.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36608-36615 121 0.13% 85.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36864-36871 265 0.29% 86.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37376-37383 265 0.29% 86.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37632-37639 123 0.14% 86.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37895 333 0.37% 86.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38144-38151 195 0.22% 87.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38400-38407 2 0.00% 87.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38656-38663 125 0.14% 87.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38912-38919 265 0.29% 87.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39168-39175 256 0.28% 87.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39424-39431 5 0.01% 87.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39680-39687 65 0.07% 87.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39936-39943 452 0.50% 88.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40192-40199 7 0.01% 88.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40448-40455 192 0.21% 88.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40960-40967 259 0.29% 88.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41216-41223 3 0.00% 88.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41472-41479 192 0.21% 89.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41728-41735 9 0.01% 89.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-41991 452 0.50% 89.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42240-42247 64 0.07% 89.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42496-42503 5 0.01% 89.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42752-42759 255 0.28% 90.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42816-42823 1 0.00% 90.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43008-43015 264 0.29% 90.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43264-43271 126 0.14% 90.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43520-43527 3 0.00% 90.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43712-43719 1 0.00% 90.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43776-43783 194 0.21% 90.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44032-44039 335 0.37% 91.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44288-44295 123 0.14% 91.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44544-44551 264 0.29% 91.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45056-45063 264 0.29% 91.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45312-45319 120 0.13% 91.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45568-45575 72 0.08% 92.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45824-45831 4 0.00% 92.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46087 385 0.43% 92.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46336-46343 194 0.21% 92.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46592-46599 76 0.08% 92.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46848-46855 128 0.14% 92.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47104-47111 209 0.23% 93.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47360-47367 65 0.07% 93.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47616-47623 67 0.07% 93.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47744-47751 1 0.00% 93.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47872-47879 73 0.08% 93.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47936-47943 2 0.00% 93.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48135 459 0.51% 93.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48256-48263 3 0.00% 93.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48384-48391 69 0.08% 93.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48448-48455 1 0.00% 93.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48640-48647 129 0.14% 94.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48903 129 0.14% 94.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48960-48967 3 0.00% 94.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49024-49031 1 0.00% 94.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49088-49095 3 0.00% 94.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49159 5220 5.77% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 90454 # Bytes accessed per row activation -system.physmem.totQLat 377144928750 # Total ticks spent queuing -system.physmem.totMemAccLat 474552728750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 78454360000 # Total ticks spent in databus transfers -system.physmem.totBankLat 18953440000 # Total ticks spent accessing banks -system.physmem.avgQLat 24035.94 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1207.93 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::samples 90412 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 11182.734327 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 1029.544171 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 16746.961445 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 23519 26.01% 26.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 14711 16.27% 42.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 2935 3.25% 45.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 2119 2.34% 47.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 1367 1.51% 49.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 1185 1.31% 50.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 943 1.04% 51.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 1073 1.19% 52.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 614 0.68% 53.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 515 0.57% 54.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 541 0.60% 54.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-775 575 0.64% 55.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-839 297 0.33% 55.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-903 299 0.33% 56.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 230 0.25% 56.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 594 0.66% 56.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 170 0.19% 57.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1159 148 0.16% 57.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1223 128 0.14% 57.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1287 277 0.31% 57.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1351 134 0.15% 57.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1415 2231 2.47% 60.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1479 108 0.12% 60.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1543 229 0.25% 60.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1607 52 0.06% 60.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1671 35 0.04% 60.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1735 49 0.05% 60.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1799 107 0.12% 61.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1863 29 0.03% 61.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1927 27 0.03% 61.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1991 27 0.03% 61.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2055 349 0.39% 61.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2119 23 0.03% 61.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2183 21 0.02% 61.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2247 26 0.03% 61.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2311 89 0.10% 61.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2375 16 0.02% 61.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2439 22 0.02% 61.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2503 22 0.02% 61.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2567 90 0.10% 61.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2631 13 0.01% 61.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2695 10 0.01% 61.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2759 21 0.02% 61.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2823 65 0.07% 61.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2887 13 0.01% 61.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2951 15 0.02% 62.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3015 14 0.02% 62.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3079 339 0.37% 62.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3143 16 0.02% 62.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3207 12 0.01% 62.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3271 10 0.01% 62.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3335 148 0.16% 62.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3399 5 0.01% 62.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3463 16 0.02% 62.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3527 11 0.01% 62.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3591 140 0.15% 62.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3655 10 0.01% 62.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3719 13 0.01% 62.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3783 37 0.04% 62.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3847 139 0.15% 63.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3911 14 0.02% 63.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3975 9 0.01% 63.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4039 13 0.01% 63.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4103 357 0.39% 63.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4167 7 0.01% 63.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4231 6 0.01% 63.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4295 7 0.01% 63.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4359 77 0.09% 63.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4423 6 0.01% 63.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4487 8 0.01% 63.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4551 10 0.01% 63.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4615 79 0.09% 63.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4679 8 0.01% 63.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4743 9 0.01% 63.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4807 6 0.01% 63.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4871 18 0.02% 63.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4935 6 0.01% 63.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4999 10 0.01% 63.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5063 10 0.01% 63.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5127 276 0.31% 64.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5191 5 0.01% 64.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5255 9 0.01% 64.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5319 8 0.01% 64.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5383 76 0.08% 64.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5447 164 0.18% 64.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5511 59 0.07% 64.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5575 1 0.00% 64.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5639 301 0.33% 64.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5703 1 0.00% 64.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5895 129 0.14% 64.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5959 1 0.00% 64.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6151 456 0.50% 65.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6407 69 0.08% 65.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6535 2 0.00% 65.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6599 1 0.00% 65.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6663 68 0.08% 65.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6791 1 0.00% 65.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6919 2 0.00% 65.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7175 268 0.30% 65.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7431 68 0.08% 65.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7687 129 0.14% 66.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7943 66 0.07% 66.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8199 512 0.57% 66.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8455 67 0.07% 66.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8711 130 0.14% 66.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8967 68 0.08% 66.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9223 266 0.29% 67.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9479 2 0.00% 67.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9735 69 0.08% 67.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9991 72 0.08% 67.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10048-10055 1 0.00% 67.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10247 456 0.50% 67.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10503 130 0.14% 68.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10759 301 0.33% 68.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11015 64 0.07% 68.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11271 271 0.30% 68.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11527 6 0.01% 68.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11584-11591 1 0.00% 68.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11783 73 0.08% 68.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11840-11847 1 0.00% 68.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12039 68 0.08% 68.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12295 341 0.38% 69.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12480-12487 2 0.00% 69.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12551 127 0.14% 69.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12672-12679 1 0.00% 69.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12807 128 0.14% 69.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13063 133 0.15% 69.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13319 322 0.36% 70.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13575 57 0.06% 70.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13831 77 0.09% 70.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14087 70 0.08% 70.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14343 324 0.36% 70.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14400-14407 1 0.00% 70.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14599 72 0.08% 70.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14855 126 0.14% 70.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15111 141 0.16% 71.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15367 387 0.43% 71.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15623 74 0.08% 71.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15879 1 0.00% 71.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16135 66 0.07% 71.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16391 651 0.72% 72.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16647 66 0.07% 72.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16960-16967 1 0.00% 72.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17024-17031 1 0.00% 72.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17159 72 0.08% 72.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17415 390 0.43% 72.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17671 142 0.16% 73.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17927 127 0.14% 73.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18183 70 0.08% 73.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18240-18247 1 0.00% 73.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18439 321 0.36% 73.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18496-18503 1 0.00% 73.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18624-18631 1 0.00% 73.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18688-18695 68 0.08% 73.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18944-18951 77 0.09% 73.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19072-19079 1 0.00% 73.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19207 58 0.06% 73.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19463 323 0.36% 74.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19648-19655 1 0.00% 74.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19712-19719 131 0.14% 74.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19968-19975 131 0.14% 74.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20224-20231 129 0.14% 74.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20487 345 0.38% 75.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20736-20743 68 0.08% 75.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20992-20999 71 0.08% 75.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21248-21255 5 0.01% 75.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21440-21447 1 0.00% 75.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21511 267 0.30% 75.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21760-21767 64 0.07% 75.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22016-22023 302 0.33% 75.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22272-22279 133 0.15% 76.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22535 456 0.50% 76.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22784-22791 69 0.08% 76.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23040-23047 68 0.08% 76.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23559 265 0.29% 77.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23808-23815 68 0.08% 77.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24064-24071 131 0.14% 77.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24327 65 0.07% 77.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24384-24391 1 0.00% 77.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24583 514 0.57% 77.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24832-24839 67 0.07% 78.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25088-25095 129 0.14% 78.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25344-25351 67 0.07% 78.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25472-25479 1 0.00% 78.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25607 262 0.29% 78.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25792-25799 1 0.00% 78.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26112-26119 69 0.08% 78.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26375 69 0.08% 78.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26631 455 0.50% 79.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26816-26823 1 0.00% 79.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26880-26887 130 0.14% 79.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26944-26951 1 0.00% 79.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27136-27143 301 0.33% 79.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27399 64 0.07% 79.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27584-27591 1 0.00% 79.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27655 267 0.30% 80.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27840-27847 1 0.00% 80.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27911 4 0.00% 80.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28160-28167 73 0.08% 80.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28423 69 0.08% 80.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28544-28551 1 0.00% 80.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28608-28615 1 0.00% 80.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28679 341 0.38% 80.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28935 128 0.14% 80.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29191 130 0.14% 80.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29447 132 0.15% 80.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29504-29511 1 0.00% 80.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29703 322 0.36% 81.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29760-29767 1 0.00% 81.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-29959 57 0.06% 81.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30215 76 0.08% 81.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30272-30279 2 0.00% 81.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30471 68 0.08% 81.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30727 322 0.36% 81.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-30983 72 0.08% 82.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31239 126 0.14% 82.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31495 141 0.16% 82.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31616-31623 1 0.00% 82.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31751 387 0.43% 82.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32007 71 0.08% 82.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32192-32199 1 0.00% 82.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32519 67 0.07% 82.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32775 652 0.72% 83.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33031 72 0.08% 83.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33287 3 0.00% 83.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33344-33351 1 0.00% 83.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33543 71 0.08% 83.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33799 386 0.43% 84.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34048-34055 141 0.16% 84.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34304-34311 125 0.14% 84.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34560-34567 72 0.08% 84.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34823 321 0.36% 84.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35072-35079 68 0.08% 85.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35328-35335 76 0.08% 85.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35584-35591 57 0.06% 85.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35847 321 0.36% 85.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36096-36103 131 0.14% 85.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36352-36359 129 0.14% 85.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36608-36615 128 0.14% 85.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36871 340 0.38% 86.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37120-37127 69 0.08% 86.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37376-37383 72 0.08% 86.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37632-37639 4 0.00% 86.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37696-37703 1 0.00% 86.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37895 269 0.30% 86.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37952-37959 1 0.00% 86.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38151 64 0.07% 86.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38400-38407 301 0.33% 87.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38592-38599 1 0.00% 87.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38656-38663 129 0.14% 87.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38919 455 0.50% 87.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39168-39175 69 0.08% 87.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39424-39431 67 0.07% 87.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39744-39751 1 0.00% 87.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39936-39943 262 0.29% 88.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40064-40071 1 0.00% 88.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40192-40199 67 0.07% 88.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40448-40455 129 0.14% 88.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40704-40711 66 0.07% 88.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40967 514 0.57% 89.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41152-41159 1 0.00% 89.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41223 65 0.07% 89.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41472-41479 129 0.14% 89.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41728-41735 68 0.08% 89.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-41991 264 0.29% 89.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42503 68 0.08% 89.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42759 69 0.08% 89.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43015 456 0.50% 90.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43271 132 0.15% 90.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43527 302 0.33% 90.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43776-43783 64 0.07% 90.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 267 0.30% 91.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44096-44103 1 0.00% 91.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44295 5 0.01% 91.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44551 71 0.08% 91.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44807 68 0.08% 91.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 341 0.38% 91.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45319 129 0.14% 91.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 130 0.14% 92.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 131 0.14% 92.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 321 0.36% 92.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46343 57 0.06% 92.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46464-46471 1 0.00% 92.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46599 74 0.08% 92.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 69 0.08% 92.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 320 0.35% 93.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47296-47303 1 0.00% 93.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 72 0.08% 93.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 128 0.14% 93.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 142 0.16% 93.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 391 0.43% 93.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 73 0.08% 94.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 1 0.00% 94.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 66 0.07% 94.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48960-48967 1 0.00% 94.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49024-49031 2 0.00% 94.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 2 0.00% 94.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 5357 5.93% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 90412 # Bytes accessed per row activation +system.physmem.totQLat 377428295750 # Total ticks spent queuing +system.physmem.totMemAccLat 474604408250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 78454415000 # Total ticks spent in databus transfers +system.physmem.totBankLat 18721697500 # Total ticks spent accessing banks +system.physmem.avgQLat 24053.99 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1193.16 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30243.87 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 30247.14 # Average memory access latency per DRAM burst system.physmem.avgRdBW 381.87 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.60 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 50.96 # Average system read bandwidth in MiByte/s @@ -492,13 +510,13 @@ system.physmem.busUtilRead 2.98 # Da system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing system.physmem.avgWrQLen 1.22 # Average write queue length when enqueuing -system.physmem.readRowHits 15616330 # Number of row buffer hits during reads -system.physmem.writeRowHits 90931 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads +system.physmem.readRowHits 15616374 # Number of row buffer hits during reads +system.physmem.writeRowHits 90932 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.53 # Row buffer hit rate for reads system.physmem.writeRowHitRate 85.11 # Row buffer hit rate for writes -system.physmem.avgGap 159351.16 # Average gap between requests +system.physmem.avgGap 159352.08 # Average gap between requests system.physmem.pageHitRate 99.43 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 2.39 # Percentage of time for which DRAM has all the banks in precharge state +system.physmem.prechargeAllPercent 2.38 # Percentage of time for which DRAM has all the banks in precharge state system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory @@ -511,259 +529,259 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 8 system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54426353 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16743636 # Transaction distribution -system.membus.trans_dist::ReadResp 16743636 # Transaction distribution +system.membus.throughput 54425977 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16743649 # Transaction distribution +system.membus.trans_dist::ReadResp 16743649 # Transaction distribution system.membus.trans_dist::WriteReq 763424 # Transaction distribution system.membus.trans_dist::WriteResp 763424 # Transaction distribution -system.membus.trans_dist::Writeback 57656 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4518 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4518 # Transaction distribution -system.membus.trans_dist::ReadExReq 131342 # Transaction distribution -system.membus.trans_dist::ReadExResp 131342 # Transaction distribution +system.membus.trans_dist::Writeback 57655 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4516 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4516 # Transaction distribution +system.membus.trans_dist::ReadExReq 131340 # Transaction distribution +system.membus.trans_dist::ReadExResp 131340 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382990 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3860 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1892570 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4279432 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1892587 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4279449 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 31064064 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 31064064 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 35343496 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 35343513 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390397 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7720 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16471520 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 18869661 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16471440 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 18869581 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 124256256 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 124256256 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 143125917 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 143125917 # Total data (bytes) +system.membus.tot_pkt_size::total 143125837 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 143125837 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1225680000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1225677000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3756000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3756500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 18171618500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 18171612500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4990533473 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4990561725 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 35075577250 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 35076949500 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 62046 # number of replacements -system.l2c.tags.tagsinuse 51605.865819 # Cycle average of tags in use -system.l2c.tags.total_refs 1699437 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 127429 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.336344 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2574782383500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 38213.733489 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000701 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 2749.245070 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3097.480060 # Average occupied blocks per requestor +system.l2c.tags.replacements 62045 # number of replacements +system.l2c.tags.tagsinuse 51605.891965 # Cycle average of tags in use +system.l2c.tags.total_refs 1699472 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 127428 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.336723 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2574797983500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 38210.959857 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000702 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 2799.685375 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3087.560110 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.000187 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4271.539066 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3273.867246 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.583095 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu1.inst 4221.092196 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3286.593539 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.583053 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.041950 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.047264 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.042720 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.047112 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.065179 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.049955 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.064409 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.050149 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.787443 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1024 65383 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2132 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6483 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2131 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6484 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::4 56716 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.997665 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 17277508 # Number of tag accesses -system.l2c.tags.data_accesses 17277508 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 9827 # number of ReadReq hits +system.l2c.tags.tag_accesses 17277894 # Number of tag accesses +system.l2c.tags.data_accesses 17277894 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 9810 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 3607 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 412393 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 183168 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 10051 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 3578 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 432141 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 187290 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1242055 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 596450 # number of Writeback hits -system.l2c.Writeback_hits::total 596450 # number of Writeback hits +system.l2c.ReadReq_hits::cpu0.inst 412170 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 183158 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 10090 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 3595 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 432364 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 187312 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1242106 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 596455 # number of Writeback hits +system.l2c.Writeback_hits::total 596455 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 13 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 13 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 57240 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 57291 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 114531 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 9827 # number of demand (read+write) hits +system.l2c.ReadExReq_hits::cpu0.data 57198 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 57329 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 114527 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 9810 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.itb.walker 3607 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 412393 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 240408 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 10051 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 3578 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 432141 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 244581 # number of demand (read+write) hits -system.l2c.demand_hits::total 1356586 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 9827 # number of overall hits +system.l2c.demand_hits::cpu0.inst 412170 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 240356 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 10090 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 3595 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 432364 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 244641 # number of demand (read+write) hits +system.l2c.demand_hits::total 1356633 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 9810 # number of overall hits system.l2c.overall_hits::cpu0.itb.walker 3607 # number of overall hits -system.l2c.overall_hits::cpu0.inst 412393 # number of overall hits -system.l2c.overall_hits::cpu0.data 240408 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 10051 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 3578 # number of overall hits -system.l2c.overall_hits::cpu1.inst 432141 # number of overall hits -system.l2c.overall_hits::cpu1.data 244581 # number of overall hits -system.l2c.overall_hits::total 1356586 # number of overall hits +system.l2c.overall_hits::cpu0.inst 412170 # number of overall hits +system.l2c.overall_hits::cpu0.data 240356 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 10090 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 3595 # number of overall hits +system.l2c.overall_hits::cpu1.inst 432364 # number of overall hits +system.l2c.overall_hits::cpu1.data 244641 # number of overall hits +system.l2c.overall_hits::total 1356633 # number of overall hits system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 4243 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 5343 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 4274 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 5319 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 6349 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 4883 # number of ReadReq misses -system.l2c.ReadReq_misses::total 20821 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1353 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1530 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2883 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 68272 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 64705 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 132977 # number of ReadExReq misses +system.l2c.ReadReq_misses::cpu1.inst 6318 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 4908 # number of ReadReq misses +system.l2c.ReadReq_misses::total 20822 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1344 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1536 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2880 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 68023 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 64953 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 132976 # number of ReadExReq misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 4243 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 73615 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 4274 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 73342 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 6349 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 69588 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 6318 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 69861 # number of demand (read+write) misses system.l2c.demand_misses::total 153798 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 4243 # number of overall misses -system.l2c.overall_misses::cpu0.data 73615 # number of overall misses +system.l2c.overall_misses::cpu0.inst 4274 # number of overall misses +system.l2c.overall_misses::cpu0.data 73342 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 6349 # number of overall misses -system.l2c.overall_misses::cpu1.data 69588 # number of overall misses +system.l2c.overall_misses::cpu1.inst 6318 # number of overall misses +system.l2c.overall_misses::cpu1.data 69861 # number of overall misses system.l2c.overall_misses::total 153798 # number of overall misses system.l2c.ReadReq_miss_latency::cpu0.itb.walker 149500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 301157500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 396109250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 306924500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 393478000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 89250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 450843500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 372813750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1521162750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 451089750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 373371500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1525102500 # number of ReadReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu0.data 232990 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu1.data 231990 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::total 464980 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 4857371220 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 4602598395 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 9459969615 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 4852191723 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 4623461391 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 9475653114 # number of ReadExReq miss cycles system.l2c.demand_miss_latency::cpu0.itb.walker 149500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 301157500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 5253480470 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 306924500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 5245669723 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.dtb.walker 89250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 450843500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 4975412145 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 10981132365 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 451089750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 4996832891 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 11000755614 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu0.itb.walker 149500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 301157500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 5253480470 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 306924500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 5245669723 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.dtb.walker 89250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 450843500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 4975412145 # number of overall miss cycles -system.l2c.overall_miss_latency::total 10981132365 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 9827 # number of ReadReq accesses(hits+misses) +system.l2c.overall_miss_latency::cpu1.inst 451089750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 4996832891 # number of overall miss cycles +system.l2c.overall_miss_latency::total 11000755614 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 9810 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.itb.walker 3609 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 416636 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 188511 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 10052 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 3578 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 438490 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 192173 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1262876 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 596450 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 596450 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 1366 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1543 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2909 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 125512 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 121996 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 247508 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 9827 # number of demand (read+write) accesses +system.l2c.ReadReq_accesses::cpu0.inst 416444 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 188477 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 10091 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 3595 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 438682 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 192220 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1262928 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 596455 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 596455 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 1357 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 1549 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2906 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 125221 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 122282 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 247503 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 9810 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.itb.walker 3609 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 416636 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 314023 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 10052 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 3578 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 438490 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 314169 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1510384 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 9827 # number of overall (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 416444 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 313698 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 10091 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 3595 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 438682 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 314502 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1510431 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 9810 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.itb.walker 3609 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 416636 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 314023 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 10052 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 3578 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 438490 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 314169 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1510384 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 416444 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 313698 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 10091 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 3595 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 438682 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 314502 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1510431 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000554 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.010184 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.028343 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.010263 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.028221 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000099 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.014479 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.025409 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.014402 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.025533 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::total 0.016487 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.990483 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.991575 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.991062 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.543948 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.530386 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.537263 # miss rate for ReadExReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.990420 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.991607 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.991053 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.543224 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.531174 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.537270 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.itb.walker 0.000554 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.010184 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.234426 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.010263 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.233798 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000099 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.014479 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.221499 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.101827 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.014402 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.222132 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.101824 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.itb.walker 0.000554 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.010184 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.234426 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.010263 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.233798 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000099 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.014479 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.221499 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.101827 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.014402 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.222132 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.101824 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 74750 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 70977.492340 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 74136.112671 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 71812.002808 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 73975.935326 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 89250 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 71010.159080 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 76349.324186 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 73059.062965 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 172.202513 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 151.627451 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 161.283385 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 71147.340345 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 71132.036087 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 71139.893478 # average ReadExReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 71397.554606 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 76074.062755 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 73244.765152 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 173.355655 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 151.035156 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 161.451389 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 71331.633756 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 71181.645051 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 71258.370789 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu0.itb.walker 74750 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 70977.492340 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 71364.266386 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 71812.002808 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 71523.407093 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 89250 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 71010.159080 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 71498.133946 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 71399.708481 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 71397.554606 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 71525.355935 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 71527.299536 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.itb.walker 74750 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 70977.492340 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 71364.266386 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 71812.002808 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 71523.407093 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 89250 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 71010.159080 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 71498.133946 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 71399.708481 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 71397.554606 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 71525.355935 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 71527.299536 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -772,129 +790,129 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 57656 # number of writebacks -system.l2c.writebacks::total 57656 # number of writebacks +system.l2c.writebacks::writebacks 57655 # number of writebacks +system.l2c.writebacks::total 57655 # number of writebacks system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 4243 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 5343 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 4274 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 5319 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 6349 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 4883 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 20821 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 1353 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 1530 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 2883 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 68272 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 64705 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 132977 # number of ReadExReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 6318 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 4908 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 20822 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 1344 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 1536 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 2880 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 68023 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 64953 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 132976 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 4243 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 73615 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 4274 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 73342 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.dtb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 6349 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 69588 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 6318 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 69861 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::total 153798 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 4243 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 73615 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 4274 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 73342 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.dtb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 6349 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 69588 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 6318 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 69861 # number of overall MSHR misses system.l2c.overall_mshr_misses::total 153798 # number of overall MSHR misses system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 125000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 247421000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 329573750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 252789500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 327242500 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 76250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 370327500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 311886250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1259409750 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 13531353 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 15301530 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 28832883 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3982762780 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3773110105 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 7755872885 # number of ReadExReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 370964750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 312158000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1263356000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 13441344 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 15361536 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 28802880 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3980747277 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3790800609 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 7771547886 # number of ReadExReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 125000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 247421000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 4312336530 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 252789500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 4307989777 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 76250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 370327500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 4084996355 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 9015282635 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 370964750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 4102958609 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 9034903886 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 125000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 247421000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 4312336530 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 252789500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 4307989777 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 76250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 370327500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 4084996355 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 9015282635 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 343871250 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 83755912750 # number of ReadReq MSHR uncacheable cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 370964750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 4102958609 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 9034903886 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 344358750 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 83697263750 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 842500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 82922372500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 167022999000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 8435630009 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8264647000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 16700277009 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 343871250 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 92191542759 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 82980883500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 167023348500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 8440281008 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8259993501 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 16700274509 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 344358750 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 92137544758 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 842500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 91187019500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 183723276009 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 91240877001 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 183723623009 # number of overall MSHR uncacheable cycles system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000554 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.010184 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.028343 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.010263 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.028221 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000099 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.014479 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.025409 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.014402 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.025533 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total 0.016487 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.990483 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.991575 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.991062 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.543948 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.530386 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.537263 # mshr miss rate for ReadExReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.990420 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.991607 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.991053 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.543224 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.531174 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.537270 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000554 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.010184 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.234426 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.010263 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.233798 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000099 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.014479 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.221499 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.101827 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.014402 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.222132 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.101824 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000554 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.010184 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.234426 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.010263 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.233798 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000099 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.014479 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.221499 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.101827 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.014402 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.222132 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.101824 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 58312.750412 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61683.277185 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59145.882078 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61523.312653 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58328.476926 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63871.851321 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 60487.476586 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58715.534979 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63601.874491 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 60674.094708 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 58336.694106 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58312.496793 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 58324.919986 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 58520.607397 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58362.209736 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 58443.237020 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 58312.750412 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 58579.590165 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59145.882078 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 58738.373333 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58328.476926 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58702.597502 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 58617.684463 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58715.534979 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58730.316042 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 58745.262526 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 58312.750412 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 58579.590165 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59145.882078 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 58738.373333 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58328.476926 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58702.597502 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 58617.684463 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58715.534979 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58730.316042 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 58745.262526 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -915,39 +933,39 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 52790683 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2471881 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2471881 # Transaction distribution +system.toL2Bus.throughput 52790764 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2471959 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2471959 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 763424 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 763424 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 596450 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2909 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2909 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 247508 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 247508 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1725145 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5753790 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20211 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 50526 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7549672 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 54754616 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 83791781 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 28748 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 79516 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 138654661 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 138654661 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 169908 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4808598000 # Layer occupancy (ticks) +system.toL2Bus.trans_dist::Writeback 596455 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2906 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2906 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 247503 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 247503 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1725165 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5753809 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20259 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 50570 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7549803 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 54754656 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 83792621 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 28816 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 79604 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 138655697 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 138655697 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 169964 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4808655500 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3865648250 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 3865656500 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4421117527 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4421145525 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 13024000 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 13055000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 30647250 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 30669250 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48159799 # Throughput (bytes/s) +system.iobus.throughput 48159493 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 16715360 # Transaction distribution system.iobus.trans_dist::ReadResp 16715360 # Transaction distribution system.iobus.trans_dist::WriteReq 8167 # Transaction distribution @@ -1057,147 +1075,189 @@ system.iobus.reqLayer25.occupancy 15532032000 # La system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) system.iobus.respLayer0.occupancy 2374823000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42583673750 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42582472500 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) +system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7421376 # DTB read hits -system.cpu0.dtb.read_misses 6854 # DTB read misses -system.cpu0.dtb.write_hits 5628030 # DTB write hits -system.cpu0.dtb.write_misses 1815 # DTB write misses -system.cpu0.dtb.flush_tlb 1247 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 7421892 # DTB read hits +system.cpu0.dtb.read_misses 6825 # DTB read misses +system.cpu0.dtb.write_hits 5624028 # DTB write hits +system.cpu0.dtb.write_misses 1832 # DTB write misses +system.cpu0.dtb.flush_tlb 2493 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 673 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 666 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 6418 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 6408 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 151 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 143 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 219 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7428230 # DTB read accesses -system.cpu0.dtb.write_accesses 5629845 # DTB write accesses +system.cpu0.dtb.perms_faults 218 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 7428717 # DTB read accesses +system.cpu0.dtb.write_accesses 5625860 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 13049406 # DTB hits -system.cpu0.dtb.misses 8669 # DTB misses -system.cpu0.dtb.accesses 13058075 # DTB accesses -system.cpu0.itb.inst_hits 30610107 # ITB inst hits -system.cpu0.itb.inst_misses 3562 # ITB inst misses +system.cpu0.dtb.hits 13045920 # DTB hits +system.cpu0.dtb.misses 8657 # DTB misses +system.cpu0.dtb.accesses 13054577 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.itb.inst_hits 30611798 # ITB inst hits +system.cpu0.itb.inst_misses 3559 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 1247 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 2493 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 673 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 666 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2748 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2782 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 30613669 # ITB inst accesses -system.cpu0.itb.hits 30610107 # DTB hits -system.cpu0.itb.misses 3562 # DTB misses -system.cpu0.itb.accesses 30613669 # DTB accesses -system.cpu0.numCycles 2628235952 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 30615357 # ITB inst accesses +system.cpu0.itb.hits 30611798 # DTB hits +system.cpu0.itb.misses 3559 # DTB misses +system.cpu0.itb.accesses 30615357 # DTB accesses +system.cpu0.numCycles 2628262709 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 29990580 # Number of instructions committed -system.cpu0.committedOps 38158663 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 34282971 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 4584 # Number of float alu accesses -system.cpu0.num_func_calls 1059870 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 3968282 # number of instructions that are conditional controls -system.cpu0.num_int_insts 34282971 # number of integer instructions -system.cpu0.num_fp_insts 4584 # number of float instructions -system.cpu0.num_int_register_reads 196555242 # number of times the integer registers were read -system.cpu0.num_int_register_writes 36964020 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3346 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1240 # number of times the floating registers were written -system.cpu0.num_mem_refs 13622094 # number of memory refs -system.cpu0.num_load_insts 7743834 # Number of load instructions -system.cpu0.num_store_insts 5878260 # Number of store instructions -system.cpu0.num_idle_cycles 2282805163.828333 # Number of idle cycles -system.cpu0.num_busy_cycles 345430788.171666 # Number of busy cycles -system.cpu0.not_idle_fraction 0.131431 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.868569 # Percentage of idle cycles +system.cpu0.committedInsts 29989968 # Number of instructions committed +system.cpu0.committedOps 38153430 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 34435324 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 4807 # Number of float alu accesses +system.cpu0.num_func_calls 1060090 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 3967783 # number of instructions that are conditional controls +system.cpu0.num_int_insts 34435324 # number of integer instructions +system.cpu0.num_fp_insts 4807 # number of float instructions +system.cpu0.num_int_register_reads 199674548 # number of times the integer registers were read +system.cpu0.num_int_register_writes 37122022 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3633 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1176 # number of times the floating registers were written +system.cpu0.num_mem_refs 13619078 # number of memory refs +system.cpu0.num_load_insts 7744657 # Number of load instructions +system.cpu0.num_store_insts 5874421 # Number of store instructions +system.cpu0.num_idle_cycles 2288628005.429596 # Number of idle cycles +system.cpu0.num_busy_cycles 339634703.570404 # Number of busy cycles +system.cpu0.not_idle_fraction 0.129224 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.870776 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 83029 # number of quiesce instructions executed system.cpu0.icache.tags.replacements 856230 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.853093 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 60649685 # Total number of references to valid blocks. +system.cpu0.icache.tags.tagsinuse 510.852804 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 60649877 # Total number of references to valid blocks. system.cpu0.icache.tags.sampled_refs 856742 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 70.791072 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 20173406250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 217.243034 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 293.610060 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.424303 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.573457 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.997760 # Average percentage of cache occupancy +system.cpu0.icache.tags.avg_refs 70.791297 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 20177865250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 217.225698 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 293.627106 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.424269 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.573490 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.997759 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 266 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 62363171 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 62363171 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 30192721 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 30456964 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 60649685 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 30192721 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 30456964 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 60649685 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 30192721 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 30456964 # number of overall hits -system.cpu0.icache.overall_hits::total 60649685 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 417386 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 439357 # number of ReadReq misses +system.cpu0.icache.tags.tag_accesses 62363363 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 62363363 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 30194610 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 30455267 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 60649877 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 30194610 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 30455267 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 60649877 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 30194610 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 30455267 # number of overall hits +system.cpu0.icache.overall_hits::total 60649877 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 417188 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 439555 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 856743 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 417386 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 439357 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu0.inst 417188 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 439555 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 856743 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 417386 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 439357 # number of overall misses +system.cpu0.icache.overall_misses::cpu0.inst 417188 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 439555 # number of overall misses system.cpu0.icache.overall_misses::total 856743 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5696153000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6111476500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 11807629500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5696153000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 6111476500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 11807629500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5696153000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 6111476500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 11807629500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 30610107 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 30896321 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 61506428 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 30610107 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 30896321 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 61506428 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 30610107 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 30896321 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 61506428 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013636 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014220 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5699086500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6114552750 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 11813639250 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5699086500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 6114552750 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 11813639250 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5699086500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 6114552750 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 11813639250 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 30611798 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 30894822 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 61506620 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 30611798 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 30894822 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 61506620 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 30611798 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 30894822 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 61506620 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013628 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014227 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::total 0.013929 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013636 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014220 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013628 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014227 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total 0.013929 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013636 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014220 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013628 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014227 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.013929 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13647.206662 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13910.046955 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13781.997052 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13647.206662 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13910.046955 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13781.997052 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13647.206662 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13910.046955 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13781.997052 # average overall miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13660.715313 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13910.779652 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13789.011699 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13660.715313 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13910.779652 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13789.011699 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13660.715313 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13910.779652 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13789.011699 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1206,48 +1266,48 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 417386 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 439357 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 417188 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 439555 # number of ReadReq MSHR misses system.cpu0.icache.ReadReq_mshr_misses::total 856743 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 417386 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 439357 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 417188 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 439555 # number of demand (read+write) MSHR misses system.cpu0.icache.demand_mshr_misses::total 856743 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 417386 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 439357 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 417188 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 439555 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 856743 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4859799000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5230292500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 10090091500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4859799000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5230292500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 10090091500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4859799000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5230292500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 10090091500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 435321250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4863118500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5232991250 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 10096109750 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4863118500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5232991250 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 10096109750 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4863118500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5232991250 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 10096109750 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 435943750 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 1072500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 436393750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 435321250 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 437016250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 435943750 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 1072500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 436393750 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013636 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014220 # mshr miss rate for ReadReq accesses +system.cpu0.icache.overall_mshr_uncacheable_latency::total 437016250 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013628 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014227 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013929 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013636 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.014220 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013628 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.014227 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total 0.013929 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013636 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.014220 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013628 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.014227 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total 0.013929 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11643.416406 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11904.425103 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11777.267512 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11643.416406 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11904.425103 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11777.267512 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11643.416406 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11904.425103 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11777.267512 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11656.899288 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11905.202421 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11784.292081 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11656.899288 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11905.202421 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11784.292081 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11656.899288 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11905.202421 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11784.292081 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1255,120 +1315,120 @@ system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 627680 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.877363 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 23660930 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 628192 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 37.665125 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 664004250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 184.794485 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 327.082879 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.360927 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.638834 # Average percentage of cache occupancy +system.cpu0.dcache.tags.replacements 627688 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.877185 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 23660968 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 628200 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 37.664706 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 664900250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 184.764796 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 327.112389 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.360869 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.638891 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999760 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 330 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 109 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 97784680 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 97784680 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6519451 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 6679636 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13199087 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4994316 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 4980652 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 9974968 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 118550 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 117644 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 236194 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 124564 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 123208 # number of StoreCondReq hits +system.cpu0.dcache.tags.tag_accesses 97784872 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 97784872 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6520567 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 6678544 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 13199111 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4990810 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 4984176 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 9974986 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 118420 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 117773 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 236193 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 124411 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 123361 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 247772 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 11513767 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 11660288 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 23174055 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 11513767 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 11660288 # number of overall hits -system.cpu0.dcache.overall_hits::total 23174055 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 182495 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 186610 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 369105 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 126878 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 123539 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 250417 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6016 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 5563 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 11579 # number of LoadLockedReq misses -system.cpu0.dcache.demand_misses::cpu0.data 309373 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 310149 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 619522 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 309373 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 310149 # number of overall misses -system.cpu0.dcache.overall_misses::total 619522 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2725951250 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2755941500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5481892750 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5868624133 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 5606519635 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 11475143768 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 81127500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 79383250 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 160510750 # number of LoadLockedReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 8594575383 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 8362461135 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 16957036518 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 8594575383 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 8362461135 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 16957036518 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6701946 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 6866246 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 13568192 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5121194 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 5104191 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 10225385 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 124566 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 123207 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.demand_hits::cpu0.data 11511377 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 11662720 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 23174097 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 11511377 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 11662720 # number of overall hits +system.cpu0.dcache.overall_hits::total 23174097 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 182487 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 186630 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 369117 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 126578 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 123831 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 250409 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 5990 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 5590 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 11580 # number of LoadLockedReq misses +system.cpu0.dcache.demand_misses::cpu0.data 309065 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 310461 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 619526 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 309065 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 310461 # number of overall misses +system.cpu0.dcache.overall_misses::total 619526 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2723439500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2756826750 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5480266250 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5861796621 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 5628899645 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 11490696266 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 80813500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 79398250 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 160211750 # number of LoadLockedReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 8585236121 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 8385726395 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 16970962516 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 8585236121 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 8385726395 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 16970962516 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6703054 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 6865174 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 13568228 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5117388 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 5108007 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 10225395 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 124410 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 123363 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 247773 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 124564 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 123208 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 124411 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 123361 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 247772 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 11823140 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 11970437 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 23793577 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 11823140 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 11970437 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 23793577 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.027230 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.027178 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.027204 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.024775 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.024203 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.024490 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048296 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.045152 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.046732 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026167 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.025910 # miss rate for demand accesses +system.cpu0.dcache.demand_accesses::cpu0.data 11820442 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 11973181 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 23793623 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 11820442 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 11973181 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 23793623 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.027224 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.027185 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.027205 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.024735 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.024243 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.024489 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048147 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.045313 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.046736 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026147 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.025930 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total 0.026037 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026167 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.025910 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026147 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.025930 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total 0.026037 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14937.128414 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14768.455603 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14851.851777 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 46254.071888 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 45382.588778 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 45824.140406 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13485.289229 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14269.863383 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13862.229035 # average LoadLockedReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 27780.625274 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 26962.721579 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 27371.161182 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 27780.625274 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 26962.721579 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 27371.161182 # average overall miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14924.019245 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14771.616300 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14846.962481 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 46309.758576 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 45456.304520 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 45887.712766 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13491.402337 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14203.622540 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13835.211572 # average LoadLockedReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 27778.092379 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27010.562985 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 27393.462931 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 27778.092379 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 27010.562985 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 27393.462931 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1377,77 +1437,77 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 596450 # number of writebacks -system.cpu0.dcache.writebacks::total 596450 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 182495 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 186610 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 369105 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 126878 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 123539 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 250417 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6016 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5563 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 11579 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 309373 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 310149 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 619522 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 309373 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 310149 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 619522 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2359626750 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2381686500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4741313250 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5588242867 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 5334624365 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10922867232 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69088500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 68209750 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 137298250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7947869617 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7716310865 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 15664180482 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7947869617 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7716310865 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 15664180482 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91489795250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90582792250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182072587500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13259276491 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 12977158000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26236434491 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 104749071741 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103559950250 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 208309021991 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027230 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027178 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.027204 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.024775 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.024203 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024490 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.048296 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.045152 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046732 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026167 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025910 # mshr miss rate for demand accesses +system.cpu0.dcache.writebacks::writebacks 596455 # number of writebacks +system.cpu0.dcache.writebacks::total 596455 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 182487 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 186630 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 369117 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 126578 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 123831 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 250409 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 5990 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5590 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 11580 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 309065 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 310461 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 619526 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 309065 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 310461 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 619526 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2357134500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2382546250 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4739680750 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5582137379 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 5356296355 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10938433734 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 68828500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 68170750 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 136999250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7939271879 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7738842605 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 15678114484 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7939271879 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7738842605 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 15678114484 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91425467750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90647011250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182072479000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13263386492 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 12973041499 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26236427991 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 104688854242 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103620052749 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 208308906991 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027224 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027185 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.027205 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.024735 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.024243 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024489 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.048147 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.045313 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046736 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026147 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025930 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total 0.026037 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026167 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025910 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026147 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025930 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.026037 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12929.815885 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12762.909276 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12845.432194 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44044.222537 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 43181.702661 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43618.712915 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11484.125665 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12261.324825 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11857.522239 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25690.249689 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24879.367223 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25284.300609 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25690.249689 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24879.367223 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25284.300609 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12916.725575 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12766.148261 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12840.591872 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44100.375887 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 43254.890577 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43682.270741 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11490.567613 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12195.125224 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11830.677893 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25688.032870 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24926.939632 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25306.628752 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25688.032870 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24926.939632 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25306.628752 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1458,70 +1518,112 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 7578699 # DTB read hits -system.cpu1.dtb.read_misses 7251 # DTB read misses -system.cpu1.dtb.write_hits 5604812 # DTB write hits -system.cpu1.dtb.write_misses 1846 # DTB write misses -system.cpu1.dtb.flush_tlb 1247 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 7578222 # DTB read hits +system.cpu1.dtb.read_misses 7256 # DTB read misses +system.cpu1.dtb.write_hits 5608824 # DTB write hits +system.cpu1.dtb.write_misses 1858 # DTB write misses +system.cpu1.dtb.flush_tlb 2493 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 766 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 773 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 6708 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 6698 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 153 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 144 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 233 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 7585950 # DTB read accesses -system.cpu1.dtb.write_accesses 5606658 # DTB write accesses +system.cpu1.dtb.perms_faults 234 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 7585478 # DTB read accesses +system.cpu1.dtb.write_accesses 5610682 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 13183511 # DTB hits -system.cpu1.dtb.misses 9097 # DTB misses -system.cpu1.dtb.accesses 13192608 # DTB accesses -system.cpu1.itb.inst_hits 30896338 # ITB inst hits -system.cpu1.itb.inst_misses 3789 # ITB inst misses +system.cpu1.dtb.hits 13187046 # DTB hits +system.cpu1.dtb.misses 9114 # DTB misses +system.cpu1.dtb.accesses 13196160 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.itb.inst_hits 30894839 # ITB inst hits +system.cpu1.itb.inst_misses 3806 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 1247 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 2493 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 766 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 773 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2857 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2929 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 30900127 # ITB inst accesses -system.cpu1.itb.hits 30896338 # DTB hits -system.cpu1.itb.misses 3789 # DTB misses -system.cpu1.itb.accesses 30900127 # DTB accesses -system.cpu1.numCycles 2631198481 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 30898645 # ITB inst accesses +system.cpu1.itb.hits 30894839 # DTB hits +system.cpu1.itb.misses 3806 # DTB misses +system.cpu1.itb.accesses 30898645 # DTB accesses +system.cpu1.numCycles 2631205114 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 30221754 # Number of instructions committed -system.cpu1.committedOps 38460770 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 34602143 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 5685 # Number of float alu accesses -system.cpu1.num_func_calls 1080538 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3981203 # number of instructions that are conditional controls -system.cpu1.num_int_insts 34602143 # number of integer instructions -system.cpu1.num_fp_insts 5685 # number of float instructions -system.cpu1.num_int_register_reads 198301383 # number of times the integer registers were read -system.cpu1.num_int_register_writes 37233535 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 4147 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1540 # number of times the floating registers were written -system.cpu1.num_mem_refs 13778426 # number of memory refs -system.cpu1.num_load_insts 7920474 # Number of load instructions -system.cpu1.num_store_insts 5857952 # Number of store instructions -system.cpu1.num_idle_cycles 2292395060.642381 # Number of idle cycles -system.cpu1.num_busy_cycles 338803420.357619 # Number of busy cycles -system.cpu1.not_idle_fraction 0.128764 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.871236 # Percentage of idle cycles +system.cpu1.committedInsts 30222584 # Number of instructions committed +system.cpu1.committedOps 38466237 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 34785148 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 5462 # Number of float alu accesses +system.cpu1.num_func_calls 1080322 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 3981720 # number of instructions that are conditional controls +system.cpu1.num_int_insts 34785148 # number of integer instructions +system.cpu1.num_fp_insts 5462 # number of float instructions +system.cpu1.num_int_register_reads 201769035 # number of times the integer registers were read +system.cpu1.num_int_register_writes 37410979 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 3860 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1604 # number of times the floating registers were written +system.cpu1.num_mem_refs 13781482 # number of memory refs +system.cpu1.num_load_insts 7919681 # Number of load instructions +system.cpu1.num_store_insts 5861801 # Number of store instructions +system.cpu1.num_idle_cycles 2292298207.924829 # Number of idle cycles +system.cpu1.num_busy_cycles 338906906.075172 # Number of busy cycles +system.cpu1.not_idle_fraction 0.128803 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.871197 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.iocache.tags.replacements 0 # number of replacements @@ -1540,10 +1642,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1557221573750 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1557221573750 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1557221573750 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1557221573750 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1557253805500 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1557253805500 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1557253805500 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1557253805500 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency |